JP4438389B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
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- 229910052710 silicon Inorganic materials 0.000 description 18
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
請求項2に記載の発明は、請求項1に記載の発明において、前記第1絶縁層をガラス繊維に熱硬化性樹脂を含浸させたものによって形成することを特徴とするものである。
請求項3に記載の発明は、請求項1に記載の発明において、前記上層再配線のうちのいずれかの層の上層再配線と、前記下層再配線のうちのいずれかの層の下層再配線と、前記上下導通部と、を同時に形成することを特徴とするものである。
請求項4に記載の発明は、請求項1に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項5に記載の発明は、請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項6に記載の発明は、請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とするものである。
請求項7に記載の発明は、請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とするものである。
請求項8に記載の発明は、請求項1に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う最上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項9に記載の発明は、請求項8に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とするものである。
請求項10に記載の発明は、請求項1に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う最下層絶縁膜を形成する工程を有することを特徴とするものである。
請求項11に記載の発明は、請求項10に記載の発明において、前記最下層絶縁膜下に電子部品を前記最下層の下層再配線の接続パッド部に接続させて設ける工程を有することを特徴とするものである。
請求項12に記載の発明は、請求項1に記載の発明において、前記上下導通部を形成するとき、前記上下導通部を前記上層配線および前記下層配線に接続することを特徴とするものである。
請求項13に記載の発明は、請求項1に記載の発明において、前記上層再配線の層数と前記下層再配線の層数とを同じとすることを特徴とする半導ものである。
2 上層配線
3 下層配線
4 半導体構成体
5 接着層
6 シリコン基板
7 接続パッド
13 再配線
14 柱状電極
15 封止膜
16 絶縁層
17 第1の上層絶縁膜
20 第1の上層再配線
21 第2の上層絶縁膜
24 第2の上層再配線
25 最上層絶縁膜
27 半田ボール
31 第1の下層絶縁膜
33 第1の下層再配線
34 第2の下層絶縁膜
37 第2の下層再配線
38 最下層絶縁膜
40 半導体構成体
42 貫通孔
43 上下導通部
Claims (13)
- ベース板上に、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記半導体構成体の周囲における前記ベース板上に、基材に樹脂を含浸させてなるものを配置して加熱加圧することによって第1絶縁層を形成する工程と、
前記半導体構成体及び前記第1絶縁層上に第2絶縁層を形成する工程と、
接続パッド部を有し、且つ、少なくとも一部がいずれかの前記半導体構成体の前記外部接続用電極に接続される少なくとも1層の上層再配線を、該上層再配線のうち、最上層の上層再配線の接続パッド部が前記第1絶縁層の上方に配置されるように形成する工程と、
前記ベース板下に少なくとも1層の下層再配線を形成する工程と、
前記第1絶縁層および前記ベース板に形成された貫通孔内に前記上層再配線の少なくとも一部と前記下層再配線の少なくとも一部とを接続する上下導通部を形成する工程と、
前記半導体構成体間における前記第1絶縁層および前記ベース板を切断して前記最上層の上層再配線の接続パッド部が前記第1絶縁層上に配置された半導体装置を複数個得る工程と、
を有し、
前記ベース板の上下面にそれぞれ上層配線および下層配線が設けられ、前記上層配線と前記下層配線とのうちの一方はグラウンド配線であり、他方は電源配線であることを特徴とする半導体装置の製造方法。 - 請求項1に記載の発明において、前記第1絶縁層をガラス繊維に熱硬化性樹脂を含浸させたものによって形成することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記上層再配線のうちのいずれかの層の上層再配線と、前記下層再配線のうちのいずれかの層の下層再配線と、前記上下導通部と、を同時に形成することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項8に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う最下層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項10に記載の発明において、前記最下層絶縁膜下に電子部品を前記最下層の下層再配線の接続パッド部に接続させて設ける工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記上下導通部を形成するとき、前記上下導通部を前記上層配線および前記下層配線に接続することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記上層再配線の層数と前記下層再配線の層数とを同じとすることを特徴とする半導体装置の製造方法。
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JP4343727B2 (ja) * | 2004-02-13 | 2009-10-14 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2006173232A (ja) * | 2004-12-14 | 2006-06-29 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP4534927B2 (ja) * | 2005-09-27 | 2010-09-01 | カシオ計算機株式会社 | 半導体装置 |
CN101288351B (zh) | 2005-10-14 | 2011-04-20 | 株式会社藤仓 | 印刷布线基板及印刷布线基板的制造方法 |
KR100851072B1 (ko) * | 2007-03-02 | 2008-08-12 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
JP5193503B2 (ja) * | 2007-06-04 | 2013-05-08 | 新光電気工業株式会社 | 貫通電極付き基板及びその製造方法 |
KR100881400B1 (ko) * | 2007-09-10 | 2009-02-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
JP2009231328A (ja) * | 2008-03-19 | 2009-10-08 | Dainippon Printing Co Ltd | 電子モジュール |
US8441133B2 (en) * | 2009-03-31 | 2013-05-14 | Ibiden Co., Ltd. | Semiconductor device |
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