CN105304582B - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105304582B
CN105304582B CN201410383922.5A CN201410383922A CN105304582B CN 105304582 B CN105304582 B CN 105304582B CN 201410383922 A CN201410383922 A CN 201410383922A CN 105304582 B CN105304582 B CN 105304582B
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layer
load
bearing part
encapsulating structure
preparation
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CN105304582A (zh
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邱志贤
钟兴隆
张卓兴
陈嘉扬
杨超雅
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装结构及其制法，封装结构，包括：承载件、设于该承载件上的电子元件、包覆该电子元件的封装层、形成于该封装层上的一第一屏蔽层、以及形成于该第一屏蔽层上的至少一第二屏蔽层，且该第一屏蔽层与该第二屏蔽层为不同材质，藉由在该封装层上形成多层屏蔽层，以避免该电子元件受电磁波干扰。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构，尤指一种具防电磁波干扰的封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，大部份的电子产品均朝向小型化及高速化的目标发展，尤其是通讯产业的发展已普遍运用整合于各类电子产品，例如行动电话(Cell phone)、膝上型电脑(laptop)等。然而上述的电子产品需使用高频的射频晶片，且射频晶片可能相邻设置数位积体电路、数位讯号处理器(Digital Signal Processor，简称DSP)或基频晶片(BB,Base Band)，造成电磁干扰(Electromagnetic Interference，简称EMI)产生的现象，因此必需进行电磁屏蔽(Electromagnetic Shielding)处理。
现有避免EMI的射频(Radio frequency，简称RF)模组，如图1A至图1C所示，该射频模组1用于将多个射频晶片11a,11b与非射频式电子元件11电性连接在一封装基板10上，再以如环氧树脂的封装层13包覆各该射频晶片11a,11b与该非射频式电子元件11，并于该封装层13上形成一金属薄膜14。该射频模组1藉由该封装层13保护该射频晶片11a,11b、非射频式电子元件11及封装基板10，并避免外界水气或污染物的侵害，且藉由该金属薄膜14保护该些射频晶片11a,11b免受外界EMI影响。
惟，现有射频模组1的外围虽可藉由包覆该金属薄膜14以达到避免EMI的目的，但若射频晶片11a,11b如为低频元件，则单一金属薄膜14作为屏障层难以防止电磁干扰。
因此，如何克服现有技术的缺失，实为一重要课题。
发明内容
为克服现有技术的种种缺失，本发明提供一种封装结构及其制法，藉由在封装层上形成多层屏蔽层，以避免该电子元件受电磁波干扰。
本发明的封装结构，包括：一承载件；至少一电子元件，其设于该承载件上；封装层，其包覆该电子元件；一第一屏蔽层，其形成于该封装层上；以及至少一第二屏蔽层，其形成于该第一屏蔽层上，且该第一与第二屏蔽层为不同材质所形成。
本发明还提供一种封装结构的制法，包括：提供一封装体，该封装体具有一承载件、设于该承载件上的至少一电子元件及包覆该电子元件的封装层；形成一第一屏蔽层于该封装层上；以及形成至少一第二屏蔽层于该第一屏蔽层上，且该第一屏蔽层与该第二屏蔽层为不同材质所形成。
前述的制法中，当该封装体具有多个该电子元件时，该封装体定义有多个封装单元，且各该封装单元具有至少一该电子元件。因此，还包括先形成多个沟道于各该封装单元之间；再形成该第一屏蔽层于该封装层上与各该沟道中；沿各该沟道进行切单制程，以分离各该封装单元，且该第一屏蔽层保留于各该封装单元上；以及之后形成该第二屏蔽层于该第一屏蔽层上。
前述的封装结构及其制法中，该电子元件为射频晶片。
前述的封装结构及其制法中，形成该第一屏蔽层的材质为绝缘材或导电材，且形成该第二屏蔽层的材质为导体材。
前述的封装结构及其制法中，该沟道贯穿该封装层、或该沟道延伸至该承载件内，例如，该第一屏蔽层复沿该沟道的表面形成、或该第一屏蔽层填满该沟道。因此，该第一屏蔽层复延伸至该承载件上，且该承载件的边缘成为阶梯部，而该第一屏蔽层复覆盖该阶梯部，使该第一屏蔽层对应该阶梯部之处呈现阶梯状、或该第一屏蔽层的侧表面齐平该承载件的侧表面。
由上可知，本发明的封装结构及其制法，藉由该封装层上形成第一与第二屏蔽层的多个屏蔽层，以提升屏蔽功效，所以可避免该电子元件受外部电磁波干扰的问题。
附图说明
图1A至图1C为现有射频模组的制法的剖面示意图；
图2A至图2F为本发明封装结构的制法的第一实施例的剖面示意图；其中，图2D’为图2D的另一实施例，图2F’为图2F的另一实施例；
图3A至图3B为本发明封装结构的制法的第二实施例的剖面示意图；其中，图3B’为图3B的另一实施例；
图4A至图4B为本发明封装结构的制法的第三实施例的剖面示意图；以及
图5为本发明封装结构的制法的第四实施例的剖面示意图。
符号说明
1 射频模组
10 封装基板
11 非射频式电子元件
11a,11b 射频晶片
13,23 封装层
14 金属薄膜
2,2’,3,3’,4,5 封装结构
2a,4a 封装体
2b 封装单元
20,40 承载件
20a 上表面
20b 下表面
20c,23c,24a,40c 侧表面
200 电性接触垫
201 绝缘保护层
21,41,51 电子元件
210 焊线
22,22’ 阶梯部
23a 第一表面
23b 第二表面
24,24’ 第一屏蔽层
25,55 第二屏蔽层
230,330 沟道
410 焊球。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明封装结构的制法的第一实施例的剖面示意图。于本实施例中，所述的封装结构2可发出电磁波者，例如为射频(Radio frequency,RF)模组。
如图2A所示，提供一具有上表面20a及下表面20b的承载件20，再接置多个电子元件21于该承载件20的上表面20a上。
所述的承载件20的上表面20a具有线路层与绝缘保护层201，该线路层包含多个外露于该绝缘保护层201的电性接触垫200。于本实施例中，该承载件20的种类繁多，例如，该承载件20的内部可包含介电层(图略)、接地部(图略)与内部线路(图略)，且该内部线路可选择性地电性连接该电性接触垫200，因而该承载件20的构造并无特别限制。
所述的电子元件21为射频晶片或其它半导体晶片，例如：蓝芽晶片或Wi-Fi(Wireless Fidelity)晶片。于本实施例中，该些电子元件21为蓝芽晶片或Wi-Fi晶片，且也可于该承载件20的上表面20a上设置其它无影响电磁波干扰的电子元件(图略)。
此外，该电子元件21为打线式晶片，即藉由多个焊线210对应电性连接该承载件20的电性接触垫200。
如图2B所示，形成一封装层23于该承载件20的上表面20a上，以包覆各该电子元件21，藉以形成一封装体2a。
于本实施例中，该封装层23例如为封装胶体，其具有相对的第一表面23a及第二表面23b，且该封装层23以其第二表面23b结合至该承载件20的上表面20a。
此外，各该电子元件21并未外露于该封装层23的第一表面23a。
又，该封装体2a定义有多个封装单元2b，且各该封装单元2b具有至少一该电子元件21。
如图2C所示，形成多个沟道230于各该封装单元2b之间，以令该承载件20的部分上表面20a外露于该些沟道230。
于本实施例中，该沟道230贯穿该封装层23而未延伸至该承载件20的内部。
如图2D所示，形成第一屏蔽层24于该封装层23的第一表面23a上。
于本实施例中，该第一屏蔽层24还沿该沟道230内的封装层23的表面形成。
于其它实施例中，如图2D’所示，该第一屏蔽层24’填满该沟道230。
此外，形成该第一屏蔽层24的材质为绝缘材或导电材，且其材质不同于该封装层23的材质。
如图2E所示，沿该沟道230进行切单制程，以分离各该封装单元2b，且该第一屏蔽层24保留于各该封装单元2b上。
于本实施例中，该承载件20的边缘与该封装层23构成阶梯部22，使该第一屏蔽层24对应该阶梯部22之处呈现阶梯状。
如图2F所示，形成一第二屏蔽层25于该第一屏蔽层24与该承载件20的侧表面20c上，以形成该封装结构2，且形成该第一屏蔽层24的材质不同于形成该第二屏蔽层25的材质。
于本实施例中，形成该第二屏蔽层25的材质为导体材，且其以化学镀膜的方式形成，如溅镀(sputtering)，亦可藉由涂布(coating)方式形成。
此外，形成该第二屏蔽层25的材质例如铜(Cu)、镍(Ni)、铁(Fe)或铝(Al)等。
又，该第二屏蔽层25可选择性地电性连接该承载件20的接地部(因该接地部外露于该承载件20的侧表面20c)。
另外，若接续图2D’的制程，制作出如图2F所示的封装结构2’，且该第一屏蔽层24’的侧表面24a齐平该承载件20的侧表面20c。
图3A至图3B为本发明封装结构的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于沟道的深度，其它制程大致相同。
如图3A所示，形成多个沟道330于各该封装单元2b之间，且该沟道330贯穿该封装层23并延伸至该承载件20的内部。
如图3B及图3B’所示，可参考图2D至图2F所述的制程，以制成另一态样的封装结构3,3’。
于本实施例中，该承载件20的边缘成为阶梯部22’，且该封装层23未形成于该承载件20的边缘上，使该承载件20的边缘伸出该封装层23的侧表面23c。
图4A至图4B为本发明封装结构4的制法的第三实施例的剖面示意图。本实施例与上述实施例的差异在于未形成沟道，其它制程大致相同。
如图4A所示，提供一封装体4a，该封装体4a具有一承载件40、设于该承载件40上的一电子元件41及包覆该电子元件21的封装层23。
于本实施例中，该电子元件41为覆晶式晶片，即藉由多个焊球410对应电性连接至该承载件40的电性接触垫200。
如图4B所示，形成一第一屏蔽层24于该封装层23上，再形成一第二屏蔽层25于该第一屏蔽层24上。
于本实施例中，该承载件40的侧表面40c齐平该封装层23的侧表面23c，即该承载件40的边缘未伸出该封装层23的侧表面23c。
图5为本发明封装结构5的制法的第四实施例的剖面示意图。本实施例与上述实施例的差异在于电子元件的数量与第二屏蔽层的数量，其它制程大致相同。
如图5所示，该封装结构5具有多个电子元件51与多个第二屏蔽层55。
于本实施例中，各该第二屏蔽层55的材质可不相同，且相邻的各第二屏蔽层55的材质不会相同。
本发明的制法藉由在该封装层23外形成该第一屏蔽层24,24’与该第二屏蔽层25,55以作为电磁波屏障(EMI Shielding)，以防止该电子元件21,41,51受外部电磁波干扰，例如，防止蓝芽晶片的讯号受干扰。
此外，若该电子元件21,41,51为低频元件，则多层屏障(shielding)的结构能提供较好的防电磁干扰效果。
本发明复提供一种封装结构2,2’,3,3’,4,5，包括：一承载件20,40、至少一电子元件21,41,51、封装层23、一第一屏蔽层24,24’、以及至少一第二屏蔽层25,55。
所述的封装结构2,2’,3,3’,4,5为射频模组。
所述的承载件20,40具有多个电性接触垫200。
所述的电子元件21,41,51设于该承载件20,40上且电性连接该些电性接触垫200。于一实施例中，该电子元件21,41,51为射频晶片，例如，蓝芽晶片或Wi-Fi晶片。
所述的封装层23设于该承载件20,40上，以包覆该电子元件21,41,51。
所述的第一屏蔽层24,24’形成于该封装层23上，且形成该第一屏蔽层24,24’的材质为绝缘材。
所述的第二屏蔽层25,55形成于该第一屏蔽层24,24’上，且形成该第一屏蔽层24,24’的材质不同于形成该第二屏蔽层25,55的材质，例如，形成该第二屏蔽层25,55的材质为导体材。
于一实施例中，该第一屏蔽层25,55复延伸至该承载件20,40上。
于一实施例中，该承载件20,40的边缘成为阶梯部22,22’。因此，该第一屏蔽层24复覆盖该阶梯部22,22’，且该第一屏蔽层24对应该阶梯部22,22’之处呈现阶梯状；或者，该第一屏蔽层24’还覆盖该阶梯部，且该第一屏蔽层24’的侧表面24a齐平该承载件20的侧表面20c。
综上所述，本发明的封装结构及其制法，主要藉由在该封装层外形成多层不同材质的屏蔽层的设计，以避免该电子元件受外部电磁波干扰的问题。
此外，若该电子元件为低频元件，则多层屏障结构能提供较好的防电磁干扰效果。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (12)

1.一种封装结构，包括：
一承载件，其侧表面外露有接地部；
单一电子元件，其设于该承载件上；
封装层，其包覆该电子元件；
一第一屏蔽层，其形成于该封装层上，且形成该第一屏蔽层的材质为绝缘材；以及
至少一第二屏蔽层，其形成于该第一屏蔽层与该承载件的侧表面上，且形成该第二屏蔽层的材质为导体材，该第二屏蔽层并电性连接该承载件侧表面的接地部。
2.如权利要求1所述的封装结构，其特征为，该电子元件为射频晶片。
3.如权利要求1所述的封装结构，其特征为，该第一屏蔽层还延伸至该承载件上。
4.如权利要求1所述的封装结构，其特征为，该承载件的边缘成为阶梯部。
5.如权利要求4所述的封装结构，其特征为，该第一屏蔽层还覆盖该阶梯部，且该第一屏蔽层对应该阶梯部之处呈现阶梯状。
6.如权利要求4所述的封装结构，其特征为，该第一屏蔽层还覆盖该阶梯部，且该第一屏蔽层的侧表面齐平该承载件的侧表面。
7.一种封装结构的制法，包括：
提供一封装体，该封装体具有一承载件、设于该承载件上的多个电子元件及包覆该电子元件的封装层，其中，该封装体定义有多个封装单元，且各该封装单元仅具有单一该电子元件，该承载件的侧表面外露有接地部；
形成多个沟道于各该封装单元之间；
形成一第一屏蔽层于该封装层上与各该沟道中，且形成该第一屏蔽层的材质为绝缘材；
沿各该沟道进行切单制程，以分离各该封装单元，且该第一屏蔽层保留于各该封装单元上；以及
形成至少一第二屏蔽层于该第一屏蔽层与该承载件的侧表面上，且形成该第二屏蔽层的材质为导体材，该第二屏蔽层并电性连接该承载件侧表面的接地部。
8.如权利要求7所述的封装结构的制法，其特征为，该电子元件为射频晶片。
9.如权利要求7所述的封装结构的制法，其特征为，该沟道贯穿该封装层。
10.如权利要求9所述的封装结构的制法，其特征为，该沟道延伸至该承载件内。
11.如权利要求7所述的封装结构的制法，其特征为，该第一屏蔽层还沿该沟道的表面形成。
12.如权利要求7所述的封装结构的制法，其特征为，该第一屏蔽层填满该沟道。
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