TWI475660B - 在多晶片模組中用於電磁干擾屏蔽之方法及裝置 - Google Patents

在多晶片模組中用於電磁干擾屏蔽之方法及裝置 Download PDF

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TWI475660B
TWI475660B TW097120502A TW97120502A TWI475660B TW I475660 B TWI475660 B TW I475660B TW 097120502 A TW097120502 A TW 097120502A TW 97120502 A TW97120502 A TW 97120502A TW I475660 B TWI475660 B TW I475660B
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Jinbang Tang
Jong-Kai Lin
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    • H05K1/0213Electrical arrangements not otherwise provided for
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    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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Description

在多晶片模組中用於電磁干擾屏蔽之方法及裝置
本發明大體係關於半導體封裝,且特別係關於為多晶片模組及相關封裝提供電磁屏蔽的方法。
本申請案在2007年6月19日已經於美國申請為專利申請案第11/765,170號。
半導體裝置持續減少尺寸及增加功率密度,進而給系統設計者帶來很多挑戰。其中一個主要挑戰係關於電磁干擾(EMI)-即,如何屏蔽內部元件相互之間以及與外部源的干擾。這樣的屏蔽在多晶片與多模組射頻整合的情況中尤其重要。
晶片對晶片及模組對模組的屏蔽通常使用一嵌入式屏蔽結構、一金屬罐蓋罩、等形屏蔽結構或其類似物而予以提供。然而,這樣的解決方法傾向於增加元件的大小,並且通常需要額外的處理步驟及成本。
因此,經由克服先前技術的這些及其他缺點,而需要與多晶片及多模組封裝一起使用的高效能、低成本之屏蔽技術。此外,本發明其他可取的效能及特徵從隨後詳細描述及該等所附請求項,結合附加圖式以及上述技術領域及背景將成為明顯的。
以下詳細描述於本質上僅僅是示範,且不欲限制本發明或本申請案以及本發明的使用。此外,無意被由先前技術 領域、背景或以下詳細描述中出現的任何表達的或暗示的理論所限制。為求簡潔,與半導體處理、電子封裝及裝置封裝的傳統技術在此不予描述。
為了說明的簡單與清晰,該等圖示描繪一般結構及/或該等各種實施例之建構的方式。已知的部件與技術的描述及細節可能被省略,以避免不必要地混淆其他部件。該等圖示中的元件不需按比例繪製:一些部件的大小可能相對於其他元件被放大,以幫助增進理解該等示範性實施例。
列舉的名詞,比如"第一"、"第二"、"第三"等可用於相似元件之間的區分,且不需要用於描述一特定空間或時間順序。這樣使用的這些名詞於合適的情況下是可互換的。這裏描述的本發明的該等實施例是(例如)能夠依序使用,除了那些於此說明或描述的之外。除非明確說明,否則"連接"指的是一元件/節點/部件是直接連接到(或直接連通與)另一元件/節點/部件,且不一定是機械地。同樣地,除非明確說明,否則"耦合"指的是一元件/節點/部件是直接或間接連接到(或是直接或間接連通與)另一元件/節點/部件,且不一定是機械地。
該等詞"包括"、"包含"、"具有"以及其任何變形是同義地用於表示非獨佔性包含。該等詞"左"、"右"、"裏"、"外"、"前"、"後"、"上"、"下"以及其他這類的方向性詞係用於描述相對位置,而不一定是在空間中的絕對位置。該詞"示範性"是用於"實例"而不是"理想"的意思。
一般地,本發明係關於使用導電模製化合物以屏蔽半導 體封裝的方法及結構,以達到局部及總體屏蔽。參考圖1-6中所示之簡化的剖面說明,將描述一示範性的EMI屏蔽方法。
如圖1中所示,提供一具有一黏著層(例如,一膠帶)104的承載結構或"基板"102。接著,如圖2中所示,一或多個電子元件(106、108等)係附接到黏著層104的表面105。這些電子元件可以是RF元件、微處理器、電容器、電阻器或者任何其他類型的主動或被動元件,取決於特定應用。在該說明的實施例中,係顯示一"球狀上蓋"表面聲波(SAW)結構108及半導體元件106。然而,該等實施例並不限於元件的類型或數目。亦應瞭解的是,當一單獨的多層結構係顯示於該等圖示中時,可同時產生多個結構,然後切割各個結構以用於測試。
如圖3中所說明,一絕緣層係形成於電子元件106與108上,以及可選擇地於黏著層104的任何暴露區域之上。接著,一導電模製化合物或"囊封材料"115係形成於絕緣層110之上。導電模製化合物115可包括任何材料,其為該等嵌入式元件提供結構支撐並且同時顯出一適合提供所需EMI屏蔽的電氣導電性,例如,含有塑膠及金屬兩者成分的導電塑膠化合物,其具有金屬的電磁特性,但是能像塑膠一樣地處理。
如圖5中所示,該基板102及黏著層104已經被移除,並且為了清晰,所產生的結構係倒置顯示。因此,原先在下側的元件108與106及部分之絕緣層110現在一起被暴露 了,進而形成一表面120。
接著,形成多層電路140,如圖6中所示,以使其與各種電氣元件電連通。多層電路140包含各種互連、介電質、多層電鍍金屬以及允許在層之間電連通的其他元件。在說明的實施例中,(例如)繪示出信號通孔152接觸於元件106與108。此等層之處理在此技術領域中是眾所周知的。組成多層結構140的各層的大小、形狀及厚度可經選擇,以滿足任何特別設計目的。在一實施例中,(例如)層140有一大約20到200微米的經結合的厚度。
接著,如圖6中所示,形成一或多個屏蔽通孔150,使其延伸穿過多層電路140且接觸導電囊封材料115。屏蔽通孔150可能是由傳統用在關於印刷電路板(PCB)技術的常見電鍍通孔所組成,或者可能是金屬填充(例如,銅填充)通孔結構。此外,多個熱通孔層可藉由連續電鍍及蝕刻以形成垂直堆積的這類通孔而形成。通孔的形狀、厚度、間隔、密度及大小可變化。例如,通孔可以一正規陣列、一交錯陣列、一隨機圖案或任何其他合適的配置而間隔開。
以這種方式,該等元件106與108經由導電化合物115及基板屏蔽通孔150而相互屏蔽,而屏蔽通孔150可能是以一內部或周圍通孔環的形式。
應瞭解的是,圖1-6係為了清晰的目的而被簡化,且一典型完成的結構還可包含任何數目的被動元件及主動元件。例如,各種基頻IC、收發器、電源管理模組等可用於一示範性應用中。關於這類的嵌入式晶片結構的更多資訊 可於例如由本案專利代理人擁有的美國專利第6,838,776號及美國專利第6,921,975號中找到。
按照另一實施例,可在塗上導電模製化合物之前形成一局部屏蔽層。這樣的結構被顯示於等角圖圖7中,其中元件106、108係附接到導電的非連續的屏蔽區域170。此類屏蔽層可包括環氧樹脂、陶瓷或其類似物。在另一實施例中,若(例如)在薄化處理後暴露出該等元件,一頂部屏蔽層可被形成於該導電囊封材料115上。
然而本發明可結合一些不同封裝及製程而使用,而一種此類製程是重分佈晶片封裝(RCP)製程。參考圖8-13的等角圖中所說明的簡化製程,一基板802被塗佈一黏著劑804(圖8)。接著,一模製框架806係固定於黏著劑804的該表面(圖9),且相同或變化類型的一些晶粒808(或者其他電子元件)係與一或多個元件一起以一預定圖案放置(主動側朝下)於膠帶804上(圖10)。一前述的絕緣層可在此時形成於元件808之上。
一環氧樹脂或其他囊封材料810(例如,一導電環氧樹脂)係沈積到此總成上,使其覆蓋晶粒808並且實質填滿晶粒808之間的間隔(圖11)。接著,移除模製框架806(圖12)。囊封材料810的表面可向下研磨至所要厚度,其中層115仍然覆蓋該等元件的頂部。然後,層804與802被釋放,該面板係予以清除,且暴露出各個晶粒的背側(裝置輸入/輸出)表面或者其他元件808(圖13)。所產生的面板層結構之後經適當地處理(例如,如在此關於圖6的該實施例 所討論),以利用傳統方法形成增層或其他多層結構(包含通孔及其類似物)。應瞭解的是,也可於該過程中的不同時間執行各種額外步驟,包括清潔、固化及/或烘乾。
根據一實施例,一種製造一多層封裝結構之方法,其包括:提供一基板,該基板上具有一黏著層;附接複數個電子元件到該黏著層;形成一絕緣層於該複數個電子元件之上;形成一導電囊封材料結構於該絕緣層之上;自該等電子元件卸離該黏著層;形成多層電路於該複數個電子元件之上且與該複數個電子元件電連通;以及形成一屏蔽通孔穿過該多層電路,以使其接觸該導電囊封材料。該方法進一步包含在形成該導電囊封材料之前,於該黏著層上形成一局部絕緣層。另一實施例進一步包含減少該導電囊封材料層的厚度。在另一實施例中,此方法進一步包含於該導電囊封材料結構上形成一頂部屏蔽層之步驟。在一實施例中,該導電囊封材料包括導電塑膠模製化合物。在另一實施例中,形成該絕緣層包含沈積一聚合物層。形成該多層電路可包含形成用於在該複數個元件之間傳輸信號之至少一個信號通孔。
根據一實施例的一種屏蔽多層封裝結構包括:一導電囊封材料結構;複數個電子元件,嵌入於該導電囊封材料結構中,其中一絕緣層係位於該導電囊封材料結構與該等電子元件之間;多層電路,位於該複數個電子元件上且與其電連通;以及至少一個屏蔽通孔,延伸穿過該多層電路,以使其接觸該導電囊封材料。此封裝進一步包含一局部絕 緣覆蓋層,位於該複數個電子元件之至少一者與該導電囊封材料之間。另一實施例進一步包含一頂部屏蔽層,位於該導電囊封材料結構上。在另一實施例中,該導電囊封材料包括一導電塑膠模製化合物。在一實施例中,形成該絕緣層包含沈積一聚合物層。
一種屏蔽複數個電子元件免於電磁干擾(EMI)之方法,包括:將該複數個電子元件嵌入於一導電囊封材料結構內,以使絕緣層位於該導電囊封材料結構與該等電子元件之間;以及形成與該導電囊封材料電接觸之至少一個屏蔽通孔。一方法進一步包含形成與該複數個電子元件電連通之多層電路。在另一實施例中,此方法進一步包含形成一局部絕緣層,該局部絕緣層位於該複數個電子元件之至少一者與該導電囊封材料之間。在另一實施例中,形成該局部屏蔽層包含形成一層環氧樹脂或陶瓷。一頂部屏蔽層係位於該導電囊封材料結構上。在不同實施例中,該導電囊封材料包括選自由下列組成之群的一材料:鋁、銅、鎳鐵、錫與鋅。在一實施例中,該絕緣層經由沈積一聚合物層而提供。在另一實施例中,沈積該聚合物層包含沈積一聚醯亞胺層。
以上出現的該示範性實施例或該等示範性實施例只是實例,且並不欲在任何方面限制本發明的範圍、應用性或配置。相反地,以上詳細描述將為那些熟習此項技術者執行該示範性實施例或該等示範性實施例提供一方便途徑。應瞭解的是,在不偏離本發明在該等所附請求項及其法律上 的均等物中所闡述的範圍下,可在元件的功能及配置中作各種變化。
102‧‧‧基板
104‧‧‧黏著層
105‧‧‧表面
106‧‧‧半導體元件
108‧‧‧"球狀上蓋"表面聲波(SAW)結構
110‧‧‧絕緣層
115‧‧‧囊封材料
120‧‧‧表面
140‧‧‧多層電路
150‧‧‧屏蔽通孔
152‧‧‧信號通孔
170‧‧‧屏蔽區域
802‧‧‧基板
804‧‧‧黏著劑
806‧‧‧模製結構
808‧‧‧晶粒
810‧‧‧囊封材料
圖1-6繪示為根據一實施例製造一多晶片模組的示範性製程;圖7是根據一實施例且在圖1-6描繪過程中的一時間點的一多晶片模組的等角圖;圖8-13繪示為根據一實施例製造一中間面板層的示例性製程。
106‧‧‧半導體元件
108‧‧‧"球狀上蓋"表面聲波(SAW)結構
110‧‧‧絕緣層
115‧‧‧囊封材料
140‧‧‧多層電路
150‧‧‧屏蔽通孔
152‧‧‧信號通孔

Claims (20)

  1. 一種製造一多層封裝結構之方法,其包括:提供一基板,該基板上具有一黏著層;附接複數個電子元件之第一表面到該黏著層,其中該複數個電子元件具有該等第一表面及相對於該等第一表面之第二表面;形成一絕緣層,該絕緣層具有經設置與該複數個電子元件之該等第二表面接觸之第一部分,及經設置與該黏著層接觸之第二部分;形成一導電囊封材料結構於該絕緣層之上而產生一結構,其中該絕緣層之該等第一部分位於該導電囊封材料結構與該複數個電子元件之該等第二表面之間,及其中該絕緣層之該等第二部分位於該黏著層與該導電囊封材料結構之間;自該複數個電子元件之該等第一表面及該絕緣層之該等第二部分卸離該黏著層;形成多層電路於該複數個電子元件之該等第一表面之上且與該複數個電子元件之該等第一表面電連通;以及形成一屏蔽通孔穿過該多層電路及該絕緣層之該等第二部分,以使該屏蔽通孔接觸該導電囊封材料結構。
  2. 根據請求項1之方法,其進一步包含在形成該導電囊封材料之前,於該黏著層上形成一局部絕緣層。
  3. 根據請求項1之方法,其進一步包含減少該導電囊封材料層的厚度。
  4. 根據請求項1之方法,其進一步包含於該導電囊封材料結構上形成一頂部屏蔽層之步驟。
  5. 根據請求項1之方法,其中該導電囊封材料包括導電塑膠模製化合物。
  6. 根據請求項1之方法,其中形成該絕緣層包含沈積一聚合物層。
  7. 根據請求項1之方法,其中形成該多層電路包含:形成用於在該複數個元件之間傳輸信號之至少一個信號通孔。
  8. 一種屏蔽多層封裝結構,其包括:複數個電子元件,其具有實質上共平面之多個第一表面;一絕緣層,其覆蓋該複數個電子元件且具有一第一表面及一第二表面,其中該第一表面具有與該等電子元件之第二表面一致之第一部分,及實質上與該等電子元件之該等第一表面共平面之第二部分,其中該等第二部分實質上在該等電子元件之間連續;一導電囊封材料結構,其覆蓋該絕緣層且具有跨越包括該等電子元件之該封裝結構之一部分之一實質上平面且連續之第一表面,其中該等電子元件嵌入於該導電囊封材料結構中,及其中該絕緣層被提供於該導電囊封材料結構與該等電子元件之間;多層電路,其形成於該複數個電子元件上且與該複數個電子元件電連通;以及 至少一個屏蔽通孔,其延伸穿過該多層電路及該絕緣層,以使其接觸該導電囊封材料。
  9. 根據請求項8之封裝結構,其進一步包含一局部絕緣覆蓋層,其位於該複數個電子元件之至少一者與該導電囊封材料之間。
  10. 根據請求項8之封裝結構,進一步包含一頂部屏蔽層,其提供於該導電囊封材料結構上。
  11. 根據請求項1之方法,其中該導電囊封材料包括一導電塑膠模製化合物。
  12. 根據請求項1之方法,其中形成該絕緣層包含:沈積一聚合物層。
  13. 一種屏蔽複數個電子元件免於電磁干擾(EMI)之方法,其中該複數個電子元件具有第一表面及相對於該等第一表面之第二表面,該方法包括:將該複數個電子元件嵌入於一導電囊封材料結構內,以使一絕緣層之第一部分被提供於該導電囊封材料結構與該等電子元件之該等第二表面之間,並使該絕緣層之第二部分被提供於該複數個電子元件之間,且與該等第一表面共平面;以及形成至少一個屏蔽通孔,其穿過該絕緣層之該等第二部分,且與該導電囊封材料結構電接觸。
  14. 根據請求項13之方法,其進一步包含形成與該複數個電子元件電連通之多層電路。
  15. 根據請求項14之方法,其進一步包含形成一局部絕緣 層,該局部絕緣層位於該複數個電子元件之至少一者與該導電囊封材料之間。
  16. 根據請求項15之方法,其中形成該局部屏蔽層包含:形成一層環氧樹脂或陶瓷。
  17. 根據請求項13之方法,其進一步包含一提供於該導電囊封材料結構上之頂部屏蔽層。
  18. 根據請求項13之方法,其中該導電囊封材料包括選自由下列組成之群的一材料:鋁、銅、鎳鐵、錫與鋅。
  19. 根據請求項13之方法,其中該絕緣層係藉由沈積一聚合物層而提供。
  20. 根據請求項18之方法,其中沈積該聚合物層包含沈積一聚醯亞胺層。
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