CN104321864B - 具有非共面的、包封的微电子器件和无焊内建层的微电子封装 - Google Patents

具有非共面的、包封的微电子器件和无焊内建层的微电子封装 Download PDF

Info

Publication number
CN104321864B
CN104321864B CN201280073065.8A CN201280073065A CN104321864B CN 104321864 B CN104321864 B CN 104321864B CN 201280073065 A CN201280073065 A CN 201280073065A CN 104321864 B CN104321864 B CN 104321864B
Authority
CN
China
Prior art keywords
microelectronic component
active face
encapsulating
microelectronic
microelectronics packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280073065.8A
Other languages
English (en)
Other versions
CN104321864A (zh
Inventor
C·胡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN104321864A publication Critical patent/CN104321864A/zh
Application granted granted Critical
Publication of CN104321864B publication Critical patent/CN104321864B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Abstract

一种具有包封的基板的微电子封装，包括包封在包封材料内的多个微电子器件，其中，包封结构可以具有邻近多个微电子器件的有源面的有源面，并且其中，所述多个微电子器件中的至少一个微电子器件可以具有大于所述多个微电子器件中另一个微电子器件的高度(例如非共面)。微电子封装进一步包括邻近包封结构的有源面而形成的无焊内建层结构。微电子封装还可以包括邻近在包封结构的有源面上设置的、并与包封的基板的多个微电子器件中的至少一个微电子器件电接触的具有有源面的微电子器件。

Description

具有非共面的、包封的微电子器件和无焊内建层的微电子 封装
技术领域
本说明的实施例总体上涉及微电子封装的领域，更具体而言，涉及具有多个非共面的、包封的微电子器件和无焊内建层的微电子封装。
背景技术
微电子产业一直争取生产更快且更小的微电子封装，以便用于不同移动电子产品中，例如便携式计算机、电子平板电脑、蜂窝电话、数码相机等。典型地，微电子封装在诸如微处理器、芯片组、图形设备、无线设备、存储器设备、专用集成电路等的微电子器件与诸如母板、中介层、印刷电路板等的外部组件之间必须具有相当大量的导电路径(用于发送电力/接地和输入/输出信号)。相当大量的导电路径的形成导致必须在相对大的微电子器件中的形成，会需要严格的设计规则和/或会需要在互连层中的多层电介质材料和导电迹线，以实现到外部互连部的适当的导电路径。而且，多个微电子器件可以用于微电子封装的制造中，本领域技术人员会理解，这会导致的问题包括但不限于：在多个微电子器件的互连之间的带宽限制，当使用球栅阵列贴装结构时的封装的可靠性，微电子封装的尺寸缩放，由于贴装到单个微电子基板或母板的多个封装的形状因子问题，由于集成每一个都具有自身封装的多个器件的成本问题，及电位导电迹线“扇出”限制。
附图说明
在说明书的结论部分中具体指出并清楚地要求了本公开内容的主题。结合附图，依据以下的说明和所附权利要求书，本公开内容的前述及其他特征会变得更为明显。应当理解，附图仅示出了根据本公开内容的几个实施例，因此不应认为是限制本公开内容的范围。将通过使用附图，借助另外的特殊性和细节来说明本公开内容，以便更易于确定本公开内容的优点，在附图中：
图1示出了根据本说明的实施例的位于基板载体上的多个微电子器件的横截面图。
图2示出了根据本说明的实施例的布置在图1的微电子器件上的包封材料的横截面图。
图3示出了根据本说明的另一个实施例的布置在图1的微电子器件上的包封材料的横截面图。
图4示出了根据本说明的实施例的通过固化/凝固包封材料而形成的包封结构以及从基板载体的去除包封结构的横截面图。
图5示出了根据本说明的实施例的位于包封结构的有源面上的具有有源面的微电子器件。
图6示出了根据本说明的实施例的具有有源面的微电子器件借助键合引线与包封结构的至少一个微电子器件的电气附接。
图7示出了根据本说明的实施例的具有有源面的微电子器件借助焊球与包封结构的至少一个微电子器件的电气附接。
图8示出了根据本说明的实施例的具有有源面的微电子器件借助焊球与包封结构的至少一个微电子器件的电气附接。
图9示出了根据本说明的实施例的本说明的包封结构，其中，包封材料没有围绕至少微电子器件的突出的互连部或者已经被去除了。
图10示出了根据本说明的实施例的图9的结构，如果存在的话，具有布置在包封结构和具有有源面的微电子器件上的电介质材料层。
图11示出了根据本说明的实施例的图10的结构，如果存在的话，具有通过电介质层而形成的开口部，以便露出至少一个微电子器件与至少一个具有有源面的微电子器件的至少一个互连部。
图12示出了根据本说明的实施例的图11的结构，其中，以导电材料填充开口部以便形成导电通孔。
图13示出了根据本说明的实施例的图12的结构，其中，在电介质材料层上形成导电迹线。
图14示出了根据本说明的实施例的微电子封装。
图15示出了根据本说明的一个实现方式的用于同时制造多个微电子封装的多组微电子器件。
图16示出了根据本说明的一个实现方式的图15的结构，其中，分割或切割多组微电子器件，以形成单个微电子封装。
图17示出了根据本说明的实施例的用于制造微电子结构的过程的流程图。
图18示出了根据本说明的一个实现方式的电子系统/设备。
具体实施方式
在以下说明中，参考了附图，附图示例性地显示了特定实施例，在其中可以实践所要求的主题。足够详细地说明了这些实施例，以使得能量源技术人员能够实践主题。会理解，多个实施例尽管有所不同，但不必是相互排斥的。例如，本文结合一个实施例所述的特定特征、结构或特性可以在其他实施例内实施，不会脱离所要求主题的精神和范围。本说明书内对“一个实施例”或“实施例”的提及表示结合该实施例所述的特定特征、结构或特性包括在本发明包含的至少一个实现方式中。因此，短语“一个实施例”或者“在实施例中”的使用不一定指代同一实施例。另外，会理解，在不脱离所要求主题的精神和范围的情况下，可以修改单个元件在每一个公开的实施例中的位置或布置。以下的详细说明因此不应在限制性意义上来理解，主题的范围仅由所附权利要求书连同所附权利要求书给与等效替代的完整范围来限定，并适当地解释。在附图中，全部几个图中的相似的参考标记指代相同或相似的元件或功能，其中所示的元件不一定彼此按照比例，而是可以放大或缩小单个元件，以便在本说明的环境中更易于理解元件。
本说明的实施例可以包括一种微电子封装，具有包封的基板，所述包封的基板包括基本上包封在包封材料内的多个微电子器件，其中，包封结构可以具有邻近所述多个微电子器件的有源面的有源面，并且其中，所述多个微电子器件中的至少一个微电子器件可以具有大于所述多个微电子器件中另一个微电子器件的高度(例如非共面)。微电子封装进一步包括邻近包封结构的有源面而形成的无焊内建层结构。微电子封装还可以包括邻近包封结构的有源面而设置的具有有源面的微电子器件，并与包封结构的所述多个微电子器件中的至少一个微电子器件电接触。
在本说明的一个实施例中，诸如微处理器、芯片组、控制器、图形设备、无线设备、存储器设备、专用集成电路、电阻器、电容器、电感器等的多个微电子器件(示出为元件1021-1023)可以位于基板载体112上，如图1所示的。微电子器件1021-1023可以位于基板载体112上，它们各自的有源面1041-1043邻接和/或邻近基板载体112。如图1进一步所示的，微电子器件的有源面1041-1043的每一个都可以在其上具有至少一个连接结构1101-1103，例如焊盘、焊料块或柱、焊桩等。注意，高度，即，从微电子器件的有源面(参见元件1042)或者自微电子器件(例如分别为微电子器件1021和1023)突出的连接结构(参见元件1101和1103)到各自相应的微电子器件1021-1023的各自相应的背面1061-1063的距离(示出为H1-H3)，不必基本上相等。
如图2和3所示的，包封材料122可以布置在每一个微电子器件1021-1023和基板载体122上。可以借助任何适当的技术来布置包封材料122，包括但不限于材料沉积和成型。包封材料122可以是任何适当的材料，包括但不限于，二氧化硅填充的环氧树脂，例如可以从Ajinomoto Fine-Techno Co.,Inc.,1-2Suzuki-cho,Kawasaki-ku,Kawasaki-shi,210-0801,Japan(例如Ajinomoto ABF-GX13、Ajinomoto GX92等)得到的材料。如图2所示的，包封材料122可以构成覆盖每一个微电子器件1021-1023的背面124，其中，包封材料122邻接每一个微电子器件的背面1061-1063并邻接每一个微电子器件1021-1023的至少一个侧面1081-1083(在各自相应的微电子器件的有源面1041-1043与各自相应的微电子器件背面1061-1063之间延伸)。可替换地，如图3所示的，包封材料的背面124可以形成为与具有最大高度的微电子器件的背面(示出为具有高度H2的微电子器件1022(参见图1))基本上平齐。这可以借助成型来实现。这也可以通过使图2中所示的结构平坦化来实现(例如化学机械抛光)。
一旦包封材料122已经固化或基本上凝固了，就可以将它从基板载体112去除以构成包封结构130，所述包封结构130具有由与基板载体112以及每一个微电子器件1021-1023的有源面1041-1043和/或连接结构1101-1103邻接的包封材料122的一部分构成的有源面132，如图4所示的，其中，包封材料122与基板载体112邻接的部分可以与每一个微电子器件1021-1023的有源面1041-1043和/或连接结构1101-1103基本上平齐。如图5-7所示的，至少一个具有有源面的微电子器件142可以邻近包封结构的有源面132而设置。具有有源面的微电子器件142可以是任何适当的器件，例如有源器件，包括但不限于微处理器、芯片组、控制器、图形设备、无线设备、存储器设备、和专用集成电路，或者无源器件，包括但不限于，电阻器、电容器、和电感器。尽管在图5-13中将具有有源面的微电子器件142示出为与微电子器件1022相邻，但它可以与任何微电子器件1021-1023相邻，与包封材料122相邻，或者与二者都相邻。
如图5所示的，可以设置至少一个具有有源面的微电子器件142，其背面144接触包封结构的有源面132，以便可以在实质上形成的内建层中与至少一个微电子器件1021-1023电接触。在其他实施例中，可以设置至少一个具有有源面的微电子器件142，其背面144借助至少一条键合引线152接触包封结构的有源面132，键合引线152从具有有源面的微电子器件142的有源面146上的至少一个连接结构148和至少一个微电子器件1021-1023的至少一个连接结构1101-1103延伸，如图6所示的。此外，在如图7所示的另一个实施例中，具有有源面的微电子器件142可以通过多个互连部154直接电气连接到至少一个微电子器件1021-1023，的互连部154例如是在至少一个具有有源面的微电子器件的连接结构148与至少一个微电子器件的连接结构1101-1103(显示为微电子器件连接结构1102)之间延伸的焊球。在图7的实施例的一个示例中，微电子器件1022可以是微处理器，具有有源面的微电子器件142可以是存储器设备。此外，在如图8所示的实施例中，具有有源面的微电子器件142可以通过多个互连部154直接电气连接到至少两个微电子器件1021-1023(显示为微电子器件1021和1022)，互连部154例如是在至少一个具有有源面的微电子器件的连接结构148与至少两个微电子器件的连接结构1101-1103(显示为微电子器件连接结构1101和1102)之间延伸的焊球。
参考图2和3，包封材料122可以具有足够的粘性，以便围绕从微电子器件延伸的任何突出的互连部，例如微电子器件互连部1101和1103。如图9所示的，包封材料122的粘性可以不足以围绕突出的互连，例如微电子器件互连部1101。此外，应当理解，如果不希望包封材料122围绕突出的互连部，就可以借助本领域已知的任何技术将其去除。
如图10所示的，可以与包封结构的有源面132与具有有源面的微电子器件142(如果存在的话)相邻地布置第一电介质材料层1621。第一电介质材料层1621可以借助本领域已知的任何技术来形成，包括沉积，例如喷涂，之后是平坦化、自平坦化丝网印刷等。电介质层可以是任何适当地电介质材料，包括但不限于，如前所述的二氧化硅(SiO2)、氮氧化硅(SiOxNy)和氮化硅(Si3N4)及碳化硅(SiC)，以及二氧化硅填充的环氧树脂等。
如图11所示的，可以通过第一电介质材料层1621形成开口部164，以露出每一个微电子器件的连接结构1101-1103的至少一部分和至少一个具有有源面的微电子器件的互连部148(如果存在的话)。开口部164可以由本领域已知的任何技术形成，包括但不限于，激光钻孔、离子钻孔、光刻/蚀刻等。
如图12所示的，可以用导电材料填充开口部164，以形成第一导电通孔1661。导电材料可以是任何适当的材料，包括但不限于，铜、铝、银、金、它们的合金等。可以借助本领域已知的任何技术来布置导电材料，包括但不限于，沉积、电镀等，之后可以进行平坦化，如本领域技术人员会理解的。
如图13所示的，可以在第一电介质材料层1621上形成多条第一导电迹线1681的图案，以便接触至少一个第一导电通孔1661。可以借助本领域已知的任何技术来形成第一导电迹线1681的图案，包括但不限于，沉积或电镀，之后是光刻/蚀刻。第一导电迹线1681可以由如前所述的任何适当的导电材料，并借助本领域已知的任何技术形成，包括光刻、沉积、电镀等。第一电介质材料层1621、第一导电通孔1661和第一导电迹线1681可以构成第一内建层1701。
可以重复用于形成如图13所示的第一内建层1701的工艺，直至形成期望的导电路径。如图14所示的，可以形成第二内建层1702，其包括第二电介质材料层1622、第二导电通孔1662和第二导电迹线1682。如图14进一步所示的，可以形成最终内建层1703，其包括第三电介质材料层1623、第三导电通孔1663和焊盘172。内建层的组合(例如，第一内建层1701、第二内建层1702、和最终内建层1703)可以构成无焊内建层结构170。
如图13进一步所示的，可以在无焊内建层结构170上形成阻焊材料174，其中，通过阻焊材料174露出每一个焊盘172的至少一部分。可以在每一个焊盘172上形成外部互连部176，例如借助所示的球栅阵列互连部，以形成微电子封装180。可以利用阻焊材料174来包含用于形成含焊料的外部互连部176的焊料，如本领域技术人员会理解的。外部互连部176可以用于将微电子封装180连接到其他微电子结构(未示出)，例如母板、印刷电路板等。尽管外部互连部176示出为球栅阵列互连部，但会理解，外部互连部176可以是任何适当的外部互连部，包括但不限于，焊栅阵列、针栅阵列、连接盘网格阵列等，如本领域技术人员会理解的。在将焊料用于形成外部互连部176时，例如球栅阵列和焊栅阵列，焊料可以是任何适当的材料，包括但不限于，铅/锡合金和高锡含量合金(例如约90％或更多的锡)，及类似的合金。
尽管图1-14示出了单个微电子封装180的形成，但会理解，可以同时形成多个封装。如图15所示的，微电子器件1021-1023(参见图1-14)的多个组3101-3103可以如前所述的设置在基板载体122上(参见图2-14)，以构成多个包封结构330。可以按照在前相关于无焊内建层结构170(参见图9-14)所述的方式在多个包封结构330上形成多个无焊内建层结构370。可以按照在前相关于阻焊层结构172和外部互连部174(参见图14)所述的方式形成多个阻焊层372和多个封装外部互连部374，以形成多个包封结构380。
如图16所示的，可以切割或裁切图15的多个包封结构380，以将每一个微电子器件组3101-3103分隔为单个微电子封装1801-1803。可以借助本领域已知的任何技术来执行切割，包括但不限于，锯切、激光切割、离子轰击等。
在图17的流程图400中示出了制造本说明的微电子结构的一个过程的实施例。如在块410中限定的，多个微电子器件可以位于基板载体上，其中，每一个微电子器件的有源面都面向基板载体，并且其中，多个微电子器件中的至少一个的高度高于多个微电子器件中的另一个的高度。如在块420中限定的，可以借助包封材料来包封多个微电子器件。如在块430中限定的，随后固化包封材料层，以形成具有与基板载体邻接的有源面的包封材料。如在块440中所示的，从基板载体去除包封结构。如在块450中所示的，可以将有源面微电子结构设置在包封结构的有源面上。如在块460中所示的，具有有源面的微电子器件可以电气连接到包封结构内的多个微电子器件中的至少一个微电子器件。如在块470中所示的，可以在包封结构的有源面和具有有源面的微电子器件上形成无焊内建层结构。
图18示出了电子系统/设备500的实施例，例如便携式计算机、台式机、移动电话、数码相机、数字音乐播放器、上网平板/平板设备、个人数字助理、寻呼机、即时通讯设备、或者其他设备。电子系统/设备200可以适于无线发送和/或接收信息，例如通过无线局域网(WLAN)系统、无线个域网(WPAN)系统、和/或蜂窝网。电子系统/设备500可以包括在外壳520内的微电子基板510(例如母板、印刷电路板等)。正如本申请的实施例一样，微电子封装530(参见图14的元件180和图16的元件1801－1803)连接到其。如前所述的，微电子封装530可以包括多个封装微电子器件1021-1023(参见图1-14)，构成包封结构1330(参见图4-14)，其中，微电子器件可以具有不同高度以及在包封结构的有源面132(参见图4-14)上的可任选的具有有源面的微电子器件142(参见图5-14)，并且其中，可以在包封结构130上形成无焊内建层170(参见图14)。微电子基板510可以连接到不同外围设备，包括诸如键盘的输入设备540、诸如LCD显示器的显示设备550。会理解，如果显示设备550是触敏的，显示设备550也可以起到输入设备的作用。
会理解，本说明的主题不一定局限于图1-18中所示的特定应用。如本领域技术人员会理解的，主题可以应用于其他微电子器件制造应用。
如上详细说明了本发明的实施例，会理解，由所附权利要求书限定的本发明不局限于以上说明中阐述的特定细节，因为在不脱离本发明的精神或范围的情况下，这些细节的许多显而易见的变型是可能的。

Claims (28)

1.一种微电子封装，包括：
包封结构，所述包封结构包括实质上包封在包封材料内的多个微电子器件，其中，所述包封结构包括邻近所述微电子器件的有源面的有源面，并且其中，所述多个微电子器件中的至少一个微电子器件的高度大于所述多个微电子器件中的另一个微电子器件的高度；
无焊内建层结构，所述无焊内建层结构被形成为邻近所述包封结构的有源面；以及
设置在所述包封结构的有源面上的至少一个具有有源面的微电子器件。
2.根据权利要求1所述的微电子封装，其中，所述至少一个有源面电气连接到所述包封结构的所述多个微电子器件中的至少一个微电子器件。
3.根据权利要求2所述的微电子封装，其中，所述至少一个具有有源面的微电子器件通过所述无焊内建层结构电气连接到所述多个微电子器件中的至少一个微电子器件。
4.根据权利要求2所述的微电子封装，其中，所述至少一个具有有源面的微电子器件通过至少一条键合引线电气连接到所述多个微电子器件中的至少一个微电子器件。
5.根据权利要求2所述的微电子封装，其中，所述至少一个具有有源面的微电子器件通过至少一个焊料互连部直接电气连接到所述多个微电子器件中的至少一个微电子器件的有源面。
6.根据权利要求1所述的微电子封装，进一步包括电气连接到所述无焊内建层结构的外部互连部。
7.根据权利要求1所述的微电子封装，其中，所述多个微电子器件中的至少一个微电子器件包括从其有源面延伸的至少一个连接结构，并且其中，所述包封材料不包封所述多个微电子器件中的所述至少一个微电子器件的所述至少一个连接结构。
8.根据权利要求1所述的微电子封装，其中，所述包封材料包括二氧化硅填充的环氧树脂。
9.根据权利要求1-8中任意一项所述的微电子封装，其中，所述包封结构进一步包括背面，其中，所述包封结构的背面与所述多个微电子器件中的具有最大高度的至少一个微电子器件的背面实质上平齐。
10.一种形成微电子封装的方法，包括：
将多个微电子器件设置在基板载体上，其中，每一个所述微电子器件的有源面都面向所述基板载体，并且其中，所述多个微电子器件中的至少一个微电子器件的高度大于所述多个微电子器件中的另一个微电子器件的高度；
用包封材料实质上包封所述多个微电子器件；
固化所述包封材料以形成包封结构，所述包封结构具有与所述基板载体邻接的有源面；
从所述基板载体去除所述包封结构；以及
在所述包封结构的有源面上形成无焊内建层结构。
11.根据权利要求10所述的形成所述微电子封装的方法，进一步包括将至少一个具有有源面的微电子器件设置在所述包封结构的有源面上。
12.根据权利要求11所述的形成所述微电子封装的方法，进一步包括：在形成所述无焊内建层结构之前，将至少一个具有有源面的微电子器件电气连接到所述包封结构的所述多个微电子器件中的至少一个微电子器件。
13.根据权利要求12所述的形成所述微电子封装的方法，其中，电气连接所述至少一个具有有源面的微电子器件包括：将所述至少一个具有有源面的微电子器件通过所述无焊内建层结构电气连接到所述多个微电子器件中的至少一个微电子器件。
14.根据权利要求12所述的形成所述微电子封装的方法，其中，电气连接所述至少一个具有有源面的微电子器件包括：将所述至少一个具有有源面的微电子器件通过至少一条键合引线电气连接到所述多个微电子器件中的至少一个微电子器件。
15.根据权利要求12所述的形成所述微电子封装的方法，其中，电气连接所述至少一个具有有源面的微电子器件包括：将所述至少一个具有有源面的微电子器件通过至少一个焊料互连部电气连接到所述多个微电子器件中的至少一个微电子器件。
16.根据权利要求10所述的形成所述微电子封装的方法，进一步包括形成电气连接到所述无焊内建层结构的外部互连部。
17.根据权利要求10所述的形成所述微电子封装的方法，其中，将多个微电子器件设置在基板载体上包括设置多组微电子器件，且进一步包括在形成所述无焊内建层结构之后，对单组微电子器件进行切割以形成单个微电子封装。
18.根据权利要求10所述的形成所述微电子封装的方法，进一步包括：在对单组微电子器件进行切割之前，形成电气连接到所述无焊内建层结构的多个外部互连部。
19.根据权利要求10所述的形成所述微电子封装的方法，其中，所述多个微电子器件中的至少一个微电子器件的所述有源面包括从其有源面延伸的至少一个连接结构，并且其中，用包封材料来实质上包封所述多个微电子器件并没有包封所述多个微电子器件中的所述至少一个微电子器件的所述至少一个连接结构。
20.根据权利要求10所述的形成所述微电子封装的方法，其中，所述包封材料包括二氧化硅填充的环氧树脂。
21.根据权利要求10-20中任意一项所述的形成所述微电子封装的方法，其中，包封所述多个微电子器件进一步包括：形成所述包封结构的背面，所述包封结构的背面与所述多个微电子器件中的具有最大高度的至少一个微电子器件的背面实质上平齐。
22.一种微电子系统，包括：
外壳；及
布置在所述外壳内的微电子结构，包括：
微电子基板；以及
附接到所述微电子基板的至少一个微电子封装，所述至少一个微电子封装包括：
包封结构，所述包封结构包括实质上包封在包封材料内的多个微电子器件，其中，所述包封结构包括邻近所述微电子器件的有源面的有源面，并且其中，所述多个微电子器件中的至少一个微电子器件的高度大于所述多个微电子器件中的另一个微电子器件的高度；
无焊内建层结构，所述无焊内建层结构被形成为邻近所述包封结构的有源面；以及
设置在所述包封结构的有源面上的至少一个具有有源面的微电子器件。
23.根据权利要求22所述的系统，其中，所述至少一个有源面电气连接到所述包封结构的所述多个微电子器件中的至少一个微电子器件。
24.根据权利要求23所述的系统，其中，所述至少一个具有有源面的微电子器件通过所述无焊内建层结构电气连接到所述多个微电子器件中的至少一个微电子器件。
25.根据权利要求23所述的系统，其中，所述至少一个具有有源面的微电子器件通过至少一条键合引线电气连接到所述多个微电子器件中的至少一个微电子器件。
26.根据权利要求23所述的系统，其中，所述至少一个具有有源面的微电子器件通过至少一个焊料互连部直接电气连接到所述多个微电子器件中的至少一个微电子器件的有源面。
27.根据权利要求22所述的系统，其中，所述多个微电子器件中的至少一个微电子器件包括从其有源面延伸的至少一个连接结构，并且其中，包封材料不包封所述多个微电子器件中的所述至少一个微电子器件的所述至少一个连接结构。
28.根据权利要求22-27中任意一项所述的系统，其中，所述包封结构进一步包括背面，其中，所述包封结构的背面与所述多个微电子器件中的具有最大高度的至少一个微电子器件的背面实质上平齐。
CN201280073065.8A 2012-06-08 2012-06-08 具有非共面的、包封的微电子器件和无焊内建层的微电子封装 Active CN104321864B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2012/041714 WO2013184145A1 (en) 2012-06-08 2012-06-08 Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Publications (2)

Publication Number Publication Date
CN104321864A CN104321864A (zh) 2015-01-28
CN104321864B true CN104321864B (zh) 2017-06-20

Family

ID=49712399

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280073065.8A Active CN104321864B (zh) 2012-06-08 2012-06-08 具有非共面的、包封的微电子器件和无焊内建层的微电子封装

Country Status (4)

Country Link
US (1) US9685390B2 (zh)
CN (1) CN104321864B (zh)
DE (1) DE112012006469B4 (zh)
WO (1) WO2013184145A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
US9281292B2 (en) 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP
US9837278B2 (en) * 2014-02-27 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Wafer level chip scale package and method of manufacturing the same
US20160118353A1 (en) * 2014-10-22 2016-04-28 Infineon Techologies Ag Systems and Methods Using an RF Circuit on Isolating Material
US9985010B2 (en) * 2015-05-22 2018-05-29 Qualcomm Incorporated System, apparatus, and method for embedding a device in a faceup workpiece
TWI620296B (zh) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10504827B2 (en) 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
DE102021211642A1 (de) 2021-10-14 2023-04-20 Robert Bosch Gesellschaft mit beschränkter Haftung Leistungshalbleiter, Mold-Modul und Verfahren

Family Cites Families (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4921160A (en) * 1988-02-29 1990-05-01 American Telephone And Telegraph Company Personal data card and method of constructing the same
US5510649A (en) 1992-05-18 1996-04-23 Motorola, Inc. Ceramic semiconductor package having varying conductive bonds
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US5899705A (en) 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
DE69937739T2 (de) * 1999-05-11 2008-11-27 Mitsubishi Denki K.K. Halbleitervorrichtung
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6312972B1 (en) * 1999-08-09 2001-11-06 International Business Machines Corporation Pre-bond encapsulation of area array terminated chip and wafer scale packages
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6472762B1 (en) 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
US7294533B2 (en) * 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
US6909176B1 (en) 2003-11-20 2005-06-21 Altera Corporation Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate
KR100632472B1 (ko) 2004-04-14 2006-10-09 삼성전자주식회사 측벽이 비도전성인 미세 피치 범프 구조를 가지는미세전자소자칩, 이의 패키지, 이를 포함하는액정디스플레이장치 및 이의 제조방법
TWM266543U (en) 2004-10-28 2005-06-01 Advanced Semiconductor Eng Multi-chip stack package
KR100593703B1 (ko) 2004-12-10 2006-06-30 삼성전자주식회사 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
TWI269423B (en) 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
KR20080031192A (ko) 2005-06-29 2008-04-08 로무 가부시키가이샤 반도체 장치 및 반도체 장치 집합체
US7459782B1 (en) 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
TWI301663B (en) 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
JP4897451B2 (ja) 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US20080182363A1 (en) * 2007-01-31 2008-07-31 Freescale Semiconductor, Inc. Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
TW200901409A (en) 2007-06-22 2009-01-01 Nan Ya Printed Circuit Board Corp Packaging substrate with embedded chip and buried heatsink
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
JP4752825B2 (ja) 2007-08-24 2011-08-17 カシオ計算機株式会社 半導体装置の製造方法
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US20090152743A1 (en) 2007-12-15 2009-06-18 Houssam Jomaa Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic device
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US7847415B2 (en) 2008-07-18 2010-12-07 Qimonda Ag Method for manufacturing a multichip module assembly
US20100073894A1 (en) 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US20100237481A1 (en) 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US8222716B2 (en) * 2009-10-16 2012-07-17 National Semiconductor Corporation Multiple leadframe package
US20110108999A1 (en) * 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8034661B2 (en) 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8247900B2 (en) 2009-12-29 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip package having enhanced thermal and mechanical performance
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8497587B2 (en) 2009-12-30 2013-07-30 Stmicroelectronics Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
JP5460388B2 (ja) 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8264849B2 (en) 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US20110316140A1 (en) 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US20120001339A1 (en) * 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8304913B2 (en) * 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
JP5598212B2 (ja) 2010-09-29 2014-10-01 パナソニック株式会社 ハイブリッドコア基板とその製造方法、半導体集積回路パッケージ、及びビルドアップ基板とその製造方法
US20120112336A1 (en) 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US20120139095A1 (en) 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US8508037B2 (en) 2010-12-07 2013-08-13 Intel Corporation Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装

Also Published As

Publication number Publication date
DE112012006469T5 (de) 2015-03-05
US20140048959A1 (en) 2014-02-20
US9685390B2 (en) 2017-06-20
DE112012006469B4 (de) 2022-05-05
WO2013184145A1 (en) 2013-12-12
CN104321864A (zh) 2015-01-28

Similar Documents

Publication Publication Date Title
CN104321864B (zh) 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
CN104253115B (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
CN104253105B (zh) 半导体器件和形成低廓形3d扇出封装的方法
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
CN104428892B (zh) 用于基板核心层的方法和装置
CN108292645A (zh) 具有基于沟槽模制的电磁干扰屏蔽的半导体封装
JP2019512168A (ja) シリコン基板に埋め込まれたファンアウト型の３ｄパッケージ構造
CN107527884A (zh) 扇出型半导体封装件
CN107408547A (zh) 扇出型系统级封装件及其形成方法
TWI576928B (zh) 模封互連基板及其製造方法
CN103597594B (zh) 用于交替的封装功能的微电子衬底
US9635763B2 (en) Component built-in board mounting body and method of manufacturing the same, and component built-in board
CN106887393B (zh) 集成有功率传输芯片的封装结构的封装方法
JP2001217337A (ja) 半導体装置及びその製造方法
CN107622983A (zh) 半导体封装装置及其制造方法
JP2004342883A (ja) 半導体装置、及び半導体装置の製造方法
JP2006147869A (ja) 素子内蔵基板およびその製造方法
CN101228625A (zh) 具有镀金属连接部的半导体封装
CN108962840A (zh) 电子封装件及其制法
CN106816416B (zh) 半导体嵌入式混合封装结构及其制作方法
CN107195617A (zh) 基于不同高度铜柱的三维封装结构及其制造方法
US20130020572A1 (en) Cap Chip and Reroute Layer for Stacked Microelectronic Module
CN108604585A (zh) 包括集成电路(ic)封装之间的柔性连接器的集成器件
CN106298728A (zh) 封装结构及其制法
KR20160138754A (ko) 인쇄회로기판, 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant