CN108292645A - 具有基于沟槽模制的电磁干扰屏蔽的半导体封装 - Google Patents

具有基于沟槽模制的电磁干扰屏蔽的半导体封装 Download PDF

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Publication number
CN108292645A
CN108292645A CN201680068156.0A CN201680068156A CN108292645A CN 108292645 A CN108292645 A CN 108292645A CN 201680068156 A CN201680068156 A CN 201680068156A CN 108292645 A CN108292645 A CN 108292645A
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China
Prior art keywords
groove
electronic unit
package substrate
conductive
panel
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CN201680068156.0A
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Inventor
R·C·迪亚斯
E·J·李
J·D·黑普纳
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Intel Corp
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Intel Corp
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Publication of CN108292645A publication Critical patent/CN108292645A/zh
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Abstract

公开了具有电磁干扰(EMI)屏蔽的半导体封装及其制造方法。该半导体封装可以容纳单个电子部件或可以是系统级封装(SiP)实施方式。可以在半导体封装顶部并沿其周边提供EMI屏蔽。周边上的EMI屏蔽可以由设置于模制件的侧壁上的固化的导电油墨或固化的导电膏形成，所述模制件包封半导体封装上提供的电子部件。可以通过在利用固化模制件在原位形成的沟槽中填充导电油墨来形成EMI屏蔽的竖直部分，包括周边上的EMI屏蔽。EMI屏蔽的顶部部分可以另外是固化的导电油墨。

Description

具有基于沟槽模制的电磁干扰屏蔽的半导体封装
相关申请的交叉引用
本申请要求享有2015年12月22日提交的美国申请No.14/978,897的权益，在此通过引用将该美国申请的公开内容并入本文，如同完整阐述一般。
技术领域
本公开总体上涉及半导体封装，并且更具体而言涉及具有基于沟槽模制的电磁屏蔽的半导体封装。
背景技术
集成电路和其它电子器件可以被封装于半导体封装上。半导体封装可以被集成到例如消费电子系统的电子系统上。半导体封装上提供的(多个)集成电路和/或电子器件可能会彼此干扰或干扰其中集成了半导体封装的系统的其它电子部件。
附图说明
现在将参考附图，附图未必按比例绘制，并且在附图中：
图1A-图1H描绘了根据本公开的示例性实施例的具有基于沟槽模制的电磁干扰(EMI)屏蔽件的示例性半导体封装和制造过程的简化截面示意图。
图2A-图2D描绘了根据本公开的示例性实施例的示出了具有基于沟槽模制的EMI屏蔽的各种半导体封装的简化截面示意图。
图3A和图3B描绘了根据本公开的示例性实施例的示出了具有基于沟槽模制的EMI屏蔽的、其中具有多个管芯的各种半导体封装的简化截面示意图。
图4A和图4B描绘了根据本公开的示例性实施例的示出了在管芯和具有基于沟槽模制的EMI屏蔽件的半导体封装之间具有任何各种电气和机械耦合的半导体封装的简化截面示意图。
图5描绘了根据本公开的示例性实施例的示出了在一个或多个电子部件周围具有基于沟槽模制的EMI屏蔽的系统级封装(SiP)的简化截面示意图。
图6描绘了根据本公开的示例性实施例的示出了用于固化其上设置有插件的模制环氧树脂的版框、以及在系统级封装的表面上的模制件的所得到的沟槽的简化示意图，其中利用带有插件的版框固化模制环氧树脂。
图7描绘了根据本公开的示例性实施例的其上设置有插件的版框的简化截面示意图。
图8描绘了根据本公开的示例性实施例的示出了用于制造图1-图5的具有基于沟槽模制的EMI结构的半导体封装的示例性方法的流程图。
具体实施方式
下文参考附图更完整地描述本公开的实施例，附图中示出了本公开的示例性实施例。然而，本公开可以体现于很多不同形式，并且不应理解为限于本文阐述的示例性实施例；相反，提供这些实施例是以使本公开将是透彻且完整的，并且将向本领域的技术人员完整传达本公开的范围。在所有附图中，相似的附图标记指代相似、但未必相同或等同的元件。
以充足的细节描述了以下实施例，以使至少本领域技术人员能够理解和利用本公开。要理解的是，基于本公开，其它实施例会是显而易见的，并且可以做出过程、机械、材料、尺寸、处理设备和参数改变而不脱离本公开的范围。
在以下描述中，给出了许多具体细节以提供对本公开的各种实施例的透彻理解。然而将显而易见的是，可以在没有这些具体细节的情况下实践本公开。为了避免使本公开难以理解，一些公知的系统配置和工艺步骤可能不会被详尽地公开。同样，示出本公开的实施例的附图为半示意性且不成比例的，并且尤其是，一些尺寸是为了呈现清晰并且可以在附图中被放大。此外，在将多个实施例公开和描述为具有一些公共特征的情况下，为了例示、描述和对其理解的清晰和容易，一般将利用类似附图标记描述类似和相似特征，即使这些特征是不等同的。
本文使用的术语“水平”可以被定义为平行于平面或表面(例如，衬底表面)的方向，不论其取向如何。本文使用的术语“竖直”可以指正交于刚刚所述的水平方向的方向。可以相对于水平平面引用诸如“上”、“上方”、“下方”、“底部”、“顶部”、“侧面”(如在“侧壁”中)、“较高”、“较低”、“上部”、“之上”和“之下”等术语。本文使用的术语“处理”包括如形成所述结构所需的沉积材料或光致抗蚀剂、图案化、曝光、显影、蚀刻、清洁、烧蚀、抛光和/或去除材料或光致抗蚀剂。
本公开的实施例可以提供一种半导体封装和一种制造半导体封装的方法。在示例性实施例中，半导体封装可以具有一个或多个电磁干扰(EMI)屏蔽结构，如本文所述。如本文所公开的，可以使用利用固化模制环氧树脂在原位模制沟槽形成物的方法来制造具有EMI屏蔽结构的这些半导体封装。在示例性实施例中，使模制环氧树脂固化可以包括使用其上具有突出部的模制版框，其可以在固化期间压印模制环氧树脂并在固化之后在模制件中产生沟槽形成物。在示例性实施例中，突出部可以是版框上提供的任何适当材料的插件。突出部的长度可以大致是模制化合物的厚度，以使得模制件中形成的沟槽基本在模制件的整个厚度上延伸。模制件形成过程可以包括沉积模制化合物(例如，热固性环氧树脂)，并且然后使其热固化，同时在固化(例如，交联、硬化等)期间向模制化合物顶部施加接触部和/或压力。根据本公开的实施例，模制化合物固化可以包括在封装衬底之上对准版框，以使得在未固化模制化合物的表面之上施加版框期间，突出部与封装衬底表面上的特征对准。模制化合物表面之上的版框的对准可以涉及任何适当的对准机制，例如包括在封装衬底表面上形成对准掩模，并对准到那些标记。
在对准并施加到模制化合物表面时，具有突出部的版框可以被加热，例如加热到可以驱使模制化合物固化的温度。将要认识到，在固化过程期间，在模制化合物表面上的排列了版框的突出部的位置处，模制化合物可能被挤压或通过其它方式移位。于是，在封装衬底上的对应于版框上的突出部的这些位置处，可以在使模制件固化期间在模制化合物中形成沟槽。作为封装衬底之上对准版框的结果，可以形成覆盖在封装衬底表面上的接地迹线上的沟槽。
在示例性实施例中，半导体封装结构可以包括封装衬底。在一些情况下，封装衬底可以是有机结构。在其它情况下，封装衬底可以是无机的(例如，陶瓷、玻璃等)。在示例性实施例中，封装衬底包括芯层，在芯层一侧或两侧上构建有一个或多个互连层。包括至少一个集成电路管芯的一个或多个电子部件可以经由任何适当机制电气和机械耦合到封装衬底，所述适当机制例如是金属柱(例如，铜柱)、倒装芯片凸块、焊料凸块、任何类型的低铅或无铅焊料凸块、锡铜凸块、引线接合、楔形接合、受控塌缩芯片连接(C4)、各向异性导电膜(ACF)、非导电膜(NCF)、其组合等。可以在封装衬底的一侧或两侧上提供半导体封装到板级互连。在示例性实施例中，半导体封装到板级互连可以是球栅阵列(BGA)连接。
半导体封装可以具有提供于半导体封装表面上(例如半导体封装的顶部互连层上)的接地层。在其它情况下，半导体封装可以具有形成在处于封装衬底内的层中的接地平面，例如在不处于封装衬底表面上的封装芯层和/或构建层上的接地平面。为了对电子部件进行机械保护，可以在半导体封装的表面上的一个或多个电子部件顶部形成模制件。可以在封装衬底的一侧或两侧上提供半导体封装到板级互连。
根据示例性实施例，可以有在利用导电材料填充的模制件内具有沟槽的半导体封装。可以在模制环氧树脂固化期间在原位形成沟槽。根据相同或不同实施例，半导体封装还可以在模制材料的顶表面的至少一部分上具有导电材料。模制材料的顶部和沟槽内的导电材料可以彼此电耦合。在其它示例性实施例中，模制材料的顶部和模制材料沟槽内的导电材料可以被短接到半导体封装的接地平面。替代地，模制材料的顶部和模制材料的沟槽内的导电材料可以被短接到半导体封装的电源平面，或者通过其它方式被钳位到任何其它适当的直流(DC)电压。
在示例性实施例中，半导体封装可以具有由固化的导电油墨和/或固化的导电膏制造的侧壁。在示例性实施例中，导电油墨和/或膏都可以提供于模制件内形成的沟道内以及半导体封装的侧壁上。于是，集成电路和/或其它电子部件的个体或组可以被其中设置有导电材料的沟槽围绕，例如，以将集成电路和/或其它电子部件的个体或组与系统级封装(SiP)实施方式中的其它部件隔离。
可以通过涂塞(puddle up)用于填充在固化模制环氧树脂期间形成的沟槽的导电油墨来形成半导体封装顶部的导电材料。在这些示例性实施例中，设置于模制顶表面上的顶部导电层也可以由固化的导电油墨和/或固化的导电膏形成。在这些示例性实施例中，顶表面导电材料可以与设置于模制件的沟槽中和/或单一化(singulate)的半导体封装的侧壁中的导电材料基本相同。应当理解，可以在单个半导体封装衬底(例如，具有构建层的芯)上形成多个半导体封装。
替代地，可以通过在半导体封装模制件的顶部层压金属片(例如，铜层压件、铝层压件等)来设置半导体封装的顶部上的导电材料。在示例性实施例中，可以在模制表面上提供层压，其中在层压金属和模制顶表面之间有环氧树脂。在其它替代实施例中，导电材料可以通过物理气相沉积(PVD)而设置在半导体封装的顶部。
图1A-图1H描绘了根据本公开的示例性实施例的具有基于沟槽模制的电磁干扰(EMI)屏蔽件的示例性半导体封装和制造过程的简化截面示意图。
如本文所描绘的，可以实施各过程以同时或接近同时制造多个具有EMI屏蔽的半导体封装。可以利用任何各种过程或其顺序来制造半导体封装。尽管这里示出了特定的制造顺序来制造各种最终和/或暂时的结构和/或特征，但根据本公开的示例性实施例，可以实施制造类似特征的任何变化。再者，根据本公开的示例性实施例，可以有比本文针对半导体封装的制造所公开的特征更多和/或更少的特征。尽管这里描绘的截面示出了在封装衬底面板上同时制造的特定数量的半导体封装，但应当理解，在特定封装衬底面板上可以同时或接近同时制造任何数量的半导体封装。此外，尽管描绘了用于制造具有EMI屏蔽的半导体封装的过程顺序的示例性实施例，但将要认识到，通过本文所示的任何过程可以同时和/或接近同时处理任何数量的封装衬底面板。例如，一些过程可以是批处理，其中可以将特定单元(例如，封装衬底面板)连同另一个该单元一起处理。在其它情况下，可以在半成品(WIP)上以顺序方式执行单位过程。
在图1A中，描绘了根据本公开的示例性实施例的示例性半导体封装衬底100的示意性截面，其具有在封装衬底100内制造的接地平面102以及设置于其上的接地接触部104和电子部件106。半导体封装衬底100可以具有任何适当大小和/或形状。例如，在示例性实施例中，半导体封装衬底100可以是矩形面板。在示例性实施例中，半导体封装衬底100可以由任何适当材料制造，所述材料包括聚合物材料、陶瓷材料、塑料、复合材料、玻璃、玻璃纤维片的环氧树脂层压件、FR-4材料、FR-5材料、其组合等。衬底可以具有芯层以及芯层的任一侧上的任何数量的互连构建层。芯层和/或互连构建层可以是任何各种前述材料，并且在一些示例性实施例中，可以不由相同材料类型构造。
将要认识到，可以通过任何适当方式制造构建层。例如，构建互连的第一层可以包括提供封装衬底芯，其中形成或不形成通孔。可以在半导体衬底芯材料上层压电介质层压材料。可以使用任何适当机制，包括光刻、等离子体蚀刻、激光烧蚀、湿法蚀刻、其组合等，在构建层中图案化出通孔和/或沟槽。通孔和沟槽可以分别由竖直和水平金属迹线界定在构建层内。然后可以例如通过金属无电镀、金属电解电镀、物理气相沉积、其组合等利用金属填充通孔和沟槽。可以通过任何适当的机制，例如蚀刻、清洁、抛光和/或化学机械抛光(CMP)、其组合等，去除过多的金属。可以通过相同的前述过程形成芯的任一侧上的后续构建层(例如，更高层次的构建层)。
在示例性实施例中，接地平面102可以是半导体封装衬底100内的构建层(例如，具有互连的构建层)。在具有EMI屏蔽的最终封装衬底工作时，可以将接地平面短接到地，例如其上设置具有EMI屏蔽的最终封装衬底的印刷电路板(PCB)上的地。在示例性实施例中，接地平面可以电连接到一个或多个表面接地焊盘104。表面接地焊盘104可以是半导体封装衬底100的顶表面上的一个或多个焊盘和/或互连迹线(例如，表面布线迹线)。
半导体封装衬底100可以具有设置于其上的一个或多个电子部件或器件106。尽管出于例示的目的，图1A-图1H中描绘了每个半导体封装衬底100仅一个电子部件106，但将要认识到，根据本公开的示例性实施例，可以在具有EMI屏蔽的每个半导体封装中设置任何适当数量的电子部件106。电子部件106可以是任何适当的电子部件106，包括但不限于集成电路、表面安装器件、有源器件、无源器件、二极管、晶体管、连接器、电阻器、电感器、电容器、微机电系统(MEMS)、其组合等。电子部件106可以经由任何适当机制而电气和机械耦合到半导体封装衬底100，所述适当机制例如是金属柱(例如，铜柱)、倒装芯片凸块、焊料凸块、任何类型的低铅或无铅焊料凸块、锡铜凸块、引线接合、楔形接合、受控塌缩芯片连接(C4)、各向异性导电膜(ACF)、非导电膜(NCF)、其组合等。
在图1B中，根据本公开的示例性实施例，图1A的示例性半导体封装衬底100的示意截面被描绘为具有在其上提供的模制化合物108。模制化合物108可以设置于封装衬底100的顶表面上，并可以包封设置于半导体封装衬底100的表面上的表面接地焊盘104和/或电子部件106。模制化合物108可以是任何适当的模制材料。例如，模制化合物108可以是液体分配热固性环氧树脂模制化合物。可以使用包括但不限于液体分配、旋涂、喷涂、其组合等的任何适当的机制在半导体封装衬底100的表面上沉积模制化合物。
图1C是根据本公开的示例性实施例的图1B的示例性半导体封装衬底100的示意性截面，其中模制化合物108已准备好使用具有主体112和从主体112突出的突出部114的版框110来固化。该设置可以处于固化(例如，交联、硬化等)模制化合物的固化环境中。在示例性实施例中，可以将版框110与封装衬底100的表面上的特征(例如一个或多个对准标记)对准。在这些示例性实施例中，对准版框110可以导致版框上的突出部114对准封装衬底100的表面上的对应位置。这些可以是封装衬底上的可能希望有沟槽的位置。根据本公开的示例性实施例，可能希望有这种沟槽以用于利用导电材料进行填充，以形成电磁干扰(EMI)屏蔽。在示例性实施例中，版框可以对准在模制化合物108之上，以使得突出部114可以与表面接地焊盘104对准。实际上，这种对准可以导致形成覆盖表面接地焊盘104的沟槽。
图1D是根据本公开的示例性实施例的图1C的示例性半导体封装衬底100的示意性截面，其中版框110被移动116到模制化合物108中和上。在示例性实施例中，可以在版框110自身被加热的情况下将具有相对平坦的表面112并具有突出部114的版框110按压在设置在半导体封装衬底100顶部的液体模制化合物108顶部上。可以在由版框110在其上施加压力的同时，固化半导体封装衬底100的顶表面上的模制化合物108。在示例性实施例中，可以对准版框110，以使得突出部114被按压到希望将模制化合物108在半导体衬底100的表面上移位到的位置中。在一些示例性实施例中，突出部114可以与表面接地焊盘104中的一个或多个对准，以使得在版框110被施加模制化合物108之上时，模制化合物108被挤压或通过其它方式移位在那些一个或多个表面接地焊盘104之上。
图1E是根据本公开的示例性实施例的图1D的示例性半导体封装衬底100的示意性截面，其中版框110被移动118离开模制件120。在固化(例如，交联)时，在与版框110接触的同时，沉积的模制化合物108可以硬化并形成模制件120以粘附到半导体封装衬底100并包封电子部件106。在示例性实施例中，模制件120中可以具有填充物和/或其它材料，以优选地控制热膨胀系数(CTE)，减小应力，赋予阻燃性，促进粘附，和/或减少模制件120中的水分吸收。在示例性实施例中，模制件120可以是任何适当厚度。例如，模制件108可以大致为1毫米(mm)厚。在其它情况下，模制件108可以大致在大约200微米(μm)和800μm之间厚。在其它情况下，模制件108可以大致在大约1mm和2mm之间厚。
根据示例性实施例，模制件120中可以形成有沟槽122。这些沟槽122可以形成于模制件120的对应于版框110的突出部114的位置中。在一些示例性实施例中，沟槽122可以覆盖在封装衬底100的表面上的表面接地焊盘104上。在示例性实施例中，这些沟槽120可以并非完全开放到下方表面接地焊盘的表面。于是，在沟槽122的底部可能有残余物124。在示例性实施例中，残余物124可以是留在沟槽122底部的相对少量的模制件。
在图1F中，根据本公开的示例性实施例，图1E的示例半导体封装衬底100的示意性截面被描绘为残余物124已被去除。残余物去除工艺可以涉及任何各种蚀刻和/或清洁工艺，以形成沟槽126。在示例性实施例中，沟槽126可以比沟槽124更宽。此外，在示例性实施例中，沟槽126可以在其底部没有残余物，并且可以开放到下方的表面接地焊盘104。可以通过任何适当的蚀刻和/或清洁工艺去除残余物124，所述工艺包括激光烧蚀、湿法蚀刻、干法蚀刻、等离子体蚀刻、湿法清洁、声波清洁、其组合等。在一些示例性实施例中，可以选择(多种)清洁和/或蚀刻工艺的类型和/或顺序，以使得与竖直蚀刻相比，横向蚀刻相对最小化。换言之，可以优化蚀刻和/或清洁工艺，以更定向地去除残余物124，其与沟槽122相比不会显著加宽沟槽126。
沟槽126可以形成于其中要在具有EMI屏蔽的最终半导体封装上形成EMI屏蔽的竖直部分(任选地包括半导体封装侧壁)的位置中。在示例性实施例中，可以形成沟槽126，以使得沟槽126的底部一直开放到表面接地焊盘和/或迹线104。在一些示例性实施例中，沟槽126的每个非连续段都可以开放到至少一个表面接地焊盘104，以使得最终EMI屏蔽的所有段都可以接地。在一些示例性实施例中，用于去除残余物124的机制(例如，激光烧蚀、蚀刻等)可以相对于表面接地焊盘104的材料(例如，铜、铝等)选择性地去除模制材料。
沟槽126的宽度可以是任何适当宽度。在示例性实施例中，根据本公开的示例性实施例，沟槽126可以大致为最终用于锯开和/或单一化半导体封装衬底100以形成具有基于沟槽模制的EMI屏蔽的半导体封装中的每者的锯片的锯缝宽度。在其它示例性实施例中，沟槽126可以比最终用于单一化个体半导体封装的锯的锯缝更宽。在一些情况下，沟槽126的宽度可以为大致500μm。在其它情况下，沟槽126的宽度可以大致在大约100μm到500μm的范围中。
在图1G中，根据本公开的示例性实施例，描绘了具有带有经填充的沟槽的模制件120的示例性半导体封装衬底100。沟槽可以被填充有任何适当的导电材料，例如导电油墨128和/或导电膏。导电油墨128可以进一步涂塞在模制件120的顶表面上，以形成EMI屏蔽的顶部分。诸如导电膏的导电油墨128可以被分配在模制件120的顶表面上并且可以接下来填充沟槽126。可以通过旋转沉积、喷洒沉积、丝网印刷、挤压工艺和/或任何其它适当的沉积工艺在模制件120表面上设置导电油墨128。在示例性实施例中，导电油墨128可以润湿模制件120，并且因此可以在范德瓦尔斯力和/或毛细作用的驱动下填充沟槽126。在相同或其它示例性实施例中，可以通过机械力，例如通过挤压工艺，迫使导电油墨128进入沟槽126中。在其它示例性实施例中，可以优选使用丝网印刷工艺，例如通过将图案化的丝网对准在模制件120的表面顶部上，来沉积导电油墨128。
导电油墨128可以是其中悬浮有金属纳米颗粒或微颗粒的环氧树脂材料。在示例性实施例中，导电油墨128中可以悬浮有银(Ag)纳米颗粒。在其它示例性实施例中，导电油墨128中可以悬浮有铜、锡、铁、金的纳米颗粒、其组合等。在一些实施例中，导电油墨128中可以悬浮有非金属导电颗粒。除了在导电油墨128中具有导电材料之外，还可以有其它化学试剂以调整导电油墨128的物理、电气和/或处理性质。在示例性实施例中，导电油墨128可以具有溶剂，溶剂可以允许导电油墨128具有针对沟槽填充可能相对优选的粘度，同时提供粘度和/或粘着性的快速增大，以呈现在沟槽126中。在相同或其它示例性实施例中，导电油墨128可以具有还原剂以防止或减少导电油墨128中可能悬浮的金属颗粒的氧化。再者，导电油墨128可以包含一定比例的填充物颗粒(例如，碳纤维、二氧化硅颗粒、陶瓷等)，其为导电油墨128提供期望的性质，例如优选的粘度范围、优选的粘着性范围、优选的疏水性(例如，表面润湿)范围、优选的颗粒悬浮性质范围、优选的固化温度范围、其组合等。
在一些示例性实施例中，导电油墨128可以通过如下方式被提供于模制件120上：首先提供优选地填充沟槽126内的间隙的粘度较小的导电油墨，并且然后提供粘度更大的导电油墨，其涂塞在模制件120顶部，以提供EMI屏蔽的顶部部分。在一些示例性实施例中，导电油墨128的粘度可以被导电油墨128中混入的溶剂的量改变。在替代实施例中，并非在模制件120的顶表面之上提供导电油墨128，可以通过例如层压来提供金属片，或者可以采用其它金属沉积机制，例如PVD。
图1H描绘了根据本公开的示例性实施例的图1G的封装衬底100的示意性截面，其已经被单一化以形成具有EMI屏蔽132的个体半导体封装。在半导体封装衬底100上制造的具有基于沟槽模制的EMI屏蔽132的个体半导体封装可以通过切割穿过每个个体半导体封装的边缘而被单一化，以在它们之间提供间隔130。可以使用激光烧蚀、锯开或任何其它适当的机制来执行单一化。在使用激光烧蚀的示例性实施例中，相邻半导体封装132之间的烧蚀宽度可以小于相邻半导体封装132之间的导电油墨128填充的沟槽的宽度。在实施锯切割的其它示例性实施例中，相邻半导体封装132之间的锯缝宽度可以小于相邻半导体封装之间的导电油墨128填充的沟槽的宽度。在这些示例性实施例中，其中半导体封装132之间的单一化的切割宽度小于导电油墨填充的沟槽的宽度，单一化的半导体封装132将在其侧壁(例如，沿其周边)上具有导电油墨(例如，固化的导电油墨)。该导电油墨侧壁可以被接地(例如，电连接到表面接地焊盘104，表面接地焊盘104进一步连接到接地平面层102)以形成半导体封装的EMI屏蔽的侧壁部分。EMI屏蔽的顶部可以由半导体封装132的顶部上的导电油墨128形成。
将要认识到，结合图1A-图1H所述的过程可以形成围绕设置于半导体封装的表面上的一个或多个电子部件106的电磁屏蔽。EMI屏蔽可以具有包封电子部件106的顶部部分和侧壁。半导体封装的侧壁可以具有EMI屏蔽，其形式为沿半导体封装132周边并从半导体封装132的顶部到底部的导电油墨侧壁。此外，可以有不沿这些具有EMI屏蔽的单一化半导体封装的周边的竖直部分(例如，导电油墨填充的沟槽)。在这些情况下，在SiP配置中，可以将半导体封装上的一些电子部件106从半导体封装132上的其它电子部件106屏蔽。例如，可以使用EMI屏蔽的竖直部分将较高频率信号的放大器与半导体封装上的其它电子部件隔离，以防止放大器向SiP的其它部件中注入电磁噪声。在替代实施例中，应当理解，可以使用层压金属或PVD沉积金属形成EMI屏蔽的顶部和/或侧壁。
图2A-图2D描绘了根据本公开的示例性实施例的示出了具有基于沟槽模制的EMI屏蔽200、216、218、220的各种半导体封装的简化截面示意图。尽管图2A-图2D描述了具有基于沟槽模制的EMI屏蔽200、216、218、220的半导体封装的各种实施例，但根据本公开的示例性实施例，将要认识到，这些实施例为示例，并且本公开决不受图2A-图2D中所述的变化的限制。
图2A是示出了根据本公开的示例性实施例的根据图1A-图1G的过程制造的半导体封装200的简化截面示意图。半导体封装200包括封装衬底202、接地平面204、表面接地焊盘或迹线206、电子部件208、包封电子部件208的模制件210、基于导电油墨的导电侧壁216、以及覆盖模制件210的基于导电油墨的顶部部分。接触表面接地焊盘206并进一步接触导电顶部214的导电侧壁216可以为封装200提供EMI屏蔽。根据示例性实施例，可以通过在模制件固化过程期间使用用于固化模制件210的版框上的突出部形成沟槽，来形成导电侧壁216。接下来可以清洁这些沟槽和/或将这些沟槽打开到下方的表面接地焊盘206。接下来，可以利用导电油墨填充沟槽，导电油墨涂塞模制件210的表面之上。替代地，可以执行间隙填充导电油墨过程，接着是第二顶部导电油墨沉积过程。在该示例性实施例中，可以在导电油墨间隙填充过程中使用粘度较低的导电油墨，以实现相对好的间隙填充性能，并可以在顶部导体沉积过程中使用粘度较大的导电油墨，以增强粘着性。
图2B是示出了根据本公开的示例性实施例的具有基于导电油墨的导电侧壁212的半导体封装216的简化截面示意图，所述侧壁212向下延伸到接地平面204和EMI屏蔽的基于导电油墨的顶部部分214。在该示例性实施例中，与图2A的半导体封装200相比，可以有较少的或者没有导电侧壁220的表面接地焊盘连接。在该示例性实施例中，沟槽形成可以使得沟槽被形成到封装衬底202中，直到沟槽在接地平面204层上着陆。在该情况下，半导体封装216的设计规则可以使得覆盖其中导电侧壁220向下延伸到接地平面204的区域的互连层可以具有无电路的排除区域，以允许导电侧壁212延伸到封装衬底202中。在具有基于沟槽模制的EMI屏蔽216的半导体封装的该实施例中，可以形成用于形成EMI屏蔽的导电侧壁238的沟槽，以使得它们延伸通过模制件以及封装衬底202顶部的构建层。
图2C是示出了根据本公开的示例性实施例的具有基于导电油墨的导电侧壁212的半导体封装218的简化截面示意图，其中表面接地焊盘或迹线206在封装衬底202的表面上。在该实施例中，在封装衬底的互连层内可以没有接地平面。由固化的导电油墨形成的导电侧壁212可以接触封装衬底202的表面上的接地焊盘206，以形成EMI屏蔽连同顶部导体214。在示例性实施例中，可以通过在对模制件210中形成的沟槽进行间隙填充时，使导电油墨涂塞在模制件210的顶部之上，来由导电油墨或导电膏制造EMI屏蔽的顶部部分214。替代地，可以执行间隙填充导电油墨过程，接着是第二顶部导电油墨沉积过程。在该示例性实施例中，可以在导电油墨填充间隙过程中使用粘度较低的导电油墨，以实现相对好的间隙填充性能，并且可以在顶部导体沉积过程中使用粘度较大的导电油墨，以增强粘着性。
图2D是示出了根据本公开的示例性实施例的具有EMI屏蔽的基于导电油墨的导电侧壁212和基于导电油墨的顶部部分214的半导体封装220的简化截面示意图。在示例性实施例中，可以通过在对模制件210中形成的沟槽进行间隙填充时，使导电油墨涂塞在模制件210的顶部之上，来由导电油墨或导电膏制造EMI屏蔽的顶部部分214。在示例性实施例中，可以使沟槽一直延伸通过半导体衬底。在该情况下，半导体封装220的设计规则可以使得覆盖其中导电侧壁212向下沿封装衬底202的整个宽度延伸的区域和位于该区域下方的互连层可以具有无电路的排除区域，以允许导电侧壁228延伸穿过封装衬底202。
图3A和图3B描绘了示出了根据本公开的示例性实施例的具有基于沟槽模制的EMI屏蔽314、316的、其中提供有多个管芯308、310的半导体封装300、320的简化截面示意图。
图3A描绘了示出了具有堆叠管芯配置的、具有基于沟槽模制的EMI屏蔽的半导体封装300的简化截面示意图。尽管这里描绘了两个管芯(例如，集成电路)308、310，但将要认识到，可以有任何适当数量的管芯堆叠于半导体封装300内。如所示，第一管芯308可以设置于封装衬底302上。封装衬底302可以具有接地构建层304和表面接地焊盘或迹线306。第一管芯308可以通过任何适当机制电气和机械附接到封装衬底，所述适当机制包括但不限于金属柱(例如，铜柱)、倒装芯片凸块、焊料凸块、任何类型的低铅或无铅焊料凸块、锡铜凸块、引线接合、楔形接合、C4、ACF、NCF、其组合等。
第二管芯310可以对准并附接到第一管芯308顶部。在一些示例性实施例中，第二管芯310可以以面向下配置附接到第一管芯308，并且在替代实施例中，第二管芯310可以以面向上配置附接到第一管芯308。在以面向下配置设置第二管芯310的情况下，第一管芯308可以采用面向上配置，并且第二管芯310的所有输入/输出(I/O)连接可以通过面到面连接通往第一管芯308。在该配置中，可以经由第一管芯308，例如经由从第一管芯308到封装衬底302的引线接合连接来抽取来自第二管芯310的I/O信号。替代地，在以面向下配置设置第二管芯310时，第一管芯308也可以采用面向下配置，并且可以具有穿硅过孔(TSV)以经由第一管芯308中的TSV将第二管芯310的I/O连接到封装衬底302。在其它示例性实施例中，两个管芯308、310都可以以面向上配置设置，并可以使用从每个管芯308、310到封装衬底302上的焊盘和/或第二管芯310和第一管芯308之间的引线接合来制作两个管芯308、310的I/O连接。在一些示例性实施例中，可以为管芯308、310之一或两者制作基于TSV的连接和引线接合连接两者。在其它示例性实施例中，管芯308、310之一可以是内插器管芯，用于制作高密度连接的目的，以提供更大的扇出比和/或提供相对更可靠的I/O连接。
继续图3A，半导体封装300可以具有包封管芯308、310的模制件312。沿半导体封装300的周边还可以有导电侧壁314。如上所述，导电侧壁314可以由固化的导电油墨和/或导电膏形成。半导体封装300还可以包括顶部导电部分316。顶部导电部分316也可以由固化的导电油墨构造。根据本公开的示例性实施例，导电侧壁314和电连接到表面接地焊盘306的顶部导电部分316的组合提供了EMI屏蔽。
图3B描绘了示出了具有横向设置的管芯配置的具有EMI屏蔽的半导体封装320的简化截面示意图。尽管这里描绘了两个管芯(例如，集成电路)322、324，但将要认识到，可以有任何适当数量的管芯提供于半导体封装320内。如所示，第一管芯322和第二管芯324都可以设置于封装衬底302上并可以由模制件312包封。封装衬底302可以具有接地构建层304和表面接地焊盘或迹线306。第一管芯322和第二管芯324可以通过任何适当机制电气和机械附接到封装衬底302，所述适当机制包括但不限于金属柱(例如，铜柱)、倒装芯片凸块、焊料凸块、任何类型的低铅或无铅焊料凸块、锡铜凸块、引线接合、楔形接合、C4、ACF、NCF、其组合等。将要认识到，在一些情况下，可以使用相同的机制将两个管芯322、324都附接到衬底，并且在其它情况下，可以使用不同的机制附接管芯322、324。沿半导体封装320的周边可以有导电侧壁314。如上所述，导电侧壁314可以由固化的导电油墨和/或导电膏形成。半导体封装300还可以包括顶部导电部分316。顶部导电部分316也可以由固化的导电油墨构造。根据本公开的示例性实施例，导电侧壁314和电连接到表面接地焊盘306的顶部导电部分316的组合提供了EMI屏蔽。
图4A和图4B描绘了根据本公开的示例性实施例的示出了在管芯和具有基于沟槽模制的EMI屏蔽400、430的半导体封装之间具有任何各种电气和机械耦合的半导体封装400、430的简化截面示意图。
图4A描绘了示出具有使用铜柱416附接到封装衬底402的管芯414的半导体封装400的简化截面示意图。封装衬底402可以具有提供于封装衬底402的表面上的接地平面404以及一个或多个接地焊盘接触部406。如本文所述，管芯414可以由模制件408包封，并且模制件408上可以设置有导电侧壁412和导电顶部410，其中导电侧壁412和导电顶部410短接到表面接地焊盘接触部406，以形成EMI屏蔽。
铜柱416可以是任何适当大小。例如，铜柱416的宽度可以大致在大约10μm到大约150μm的范围中。可以通过任何适当机制将管芯416对准并附接到半导体衬底。例如，热超声工艺可以用于使用金/镍、锡/铅或任何适当的冶金术将铜柱416熔合到封装衬底上的对应焊盘。作为另一示例性实施例，波焊接工艺可以用于将管芯414附接到封装衬底402。在示例性实施例中，可以在铜柱416周围、在管芯414和封装衬底402之间提供底部填充材料418。底部填充418中的代表性环氧树脂材料可以包括胺环氧树脂、咪唑环氧树脂、酚醛环氧树脂或酸酐环氧树脂。底部填充材料的其它示例包括聚酸亚胺、苯并环丁烯(BCB)、双马来酰亚胺型底部填充、聚苯并恶嗪(PBO)底部填充或聚降冰片烯底部填充。此外，底部填充材料418可以包括填充物材料，例如二氧化硅。可以通过旋涂、挤压涂布或喷涂技术引入底部填充材料418。在另一个实施例中，底部填充材料418包括标准制造钝化材料，例如无机钝化材料(例如，氮化硅、氮氧化硅)或有机钝化材料(例如，聚酸亚胺)。
如上所述，封装衬底402可以在衬底芯的任一侧上具有构建层。在一些情况下，可以使用无芯封装衬底402。在示例性实施例中，可以在封装衬底402上提供用于封装级I/O的接触部420。接触部420可以是任何适当的接触部，例如球栅阵列(BGA)或其它区域阵列接触部420。
图4B描绘了根据本公开的示例性实施例的示出具有使用引线接合436、438附接到封装衬底402的两个管芯432、434的半导体封装430的简化截面示意图。封装衬底402可以具有提供于封装衬底402表面上的接地平面404和一个或多个接地焊盘接触部406。如本文所述，管芯432、434可以由模制件408包封，并且模制件408上可以设置有导电侧壁412和导电顶部410，其中导电侧壁414和导电顶部412短接到表面接地焊盘接触部406，以形成EMI屏蔽。在示例性实施例中，可以在封装衬底402上提供用于封装级I/O的接触部420。接触部420可以是任何适当的接触部，例如球栅阵列(BGA)或其它区域阵列接触部420。
图5描绘了根据本公开的示例性实施例的示出了在一个或多个电子部件508、510、512、514周围具有基于沟槽模制的EMI屏蔽的系统级封装(SiP)500的简化截面示意图。SiP500可以具有封装衬底502，封装衬底502具有接地平面504以及一个或多个表面接地焊盘和/或迹线506。可以通过任何适当的配置并利用通往封装衬底的任何适当电连接提供电子部件508、510、512、514。例如，电子部件508和510设置于堆叠配置中。SiP 500可以具有包封电子部件508、510、512、514的模制件516。SiP 500还可以具有设置于模制件中的竖直导电结构522、524。这些竖直导电结构522、524可以是固化的导电油墨和/或导电膏。于是，在固化时，竖直导电结构522、524可以具有其中设置了导电颗粒的环氧树脂。该导电环氧树脂可以形成EMI屏蔽结构的竖直部分。SiP 500还可以包括设置于模制件516顶部的水平导电材料518。可以通过将导电油墨涂塞在模制件516的顶表面之上并固化该导电油墨，来在模制件516的顶表面上形成水平导电材料518。水平导电材料518可以电连接到竖直导电结构522、524和表面接地焊盘和/或迹线506。根据本公开的示例性实施例，竖直导电结构522、524中的一些可以是半导体封装的周边上的侧壁导电结构522，并且其它竖直导电结构524可以是内部竖直导电结构，以防止同一SiP 500中提供的电子部件508、510、512、514之间的EMI。例如，竖直导电结构524可以将电子部件508、510的组合所导致的EMI与电子部件512、514隔离。
图6描绘了根据本公开的示例性实施例的示出了用于固化其上设置有插件604的模制环氧树脂的版框600、以及在系统级封装610的表面上的模制件612的所得到的沟槽620的简化示意图，其中利用带有插件604的版框600固化模制环氧树脂。插件或突出部604可以是任何适当的材料，例如包括经过或未经过表面处理的任何各种金属，以减小对未固化模制化合物的粘着性。插件604可以从版框600的平坦部分602突出。在一些示例性实施例中，插件604可以被钎焊和/或熔焊到版框600的平坦部分602上。替代地，可以在版框的平坦部分602中提供的槽中提供插件604。
一旦翻转版框600以将环氧树脂612固化在封装衬底610上，就可以在模制件612中形成沟槽620。将要认识到，要在使用版框600固化时形成到模制件612中的模制化合物可以包封设置于衬底610上的各种电子部件，例如各种集成电路614、连接器616和表面安装器件(SMT)618。如所示，可以既沿封装衬底610的边缘又在封装衬底620的内部部分内形成模制件612中的沟槽620。在示例性实施例中，由于在固化过程之前将版框600对准到封装衬底的对准过程，可以在封装衬底上的接地焊盘或接地迹线之上对准沟槽620。对准过程可以涉及利用光学对准耦合的精确放置设备。可以将封装衬底610的表面上的基准和/或对准标记用于将版框600对准到封装衬底610的目的。
将要认识到，在一些示例性实施例中，版框600的突出部604可以具有经表面修整的表面和/或涂层，其可以减小模制化合物对突出部604的表面的粘着性。例如，在一些示例性实施例中，突出部可以具有沉积于其上的聚四氟乙烯(PTFE)涂层。还要认识到，在一些示例性实施例中，可以在固化过程期间振动版框600，以减小模制化合物对版框600的插件604的粘着性。在一些示例性实施例中，插件604的高度可以大体上类似于模制化合物的厚度。
图7描绘了根据本公开的示例性实施例的其上设置有插件704的版框700的简化截面示意图。在示例性实施例中，插件704可以大体上沿法线方向从版框700的平坦部分702延伸。在一些示例性实施例中，插件704可以被钎焊到平坦部分702上。在其它情况下，可以通过任何适当机制将插件704固定到平坦部分702，所述机制包括但不限于粘合剂、机械槽、凸台、熔焊、静电吸引、其组合等。在示例性实施例中，插件704可以具有中央部分706和其上的涂层708。可以提供涂层708以减少和/或防止模制化合物粘着到插件704。在一些示例性实施例中，可以使用PTFE涂布插件704。
图8描绘了根据本公开的示例性实施例的示出用于制造图1-图5的具有基于沟槽模制的EMI结构的半导体封装的示例性方法800的流程图。
在方框802，可以在衬底上组装管芯和其它部件。此时，衬底可以是衬底面板，可以在其上同时或接近同时制造多个半导体封装。衬底(例如，面板形式)可以具有形成于其上的构建层，并可以处于可以在其上形成管芯和/或其它结构的级上。管芯可以是任何适当的电子器件，例如基于半导体的电子器件。在示例性实施例中，管芯可以是具有至少一个有源器件(例如，晶体管、二极管等)和/或无源器件(例如，电阻器、电感器、电容器等)的集成电路(IC)。
在方框804，可以在衬底上沉积可以包封管芯和其它部件的模制化合物。如上所述，在示例性实施例中，可以通过任何适当的机制提供模制化合物，所述机制包括但不限于旋涂、喷涂、使用丝网印刷的分配、其组合等。可以将模制化合物沉积到足以包封衬底表面上的管芯和/或其它部件的厚度。在示例性实施例中，模制化合物可以是热固性化合物。在一些情况下，模制化合物可以具有提供于其中的一种或多种填充物材料，以设计模制件的各种物理、电气和/或热性质。
在方框806，可以使用具有突出部的版框在模制化合物上施加压力和热量，以形成包封管芯和其它部件的模制件，并且在该模制件中具有沟槽。将要认识到，在模制件的其中突出部使模制化合物移位的区域中形成的沟槽可以覆盖封装衬底上的接地接触部。向模制化合物施加具有突出部的版框并加热模制化合物可以导致模制化合物的固化过程，其中模制化合物被交联和/或硬化，以形成模制件。在一些示例性实施例中，可以修改固化的过程以导致模制化合物对版框的突出部的粘着性减小。例如，可以使用较小的横向移动(例如，沿封装衬底的平面的振动)减小粘着到突出部的量。模制化合物的固化温度可以大致在大约100℃到大约250℃的范围中。在一些示例性实施例中，固化温度可以大致在大约150℃到大约200℃的范围中。
在方框808，可以执行激光烧蚀、蚀刻和/或清洁工艺以去除沟槽底部的模制件残余物。尽管在方框806的固化过程期间在原位形成了沟槽，但沟槽可能并非始终可靠地开放到下方的地焊盘和/或迹线。结果，可以采用任何各种工艺以用于去除沟槽底部的残余物。可以通过诸如激光烧蚀、湿法蚀刻、干法蚀刻或其任何组合的任何各种机制来清洁沟槽。在一些示例性实施例中，用于清洁沟槽底部的模制件残余物的工艺也可能导致沟槽的横向蚀刻(例如，加宽)。在这些实施例中，可以调整残余物清洁工艺，以用于获得在竖直方向的蚀刻具有比在横向方向上更大的速率的更大的方向性。
在方框810，可以向模制件的顶表面施加导电材料。可以利用导电材料填充由方框806和808的过程形成的模制件中的沟槽。此外，可以在模制件顶部之上涂塞导电材料以形成EMI屏蔽的顶部水平部分。在示例性实施例中，导电材料可以是导电油墨和/或导电膏。导电油墨或导电膏可以是其中提供(例如，悬浮)有导电颗粒的环氧树脂材料。导电油墨和/或导电膏中可以包括其它材料，例如还原剂、填充物等。在示例性实施例中，可以通过旋涂、喷涂、挤压和/或丝网印刷工艺沉积导电油墨和/或导电膏。在一些情况(例如，丝网印刷)下，导电油墨和/或导电膏的沉积可以在要填充的模制沟槽中和/或附近。在一些情况下，导电油墨和/或导电膏可以是触变材料，并且因此可以优选流入沟槽并然后呈现为相对更刚性的形式。在其它示例性实施例中，可以沉积第一粘度相对较低且相对更多间隙填充的导电油墨，以填充沟槽，并且然后可以在其上沉积更高粘度的导电油墨，以形成EMI屏蔽的顶部部分。
在方框812，可以固化导电材料。固化温度可以大致在大约100℃到大约250℃的范围中。在一些示例性实施例中，固化温度可以大致在大约150℃到大约175℃的范围中。
在方框814，可以将封装中的每者单一化。可以通过任何适当机制，例如通过激光烧蚀或锯切割来进行单一化。如果使用激光烧蚀，那么切割宽度可以小于被填充的沟槽的宽度。根据本公开的示例性实施例，通过这种方式，在通过切割半导体衬底面板将半导体封装彼此单一化时，导电材料(例如，固化的导电油墨、固化的导电膏等)可以保留在切口的两侧上并在相邻半导体封装上提供EMI屏蔽的导电侧壁。
应该指出的是，如本文公开的，方法800可以实现用于制造半导体封装的电磁干扰屏蔽件的相对可靠的机制。为EMI屏蔽件使用导电油墨可以提供与诸如导电材料的物理气相沉积(PVD)的其它方法相比更成本高效的制造EMI屏蔽的机制。此外，在模制化合物固化过程期间在模制件中在原位形成沟槽可以实现相对有效率的、成本高效且相对可靠的用于形成其中形成EMI屏蔽的竖直部分的沟槽的机制。此外，与形成EMI屏蔽的其它方法相比，在模制件内形成沟槽并利用相对更顺应性材料填充那些沟槽可以提供应力缓解和用于改善半导体封装的可靠性的其它机制。
应该指出的是，可以根据本公开的特定实施例通过各种方式修改方法800。例如，在本公开的其它实施例中，可以去掉或不按照次序执行方法800的一个或多个操作。此外，根据本公开的其它实施例，可以向方法800增加其它操作。
将要认识到，本文描述的设备可以是任何适当类型的微电子封装及其配置，例如包括系统级封装(SiP)、封装上系统(SOP)、堆叠封装(PoP)、内插器封装、3D堆叠封装等。事实上，如本文所述，可以在具有EMI屏蔽的半导体封装中提供任何适当类型的微电子部件。例如，如本文公开的，可以在具有EMI屏蔽的半导体封装中封装微控制器、微处理器、基带处理器、数字信号处理器、存储器管芯、现场门阵列、存储器管芯、逻辑门管芯、无源部件管芯、MEMS、表面安装器件、专用集成电路、基带处理器、放大器、滤波器、其组合等。可以在任何各种电子装置中提供如本文所公开的具有EMI屏蔽的半导体封装，所述电子装置包括消费、工业、军事、通信、基础设施和/或其它电子装置。
如本文所述，可以使用具有EMI屏蔽的半导体封装来容纳一个或多个处理器。一个或多个处理器可以包括但不限于中央处理单元(CPU)、数字信号处理器(DSP)、精简指令集计算机(RISC)、复杂指令集计算机(CISC)、微处理器、微控制器、现场可编程门阵列(FPGA)或其任何组合。处理器还可以包括用于处理特定数据处理功能或任务的一个或多个专用集成电路(ASIC)或专用标准产品(ASSP)。在某些实施例中，处理器可以基于架构系统，并且电子装置中包括的一个或多个处理器和任何芯片组可以来自处理器和芯片组系列，例如处理器系列或Intel-64处理器(例如，SandyIvy等)。
此外或替代地，可以使用如本文所述的具有EMI屏蔽的半导体封装来容纳一个或多个存储器芯片。存储器可以包括一种或多种易失性和/或非易失性存储器装置，包括但不限于磁性存储装置、只读存储器(ROM)、随机存取存储器(RAM)、动态RAM(DRAM)、静态RAM(SRAM)、同步动态RAM(SDRAM)、双数据率(DDR)SDRAM(DDR-SDRAM)、RAM-BUS DRAM(RDRAM)、闪速存储器装置、电可擦可编程只读存储器(EEPROM)、非易失性RAM(NVRAM)、通用串行总线(USB)可移除存储器或其组合。
在示例性实施例中，其中提供具有EMI屏蔽的半导体封装的电子装置可以是计算装置。这种计算装置可以容纳一个或多个板，在板上可以设置具有EMI屏蔽的半导体封装。板可以包括若干部件，包括但不限于处理器和/或至少一个通信芯片。处理器可以通过例如具有EMI屏蔽的半导体封装的电连接而物理和电气连接到板。计算装置还可以包括多个通信芯片。例如，第一通信芯片可以专用于诸如Wi-Fi和蓝牙的短程无线通信，并且第二通信芯片可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO等长程无线通信。在各种示例性实施例中，计算装置可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、手机、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、数字视频录像机、其组合等。在其它示例性实施例中，计算装置可以是处理数据的任何其它电子装置。
本文已经描述了各种特征、方面和实施例。如本领域技术人员将理解的，所述特征、方面和实施例容易彼此组合以及进行变化和修改。因此，本公开应当被视为涵盖这样的组合、变化和修改。
本文采用的术语和表达被用作描述术语而非限制，并且在使用这样的术语和表达时，并非旨在排除图示和描述的特征的任何等同物(或其部分)，并且认识到，在权利要求的范围内各种修改是可能的。其它修改、变化和替代也是可能的。因此，权利要求旨在覆盖所有这样的等同物。
尽管本公开包括各种实施例，至少包括最佳模式，但要理解的是，考虑前面的描述，很多替代、修改和变化对于本领域技术人员将是显而易见的。因此，本公开旨在涵盖落在所包括的权利要求的范围内的所有这样的替代、修改和变化。本文公开或附图中示出的所有主题要被解释为例示性而非限制性意义。
本书面描述使用示例公开本公开的特定实施例，包括最佳模式，并且还使得本领域技术人员能够实践本公开的特定实施例，包括制造并使用任何设备、装置或系统以及执行任何并入的方法和过程。本发明的特定实施例的可专利范围在权利要求中界定，并且可以包括本领域的技术人员想到的其它示例。如果它们具有不和权利要求的文字语言不同的结构元件，或者如果它们包括具有与权利要求的文字语言非显著不同的等同的结构元件，则这样的其它示例旨在处于权利要求的范围内。
根据本公开的示例性实施例，可以存在一种微电子封装，包括：具有顶部衬底表面和衬底外周边的衬底，顶部衬底表面上安装有电子部件并且顶部衬底表面具有导电迹线，该导电迹线沿衬底外周边的至少一部分设置；在顶部衬底表面之上提供的模制化合物，具有底部模制表面、顶部模制表面，以及大体上覆盖衬底外周边的模制侧壁；以及在模制侧壁上并覆盖顶部模制表面的环氧树脂，其中环氧树脂包括导电颗粒，并且其中覆盖顶部模制表面的环氧树脂和在模制侧壁上的环氧树脂电耦合。在示例性实施例中，环氧树脂进一步电耦合到导电迹线。在其它示例性实施例中，导电迹线电连接到如下中的至少一者：(i)地，(ii)直流(DC)电压，或(iii)微电子封装的电源线电压。在其它示例性实施例中，衬底包括芯层和具有金属线的至少一个构建层，其中金属线至少包括导电迹线。在其它示例性实施例中，模制化合物包括热固性环氧树脂化合物。
根据本公开的示例性实施例，模制件包括从底部模制表面延伸到顶部模制表面并电连接到被提供为覆盖顶部模制表面的环氧树脂的导电结构。在其它示例性实施例中，环氧树脂包括如下中的至少一者：(i)固化的导电油墨，(ii)固化的导电膏，或(iii)银纳米颗粒。在其它示例性实施例中，电子部件是第一电子部件，并且其中微电子封装还包括：第二电子部件；以及电连接到导电迹线和提供在顶部模制表面上的环氧树脂的导电结构，该导电结构设置于第一电子部件和第二电子部件之间，在形成于模制件中的从底部模制表面延伸到顶部模制表面的沟槽中。在其它示例性实施例中，微电子封装还包括设置于衬底的底部衬底表面上的多个封装到板电连接。
根据本公开的示例性实施例，可以存在一种方法，包括：提供具有面板顶表面的封装衬底面板；将第一电子部件和第二电子部件电气附接到面板顶表面；在面板顶表面上沉积模制化合物，其中模制化合物包封第一电子部件和第二电子部件；向模制化合物的顶表面施加版框以固化模制化合物，以形成模制件，该版框具有平坦部分和从平坦部分沿平坦部分的大体上法线方向延伸的一个或多个突出部，该模制件具有顶部模制表面和接触面板顶表面的底部模制表面，其中模制件包括对应于版框的突出部的一个或多个沟槽；以及利用环氧树脂填充一个或多个沟槽，其中环氧树脂包括导电颗粒。在示例性实施例中，该方法还包括通过填充的一个或多个沟槽中的第一沟槽和封装衬底面板的下方部分对封装衬底面板的一部分进行单一化。在其它示例性实施例中，通过填充的一个或多个沟槽中的第一沟槽和封装衬底面板的下方部分对封装衬底面板的一部分进行单一化包括：切割穿过填充的沟槽和封装衬底面板的下方部分，该切割具有切割宽度，其中切割宽度小于填充的多个沟槽中的第一沟槽的宽度。在其它示例性实施例中，提供封装衬底面板包括提供封装芯，该封装芯上形成有至少一个构建层。根据本公开的实施例，该封装衬底面板包括面板顶表面上的电迹线，并且其中固化模制化合物包括从电迹线的表面的至少一部分去除模制件。
根据本公开的示例性实施例，填充的多个沟槽中的第一沟槽设置于第一电子部件和第二电子部件之间，并且其中封装衬底面板的部分包括第一电子部件，而不包括第二电子部件。在其它示例性实施例中，封装衬底面板的部分包括第三电子部件，并且其中在第一电子部件和第三电子部件之间设置有多个填充电气沟槽中的第二沟槽。根据示例性实施例，将第一电子部件附接到面板顶表面包括将第一电子部件的铜柱接合到面板顶表面上的一个或多个焊盘上。在其它示例性实施例中，该方法还包括使用如下方法中的至少一种去除一个或多个沟槽的底部的残余物：(i)湿法蚀刻，(ii)干法蚀刻，或(iii)激光烧蚀。在其它示例性实施例中，该方法还包括利用环氧树脂形成顶部导电层。根据一些示例性实施例，在面板顶表面上沉积模制化合物包括沉积一定量的模制化合物以填充一个或多个沟槽并形成顶部导电层。

Claims (20)

1.一种微电子封装，包括：
具有顶部衬底表面和衬底外周边的衬底，所述顶部衬底表面具有安装于其上的电子部件，并且所述顶部衬底表面具有导电迹线，所述导电迹线沿所述衬底外周边的至少部分设置；
在所述顶部衬底表面之上提供的模制化合物，所述模制化合物具有底部模制表面、顶部模制表面以及大体上覆盖所述衬底外周边的模制侧壁；以及
提供在所述模制侧壁上并覆盖所述顶部模制表面的环氧树脂，其中，所述环氧树脂包括导电颗粒，并且其中，覆盖所述顶部模制表面的所述环氧树脂和在所述模制侧壁上的环氧树脂电耦合。
2.根据权利要求1所述的微电子封装，其中，所述环氧树脂还电耦合到所述导电迹线。
3.根据权利要求2所述的微电子封装，其中，所述导电迹线电连接到如下中的至少一者：(i)地，(ii)直流(DC)电压，或(iii)所述微电子封装的电源线电压。
4.根据权利要求1所述的微电子封装，其中，所述衬底包括芯层和具有金属线的至少一个构建层，其中，所述金属线至少包括所述导电迹线。
5.根据权利要求1所述的微电子封装，其中，所述模制化合物包括热固性环氧树脂化合物。
6.根据权利要求1所述的微电子封装，其中，所述模制件包括导电结构，所述导电结构从所述底部模制表面延伸到所述顶部模制表面并且电连接到被提供为覆盖所述顶部模制表面的环氧树脂。
7.根据权利要求1所述的微电子封装，其中，所述环氧树脂包括如下中的至少一种：(i)固化的导电油墨，(ii)固化的导电膏，或(iii)银纳米颗粒。
8.根据权利要求1所述的微电子封装，其中，所述电子部件是第一电子部件，并且其中，所述微电子封装还包括：
第二电子部件；以及
导电结构，所述导电结构电连接到所述导电迹线和提供在所述顶部模制表面上的所述环氧树脂，所述导电结构设置于所述第一电子部件和所述第二电子部件之间，在形成于所述模制件中的从所述底部模制表面延伸到所述顶部模制表面的沟槽中。
9.根据权利要求1-8中任一项所述的微电子封装，还包括设置于所述衬底的底部衬底表面上的多个封装到板电连接。
10.一种方法，包括：
提供具有面板顶表面的封装衬底面板；
将第一电子部件和第二电子部件电气附接到所述面板顶表面；
在所述面板顶表面上沉积模制化合物，其中，所述模制化合物包封所述第一电子部件和所述第二电子部件；
向所述模制化合物的顶表面施加版框以固化所述模制化合物，以形成模制件，所述版框具有平坦部分和从所述平坦部分沿所述平坦部分的大体上法线方向延伸的一个或多个突出部，所述模制件具有顶部模制表面和接触所述面板顶表面的底部模制表面，其中，所述模制件包括对应于所述版框的所述突出部的一个或多个沟槽；以及
利用环氧树脂填充所述一个或多个沟槽，其中，所述环氧树脂包括导电颗粒。
11.根据权利要求10所述的方法，还包括通过填充的所述一个或多个沟槽中的第一沟槽和所述封装衬底面板的下方部分对所述封装衬底面板的部分进行单一化。
12.根据权利要求11所述的方法，其中，通过填充的所述一个或多个沟槽中的所述第一沟槽和所述封装衬底面板的所述下方部分对所述封装衬底面板的所述部分进行单一化包括：
切割穿过填充的所述沟槽和所述封装衬底面板的所述下方部分，所述切割具有切割宽度，其中，所述切割宽度小于填充的所述多个沟槽中的所述第一沟槽的宽度。
13.根据权利要求10所述的方法，其中，提供所述封装衬底面板包括提供封装芯，在所述封装芯上形成有至少一个构建层。
14.根据权利要求10-13中任一项所述的方法，其中，所述封装衬底面板包括所述面板顶表面上的电迹线，并且其中，固化所述模制化合物包括从所述电迹线的表面的至少部分去除模制件。
15.根据权利要求10所述的方法，其中，填充的所述多个沟槽中的第一沟槽设置于所述第一电子部件和所述第二电子部件之间，并且其中，所述封装衬底面板的所述部分包括所述第一电子部件，但不包括所述第二电子部件。
16.根据权利要求15所述的方法，其中，所述封装衬底面板的所述部分包括第三电子部件，并且其中，在所述第一电子部件和所述第三电子部件之间设置有填充的所述多个电气沟槽中的第二沟槽。
17.根据权利要求10所述的方法，其中，将所述第一电子部件附接到所述面板顶表面包括将所述第一电子部件的铜柱接合到所述面板顶表面上的一个或多个焊盘。
18.根据权利要求10所述的方法，还包括使用如下方法中的至少一种去除所述一个或多个沟槽的底部处的残余物：(i)湿法蚀刻，(ii)干法蚀刻，或(iii)激光烧蚀。
19.根据权利要求10所述的方法，还包括利用所述环氧树脂形成顶部导电层。
20.根据权利要求19所述的方法，其中，在所述面板顶表面上沉积所述模制化合物包括沉积一定量的所述模制化合物以填充所述一个或多个沟槽并形成所述顶部导电层。
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