TWI736072B - 封裝結構與其形成方法 - Google Patents

封裝結構與其形成方法 Download PDF

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TWI736072B
TWI736072B TW108146863A TW108146863A TWI736072B TW I736072 B TWI736072 B TW I736072B TW 108146863 A TW108146863 A TW 108146863A TW 108146863 A TW108146863 A TW 108146863A TW I736072 B TWI736072 B TW I736072B
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Taiwan
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solder
substrate
area
underfill material
forming
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TW108146863A
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TW202038344A (zh
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黃冠育
黃松輝
賴瑞協
侯上勇
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台灣積體電路製造股份有限公司
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Abstract

提供一種封裝結構與其形成方法。其方法包括在基材上形成一個或多個銲料元件。一個或多個銲料元件圍繞基材的區域。其方法也包括在基材的區域上設置半導體晶粒結構。其方法更包括在基材的區域上分配含有聚合物的液體。一個或多個銲料元件限制含有聚合物的液體大抵在區域中。此外，其方法包括固化含有聚合物的液體以形成底部填充材料。

Description

封裝結構與其形成方法
本發明實施例係有關於一種半導體結構與其形成方法，且特別關於一種封裝結構與其形成方法。
半導體積體電路產業經歷快速成長。半導體製造製程持續的進步使半導體裝置具有更精細的部件及/或更高的整合度。功能密度(即每晶片面積的互連裝置數量)已增加，而部件尺寸(即使用製造製程創建的最小元件)已減小。此種微縮化製程提供增加生產效率和降低相關成本的益處。
晶片封裝不只提供半導體裝置不受環境汙染的保護，也為封裝在其中的半導體裝置提供互連介面。已經發展出利用更少面積或更低高度的更小的封裝結構來封裝半導體裝置。
新的封裝技術已經被開發以進一步提高半導體晶粒的密度和功能。這些相對較新的半導體晶粒封裝技術面臨製造的挑戰。
一種形成封裝結構的方法，包括在基材上形成一個或多個銲料元 件，其中一個或多個銲料元件圍繞基材的區域；在基材的區域上設置半導體晶粒結構；在基材的區域上分配含有聚合物的液體，其中一個或多個銲料元件限制含有聚合物的液體大抵在區域中；及固化含有聚合物的液體以形成底部填充材料。
一種形成封裝結構的方法，包括在基材上形成多個銲料元件，其中多個銲料元件一同圍繞基材的區域；經由多個接合結構，在基材的區域上接合半導體晶粒結構；回銲多個銲料元件及多個接合結構；導入底部填充材料至被多個銲料元件圍繞的區域上，其中多個銲料元件大抵防止底部填充材料流至區域外；及固化底部填充材料。
一種封裝結構，包括半導體晶粒結構在基材上；多個接合結構在半導體晶粒與基材之間；多個銲料元件在基材上，其中多個銲料元件一同圍繞半導體晶粒結構；及底部填充材料，圍繞多個接合結構，其中底部填充材料大抵被限制在被多個銲料元件圍繞的區域中。
20/20’:半導體晶粒結構
30:表面安裝裝置
100,200,300:基材
102:導電部件
104,106,108:導電元件
110:模板
112,114,112’:開口
116,118,416:銲料元件(絕緣元件)
117:漿料材料
119:刮刀
120,206,304:底部填充材料
122:黏著層
124:抗翹曲元件
204,212,302:接合結構
208:保護層
210:基材通孔
214:導電柱
216:銲料凸塊
116’,116”,118’,916’:回銲的銲料元件
120’,120”:固化的底部填充材料
202A,202B,202C:半導體晶粒
D:距離
F:外力
G:間隙
H1,H2:高度
P1:內部部分
P2:外部部分
S:支撐部分
以下將配合所附圖示詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1A-1I圖係根據一些實施例，繪示形成封裝結構製程的多個階段的剖面圖。
第2A-2C圖係根據一些實施例，繪示形成封裝結構製程的多個階段的俯視圖。
第3A-3C圖係根據一些實施例，繪示形成封裝結構製程的多個階段的俯視圖。
第4A-4C圖係根據一些實施例，繪示形成封裝結構製程的多個階段的俯視圖。
第5圖係根據一些實施例，繪示封裝結構的剖面圖。
第6圖係根據一些實施例，繪示封裝結構的俯視圖。
第7圖係根據一些實施例，繪示封裝結構的剖面圖。
第8圖係根據一些實施例，繪示封裝結構的俯視圖。
第9圖係根據一些實施例，繪示封裝結構的俯視圖。
第10圖係根據一些實施例，繪示封裝結構的俯視圖。
以下內容提供了很多不同的實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件之上，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的，其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
再者，此處可能使用空間上的相關用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用 語可用於此，以便描述如圖所示之一元件或部件與其他元件或部件之間的關係。此空間上的相關用語除了包含圖示繪示的方位外，也包含使用或操作中的裝置的不同方位。當裝置被轉至其他方位時(旋轉90度或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
本領域技術人員將理解說明書中的用語「大抵上(substantially)」，例如「大抵平坦」或「大抵共面」等。在一些實施例中，形容詞大抵可能被去除。在適用的情況下，用語「大抵」也可以包括具有「全部」、「完全」、「全部」等的實施例。在適用的情況下，用語「大抵」也可涉及90%或更高，例如95%或更高，詳細而言，99%或更高，包括100%。此外，例如「大抵平行」或「大抵垂直」之類的用語應解釋為不排除與特定配置的微小偏差，例如可能包括10°的偏差。用語「大抵」不排除「完全」，例如「大抵不含」Y的組合物可以完全不含Y。
用語例如「約」結合特定距離或尺寸應被解釋為不排除與特定距離或尺寸的微小偏差，例如可能包括10%的偏差。與數值x的相關用語「約」可表示x±5或10%。
以下敘述一些本發明實施例，在這些實施例中所述的多個階段之前、期間以及/或之後，可提供額外的步驟。一些所述階段在不同實施例中可被替換或刪去。半導體裝置結構可增加額外部件。一些所述部件在不同實施例中可被替換或刪去。儘管所討論的一些實施例以特定順序的步驟執行，這些步驟仍可以另一合乎邏輯的順序執行。
本揭露實施例有關於3D封裝或3D-IC裝置。也可包括其他部件和製程。例如，可包括測試結構以幫助3D封裝或3D-IC裝置進行驗證測試。測試結 構可能包括，例如，形成在重分佈層中或基材上的測試墊(testing pad)，其允許3D封裝或3D-IC的測試、探針及/或探針卡的使用等等。驗證測試可以執行在中間結構以及最終結構。此外，此處揭露的結構和方法可以結合併入已知良好晶粒的中間驗證的測試方法使用，以增加產率並降低成本。
第1A-1I圖係根據一些實施例，繪示形成封裝結構製程的多個階段的剖面圖。如第1A圖所示，接收或提供基材100。基材100可包括或由聚合物材料、半導體材料、陶瓷材料、一種或多種其他合適的材料或其組合形成。在一些實施例中，基材100包括含有聚合物的基板，含有聚合物的基板具有在其中及/或在其上形成的多個導電部件102。導電部件102可包括導線、導電導孔、導電墊、一個或多個其他合適的導電元件或其組合。導電部件102可用以形成設置在基材100前側上的半導體晶粒結構，與設置在基材100後側上的其他裝置元件之間的電性連接。
在一些實施例中，如第1A圖所示，導電元件104、106和108形成在基材100的前側。在一些實施例中，導電元件104用作導電墊。導電元件104可以用於接收要設置在基材100上的半導體晶粒結構的接合結構。在一些實施例中，導電元件108用於接收例如表面安裝裝置的裝置元件。
在一些實施例中，導電元件106彼此分離，並且一起形成圍繞導電元件104的環狀結構。在一些其他實施例中，導電元件106是圍繞導電元件104的單環結構。
根據一些實施例，如第1B圖所示，模板110設置在基材100上方。在一些實施例中，模板110包括一個或多個開口112。開口112完全穿透模板110。如第1B圖所示，開口112部分地暴露基材100。在一些實施例中，開口112暴露形 成在基材100前側的導電元件106。在一些實施例中，模板還包括暴露導電元件108的開口114。
模板110可包括或由鋼、鋁、銅、矽、金、一種或多種其他合適的材料或其組合形成。開口112和114可以使用機械鑽孔製程、能量束鑽孔製程、微影和蝕刻製程、一種或多種其他適用製程或其組合形成。
根據一些實施例，如第1B圖所示，在模板110上提供漿料材料117。在一些實施例中，提供刮刀119，以在模板上延伸漿料材料117。因此，一部分漿料材料117可以被引入到模板110的開口112和114中。
在一些實施例中，漿料材料117是導電漿料。在一些實施例中，漿料材料117是銲料漿料。銲料漿料可以包括銲料粉末和助熔劑。在一些實施例中，銲料漿料是含錫的銲料漿料。含錫的銲料漿料可以更包括銅、銀、金、鋁、鉛、一種或多種其他合適的材料或其組合。在一些實施例中，含錫的銲料漿料是不含鉛的。
根據一些實施例，如第1C圖所示，在擠壓刮刀119之後，一部分的漿料材料117藉由開口112和114設置在基材100上(或擠壓在其上)以形成銲料元件116和118。在一些實施例中，銲料元件116和118同時形成。然而，可以對本揭露的實施例做出許多變化及/或修改。在一些其他實施例中，銲料元件116和118是分開形成的。在一些實施例中，銲料元件116與導電元件106直接接觸。在一些實施例中，銲料元件118與導電元件108直接接觸。
第2A-2C圖係根據一些實施例，繪示形成封裝結構製程的多個階段的俯視圖。在一些實施例中，第2A圖示出第1C圖所示結構的一部分的俯視圖。
根據一些實施例，如第2A圖所示，銲料元件116形成在模板110 的開口112之中。銲料元件116一同圍繞半導體晶粒結構將被放置的區域。
根據一些實施例，如第2A圖所示，模板110具有被開口112圍繞的內部P1和圍繞內部P1的外部P2。在一些實施例中，模板110包括連接內部P1和外部P2的支撐部分S。由於支撐部分S的支撐，內部部分P1和外部部分P2整體連接為單一件，使其製程更容易執行。
之後，根據一些實施例，如第1D圖所示，移除模板110。銲料元件116和118分別保留在導電元件106和108上。
根據一些實施例，如第1E圖所示，半導體晶粒結構20設置在基材100被銲料元件116圍繞的區域上。在一些實施例中，半導體晶粒結構20包括單一半導體晶粒。在一些實施例中，半導體晶粒結構20是具有單一半導體晶粒的晶粒封裝。在一些實施例中，半導體晶粒結構20包括多個半導體晶粒。在一些實施例中，半導體晶粒結構20是具有多個半導體晶粒的晶粒封裝。在一些實施例中，半導體晶粒結構20包括多個半導體晶粒的堆疊。在一些實施例中，一些或全部半導體晶粒橫向地設置在基材上。
根據一些實施例，如第1E圖所示，半導體模具結構20包括設置在基材200上的半導體晶粒202A、202B和202C。基材200可以包括或由半導體材料、陶瓷材料、一種或多種其他合適的材料或其組合形成。在一些實施例中，基材200為半導體晶圓，例如矽晶圓。在一些其他實施例中，基材200為玻璃晶圓。在一些其他實施例中，基材200為含有聚合物並有相似於矽晶圓輪廓的基材。
在一些實施例中，如第1E圖所示，半導體晶粒202A、202B和202C藉由接合結構204接合到基材200上。接合結構204可以包括導電柱、銲料元件、一種或多種其他合適的元件或其組合。在一些實施例中，每個銲料元件與兩個 導電柱堆疊。例如，每個銲料元件位於兩個導電柱之間，如第1E圖所示。
在一些實施例中，導電柱為金屬柱。金屬柱可以包括或由銅、鋁、鈦、鈷、金、鉑、一種或多種其他合適的材料或其組合形成。在一些實施例中，銲料元件為含錫的銲料元件。含錫的銲料元件可以更包括銅、銀、金、鋁、鉛、一種或多種其他合適的材料或其組合。在一些實施例中，含錫的銲料元件是不含鉛的。接合結構204的形成可涉及一種或多種回銲製程及/或一種或多種電鍍製程。
在一些實施例中，多個導電部件形成在基板200內及/或上。這些導電部件可以包括導線、導電墊、導電導孔、一個或多個其他合適的導電元件或其組合。在一些實施例中，在基材200中形成多個基材通孔(through substrate via)210。基材通孔210可以在設置在基材200相反表面上的元件之間形成電性連接。
在一些實施例中，如第1E圖所示，底部填充材料206形成在基材200上以圍繞接合結構204。底部填充材料206可以用於保護接合結構204。底部填充材料206可以包括或由一種或多種聚合物材料形成。底部填充材料206可以包括環氧基樹脂。在一些實施例中，底部填充材料206還包括分散在環氧基樹脂中的填料(filler)。填料可以包括纖維(例如二氧化矽纖維)、顆粒(例如二氧化矽顆粒)、一種或多種其他合適的元素或其組合。
在一些實施例中，底部填充材料206的形成涉及注入製程、分配製程、膜疊層(film lamination)製程、塗佈(application)製程、一個或多個其他可應用製程或其組合。在一些實施例中，之後使用熱固化製程來完成底部填充材料206的形成。
根據一些實施例，如第1E圖所示，形成保護層208以圍繞半導體晶粒202A、202B和202C。保護層208也圍繞底部填充材料206和接合結構204。在一些實施例中，保護層208與半導體晶粒202A、202B和202C直接接觸。
在一些實施例中，保護層208包括或由模塑化合物(molding compound)材料形成。模塑化合物材料可包括聚合物材料，例如其中分散有填料的環氧基樹脂。在一些實施例中，將液態模塑化合物材料引入或注入到基材200上。之後可以使用熱製程來固化液態模塑化合物材料，並將其轉變成保護層208。
根據一些實施例，如第1E圖所示，半導體晶粒結構20藉由接合結構212接合到導電元件104上。接合結構212也可以在基材100中的導電部件102與半導體晶粒結構20中的半導體晶粒202A、202B及/或202C之間形成電性連接。在一些實施例中，如第1E圖所示，接合結構212包括導電柱214和銲料凸塊216。
在一些實施例中，導電柱214是金屬柱。金屬柱可以包括或由銅、鋁、鈦、鈷、金、鉑、一種或多種其他合適的材料或其組合形成。在一些實施例中，銲料凸塊216為含錫的銲料凸塊。含錫的銲料凸塊可更包括銅、銀、金、鋁、鉛、一種或多種其他合適的材料或其組合。在一些實施例中，銲料凸塊216包含錫並且不含鉛。接合結構212的形成可涉及一種或多種回銲製程及/或一種或多種電鍍製程。
根據一些實施例，如第1E圖所示，表面安裝裝置(surface mounted device)30藉由銲料元件118接合到基材100上。在一些實施例中，如第1E圖所示，表面安裝裝置30位於被銲料元件116圍繞的區域外。表面安裝裝置30可以包括一個或多個被動元件，例如電阻、電容、電感、一個或多個其他合適的元件或其 組合。在一些其他實施例中，表面安裝裝置30包括記憶體裝置。
根據一些實施例，如第1F圖所示，回銲銲料元件116和118以形成回銲的銲料元件116’和118’。在一些實施例中，在形成回銲的銲料元件116’和118’的回銲過程中，接合結構212的銲料凸塊216也同時被回銲。在回銲製程之後，增強了銲料凸塊216與導電元件104之間的接合。
在一些實施例中，第2B圖顯示第1F圖所示結構的一部分的俯視圖。在一些實施例中，如第1F圖及/或第2B圖所示，回銲的銲料元件116’和118’比銲料元件116和118具有更多的圓形輪廓。在一些實施例中，如第2B圖所示，其中一個回銲的銲料元件116’沿著一個方向延伸，其方向大抵平行於半導體晶粒結構20的側面的延伸方向。
然而，本揭露的實施例不限於此。可以對本揭露的實施例做出許多變化及/或修改。在一些其他實施例中，不回銲銲料元件116和118。
在一些實施例中，如第2B圖所示，回銲的銲料元件116’一同圍繞半導體晶粒結構20所處的區域。在一些實施例中，這些回銲的銲料元件116’彼此分離。在一些實施例中，如第2B圖所示，附近的兩個回銲的銲料元件116’彼此隔開距離D。距離D可以根據需要改變。例如，藉由設計第2A圖中的模板110的支撐部分S的尺寸及/或輪廓，在第2B圖中的距離D可以改變。
往前參考第1F圖，其中一個回銲的銲料元件116’具有高度H1，並且半導體晶粒結構20具有高度H2。在一些實施例中，高度H2大於高度H1。因為模板110的幫助，允許回銲的銲料元件116’形成並具有更大的高度。高度H1可以在約80μm至約100μm的範圍內。高度H1與高度H2的高度比例(H1/H2)可以在約1/5至約3/4的範圍內。
根據一些實施例，如第1G圖所示，底部填充材料120被分配及/或引入到被回銲的銲料元件116’圍繞的區域上。在一些實施例中，底部填充材料120為含有聚合物的液體。底部填充材料120可以包括或由環氧基樹脂形成。在一些實施例中，底部填充材料120更包括分散在環氧基樹脂中的填料。填料可以包括纖維(例如二氧化矽纖維)、顆粒(例如二氧化矽顆粒)、一種或多種其他合適的元素或其組合。
在一些實施例中，保護層208的填料的重量百分比大於底部填充材料120的填料的重量百分比。在一些實施例中，保護層208的填料的平均尺寸大於底部填充材料120的填料的平均尺寸。
回銲的銲料元件116’可用於將底部填充材料120限制在大抵由回銲的銲料元件116’圍繞的區域內。回銲的銲料元件116’可大抵防止底部填充材料120流出被回銲的銲料元件116’圍繞的區域外。由於回銲的銲料元件116’的限制，防止底部填充材料120觸及表面安裝裝置30。因此，確保表面安裝裝置30的品質和可靠性。由於回銲的銲料元件116’，底部填充材料120被限制在預定的區域中，並防止佔據基材100過多的面積。因此，允許更多的裝置元件被整合到基材100上。
根據一些實施例，如第1H圖所示，底部填充材料120被固化以形成固化的底部填充材料120’。可使用熱操作、光照射操作(例如，UV光照射和/或IR光照射)、一種或多種其他適用的操作或其組合來執行固化製程。
在一些實施例中，第2C圖顯示第1H圖中部份結構的俯視圖。根據一些實施例，如第2C圖所示，固化的底部填充材料120’大抵被限制及/或阻擋在被回銲的銲料元件116’圍繞的區域內。在一些實施例中，如第2C圖所示，固化 的底部填充材料120’與回銲的銲料元件116’直接接觸。
之後，根據一些實施例，如第1H圖所示，在固化底部填充材料120以形成固化的底部填充材料120’之後，將抗翹曲(anti-warpage)元件124設置在基材100上。在一些實施例中，抗翹曲元件124是圍繞回銲的銲料元件116’和表面安裝裝置30的抗翹曲環。
在用於回銲銲料元件與固化底部填充材料120的熱操作之後，由於不同材料的不同熱膨脹係數，基材100可能翹曲。抗翹曲元件124可以幫助減小基材100的翹曲度(degree of warpage)，其有助於後續製程。
在一些實施例中，如第1H圖所示，抗翹曲元件124附接到基材100上。在一些實施例中，使用黏著層122附接抗翹曲元件124。在一些實施例中，在附接抗翹曲元件124的期間，外力F被施加在抗翹曲元件124。因此，可以減小基材100的翹曲度。
根據一些實施例，如第1I圖所示，第1H圖中所示的結構藉由接合結構302被接合到基材300上。在一些實施例中，基材300為印刷電路板。由於抗翹曲元件124減小基材100的翹曲度，第1H圖所示的結構與基材300之間可以更容易接合。
在一些實施例中，接合結構302包括銲料凸塊、金屬柱、一個或多個其他合適的導電元件或其組合。在一些實施例中，底部填充材料304形成在基材300和100之間，如第1I圖所示。底部填充材料304可用於保護結合結構302。
然而，本揭露的實施例不限於此。可以對本揭露的實施例做出許多變化及/或修改。在一些其他實施例中，漿料材料117為絕緣材料。在這些情況下，圍繞放置半導體晶粒結構20區域的元件為絕緣元件。在這些情況下，參考 數字“116”用於表示絕緣元件。絕緣元件116也可以用於防止底部填充材料120流出被絕緣元件116圍繞的區域之外。由於底部填充材料120被限制及/或約束在區域內，可以獲得基材100較大的可用區域。因此，允許將更多的裝置元件整合到基材100上。
可以對本揭露的實施例做出許多變化及/或修改。根據一些實施例，第3A-3C圖為的形成封裝結構的多個階段的俯視圖。
在一些實施例中，如第3A圖所示，模板110的開口112被設計成彼此更靠近。模板110的支撐部分S被設計成較小。因此，銲料元件116之間的距離相應地變小。
根據一些實施例，如第3B圖所示，類似於第2B圖所示的實施例，銲料元件116被回銲以形成回銲的銲料元件116’。在回銲製程之後，銲料元件116可能變圓且較寬。在一些實施例中，最初彼此分離的兩個或更多個銲料元件116連接在一起。在一些實施例中，所有銲料元件116連接在一起以形成回銲的銲料元件116’，如第3B圖所示。在這些情況下，回銲的銲料元件116’連續地圍繞設置半導體裝置結構20的區域。
根據一些實施例，如第3C圖所示，類似於第2C圖所示的實施例，固化的底部填充材料120’形成在被回銲的銲料元件116’圍繞的區域內。在一些實施例中，如第3C圖所示，由於回銲的銲料元件116’的限制，固化的底部填充材料120’完全位於被回銲的銲料元件116’圍繞的區域內。
可以對本揭露的實施例做出許多變化及/或修改。根據一些實施例，第4A-4C圖為形成封裝結構製程的多個階段的俯視圖。
如第4A圖所示，提供類似第2A圖所示的結構。在一些實施例中， 模板110更包括開口112’，如第4A圖所示。之後，執行類似於第1B-1C圖所示的製程。因此，引入到開口112中的漿料材料117的第一部分形成銲料元件116。根據一些實施例，如第4A圖所示，引入到開口112’中的漿料材料117的第二部分形成銲料元件416。銲料元件116和416一同圍繞將要設置半導體晶粒結構的區域。
在一些實施例中，如第4A圖所示，其中一個銲料元件416延伸跨越兩個彼此相鄰的銲料元件116之間的間隙G。在一些實施例中，如第4A圖所示，其中一個銲料元件416延伸跨越兩個彼此相鄰的銲料元件116的部分。
之後，類似於第2B圖所示的實施例，根據一些實施例，如第4B圖所示，設置半導體晶粒結構20。之後，執行回銲製程。因此，根據一些實施例，如第4B圖所示，形成回銲的銲料元件116’和416’。
之後，類似於第2C圖所示的實施例，根據一些實施例，如第4C圖所示，形成固化的底部填充材料120’。根據一些實施例，如第4C圖所示，固化的底部填充材料120’大抵被限制及/或阻擋在被回銲的銲料元件116’和416’圍繞的區域內。回銲的銲料元件416’阻擋了附近銲料元件116’之間間隙，可以幫助進一步約束底部填充材料。
在一些實施例中，如第4C圖所示，固化的底部填充材料120’與回銲的銲料元件116’直接接觸。在一些實施例中，如第4C圖所示，固化的底部填充材料120’與其中一個回銲的銲料元件416’直接接觸。在一些實施例中，如第4C圖所示，其中一個(或一些)回銲的銲料元件416’與固化的底部填充材料120’分離，而不與固化的底部填充材料120’直接接觸。
可以對本揭露的實施例做出許多變化及/或修改。在一些其他實施例中，每個回銲的銲料元件416’與固化的底部填充材料120’直接接觸。
在一些實施例中，回銲的銲料元件116’形成在將半導體晶粒結構20設置在基材100上之前。然而，本揭露的實施例不限於此。可以對本揭露的實施例做出許多變化及/或修改。在一些其他實施例中，回銲的銲料元件116’形成在將半導體晶粒結構20設置在基材100上之後。
可以對本揭露的實施例做出許多變化及/或修改。在一些實施例中，兩個(或更多個)半導體晶粒結構被設置在基材100上。可以形成兩個(或更多個)分開的底部填充材料以分別部分地保護兩個(或更多個)半導體晶粒結構。在一些實施例中，使用一個或多個回銲的銲料元件，來防止兩個或多個底部填充材料連接在一起。因此，每個底部填充材料被限制在圍繞的區域中。因此，控制每個底部填充材料的面積。具有受控面積的底部填充材料產生的應力顯著降低。因此，提高封裝結構的可靠性。
第5圖係根據一些實施例，繪示封裝結構的剖面圖。第6圖係根據一些實施例，繪示封裝結構的俯視圖。在一些實施例中，類似於半導體晶粒結構20，半導體晶粒結構20’也被設置在基材100上。在一些實施例中，類似於固化的底部填充材料120’，形成固化的底部填充材料120”以圍繞並保護半導體晶粒結構20’下的接合結構212。在一些實施例中，其中一個回銲的銲料元件116’用於限制固化的底部填充材料120’和120”的面積。防止固化的底部填充材料120’和120”連接在一起。控制每個固化的底部填充材料120’和120”的面積。由每個底部填充材料120’和120”產生的應力顯著減小。因此，提高封裝結構的可靠性。
第7圖係根據一些實施例，繪示封裝結構的剖面圖。第8圖係根據一些實施例，繪示封裝結構的俯視圖。在一些實施例中，形成回銲的銲料元件116’和116”以防止固化的底部填充材料120’和120”連接在一起。控制每個固化 的底部填充材料120’和120”的面積。由每個底部填充材料120’和120”產生的應力顯著減小。因此，提高封裝結構的可靠性。
第9圖係根據一些實施例，繪示封裝結構的俯視圖。在一些實施例中，在回銲的銲料元件116’和116”之間形成回銲的銲料元件916’。即使一些固化的底部填充材料120’或120”延伸跨過回銲的銲料元件116’或116”，回銲的銲料元件916’也可以進一步防止固化的底部填充材料120’和120”連接在一起。控制每個固化的底部填充材料120’和120”的面積。由每個底部填充材料120’和120”產生的應力顯著減小。因此，提高封裝結構的可靠性。
第10圖係根據一些實施例，繪示封裝結構的俯視圖。在一些實施例中，形成與第8圖所示結構相似的結構。在一些實施例中，進一步形成回銲的銲料元件116’以防止固化的底部填充材料120’和120”連接在一起。控制每個固化的底部填充材料120’和120”的面積。由每個底部填充材料120’和120”產生的應力顯著減小。因此，提高封裝結構的可靠性。
本揭露的實施例在基材上形成一個或多個元件(例如，銲料元件)以圍繞設計要設置半導體晶粒結構的區域。在其區域內形成底部填充材料以保護半導體晶粒結構與基材之間的接合結構。由於元件的限制，防止底部填充材料佔據基材過多的面積。底部填充材料也遠離位於被元件圍繞的區域外的其他裝置元件(例如表面安裝的裝置)。也可以確保裝置元件的品質和可靠性。允許將更多的裝置元件整合到基材上。封裝結構的性能和可靠性顯著提升。
根據一些實施例，提供一種形成封裝結構的方法。其方法包括在基材上形成一個或多個銲料元件。一個或多個銲料元件圍繞基材的區域。其方法也包括在基材的區域上設置半導體晶粒結構。其方法更包括在基材的區域上 分配含有聚合物的液體。一個或多個銲料元件限制含有聚合物的液體大抵在區域中。此外，其方法包括固化含有聚合物的液體以形成底部填充材料。
根據一些實施例，提供一種形成封裝結構的方法。其方法包括在基材上形成多個銲料元件，多個銲料元件一同圍繞基材的區域。其方法也包括經由多個接合結構，在基材的區域上接合半導體晶粒結構，並回銲多個銲料元件及多個接合結構。其方法更包括導入底部填充材料至被多個銲料元件圍繞的區域上。多個銲料元件大抵防止底部填充材料流至區域外。此外，其方法包括固化底部填充材料。
根據一些實施例，提供一種封裝結構。其封裝結構包括半導體晶粒結構在基材上。其封裝結構也包括多個接合結構在半導體晶粒與基材之間。其封裝結構更包括多個銲料元件在基材上，並且多個銲料元件一同圍繞半導體晶粒結構。此外，其封裝結構包括圍繞接合結構的底部填充材料。底部填充材料大抵被限制在被多個銲料元件圍繞的區域中。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
20:半導體晶粒結構
30:表面安裝裝置
100,200,300:基材
102:導電部件
104,106,108:導電元件
206,304:底部填充材料
122:黏著層
124:抗翹曲元件
204,212,302:接合結構
208:保護層
210:基材通孔
214:導電柱
216:銲料凸塊
116’,118’:回銲的銲料元件
120’:固化的底部填充材料
202A,202B,202C:半導體晶粒

Claims (8)

  1. 一種形成封裝結構的方法，包括：在一基材上形成至少一銲料元件以及一第二銲料元件，其中該至少一銲料元件圍繞該基材的一區域，且該第二銲料元件被置於該區域的外面；在該第二銲料元件上設置一表面安裝裝置(surface mounted device)；在該基材的該區域上設置一半導體晶粒結構；同時回銲該至少一銲料元件以及該第二銲料元件；在該基材的該區域上分配一含有聚合物的液體，其中該至少一銲料元件限制該含有聚合物的液體大抵在該區域中；及固化(cure)該含有聚合物的液體以形成一底部填充材料。
  2. 如申請專利範圍第1項所述之形成封裝結構的方法，更包括：在該基材上設置一模板(stencil)，其中該模板具有至少一開口，該開口部分地暴露該基材；在該模板上塗佈一銲料漿料，其中一部分的該銲料漿料經由該至少一開口設置在該基材上，以形成該至少一銲料元件；及去除該模板。
  3. 如申請專利範圍第1項或第2項所述之形成封裝結構的方法，更包括在回銲該至少一銲料元件以及該第二銲料元件之後，在該基材上設置一抗翹曲環(anti-warpage ring)。
  4. 如申請專利範圍第1項或第2項所述之形成封裝結構的方法，更包括：在回銲該至少一銲料元件以及該第二銲料元件後，附接一抗翹曲環至該基材 上；及對該抗翹曲環施加一外部力量以減少該基材的翹曲度(degree of warpage)。
  5. 一種形成封裝結構的方法，包括：在一基材上形成複數個銲料元件，其中該些銲料元件一同圍繞該基材的一區域；經由多個接合結構，在該基材的該區域上接合一半導體晶粒結構；回銲該些銲料元件及該些接合結構；在回銲該些銲料元件及該些接合結構之後，在該基材上設置一抗翹曲環；導入一底部填充材料至被該些銲料元件圍繞的該區域上，其中該些銲料元件大抵防止該底部填充材料流至該區域外；及固化該底部填充材料。
  6. 如申請專利範圍第5項所述之形成封裝結構的方法，更包括形成一第二銲料元件，其中該第二銲料元件與該些銲料元件一同圍繞該區域，並且該第二銲料元件延伸跨越兩個該些銲料元件之間的一間隙(gap)。
  7. 如申請專利範圍第5項或第6項所述之形成封裝結構的方法，其中在回銲該些銲料元件與該些接合結構之後，全部的該些銲料元件連接在一起，以連續地圍繞該區域。
  8. 一種封裝結構，包括：一第一半導體晶粒結構以及一第二半導體晶粒結構，在一基材上；複數個第一接合結構，在該第一半導體晶粒與該基材之間；複數個第二接合結構，在該第二半導體晶粒與該基材之間；複數個銲料元件，在該基材上，其中該些銲料元件一同圍繞該第一半導體晶 粒結構以形成一第一區域，且該些銲料元件一同圍繞該第二半導體晶粒結構以形成一第二區域；一第一底部填充材料，圍繞該些第一接合結構，其中該第一底部填充材料大抵被限制該第一區域中；及一第二底部填充材料，圍繞該些第二接合結構，其中該第二底部填充材料大抵被限制在該第二區域中；其中該些銲料元件之其中一者同時接觸該第一底部填充材料及該第二底部填充材料。
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