CN202443963U - 半导体基板封装构造 - Google Patents

半导体基板封装构造 Download PDF

Info

Publication number
CN202443963U
CN202443963U CN2012200353368U CN201220035336U CN202443963U CN 202443963 U CN202443963 U CN 202443963U CN 2012200353368 U CN2012200353368 U CN 2012200353368U CN 201220035336 U CN201220035336 U CN 201220035336U CN 202443963 U CN202443963 U CN 202443963U
Authority
CN
China
Prior art keywords
groove
substrate
semiconductor substrate
packaging structure
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2012200353368U
Other languages
English (en)
Inventor
翁肇鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN2012200353368U priority Critical patent/CN202443963U/zh
Application granted granted Critical
Publication of CN202443963U publication Critical patent/CN202443963U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开一种半导体基板封装构造,其包含一基板、至少一芯片及一封装胶体。所述基板的上表面承载所述至少一芯片。所述基板的上表面另具有至少一凹槽,所述凹槽呈长条状、直角三边环绕状或直角四边环绕圈状。当所述封装胶体封装于所述基板的上表面时,部分的所述封装胶体填入所述至少一凹槽内,因此可增强所述封装胶体与所述基板的结合强度,使两者的黏合界面不易产生脱离,并可确保导线与焊垫的焊接结合可靠度或其它应力集中区域的结构完整性,从而提高所述半导体基板封装构造的封装品质。

Description

半导体基板封装构造
技术领域
本实用新型涉及一种半导体基板封装构造,特别是涉及一种增强封装胶体结合强度的半导体基板封装构造。
背景技术
现今,电子产品趋向多功能与小型化,其所搭配之电路组件相应往小型化的方向发展。现有的基板封装结构中例如:具有基板(substrate)的封装构造包含球形栅格数组封装构造(ball grid array,BGA)、针脚栅格数组封装构造(pin gridarray,PGA)、接点栅格数组封装构造(land grid array,LGA)或基板上芯片封装构造(board on chip,BOC)等。在上述封装构造中,所述基板的上表面承载有至少一芯片,并通过打线(wire bonding)或凸块(bumping)制程将芯片的数个接垫电性连接至所述基板的上表面的数个焊垫。同时,所述基板的下表面亦必需提供大量的焊垫,以焊接数个输出端,例如锡球。
请参照图1所示,图1揭示一种现有的半导体基板封装构造的侧剖视图。一现有半导体基板封装构造90包含:一基板91、一芯片92及一封装胶体93。所述基板91具有一上表面911及一下表面912,所述基板91的上表面911承载所述芯片92。所述基板91的上表面911另包含数个焊垫913,所述芯片92通过数条导线921电性连接至所述数个焊垫913。并且所述封装胶体93封装于所述基板91的上表面,并包覆所述芯片92、所述数个焊垫913及所述数条导线921。
另外,所述基板91的下表面912设有数个接垫(未标示),所述基板91上表面911的所述数个焊垫913通过基板内部线路电性连接至所述基板91下表面912的所述数个接垫,并且所述数个接垫上设有数个锡球94,以做为连接其它基板或装置的讯号输出端。
然而,上述的现有的半导体基板封装构造90中的所述基板91与所述封装胶体93的应力系数(例如热膨胀系数)存在一定程度的差异,当所述半导体基板封装构造90承受应力改变时(例如热胀冷缩现象),两者的黏合界面可能产生脱离,特别是可能导致所述封装胶体93内的所述数个焊垫913及所述数条导线921的焊接结合部份(或其它应力集中区域)受到应力拉扯而损坏,从而使得产品失效。
故,有必要提供一种半导体基板封装构造,以解决现有技术所存在的问题。
实用新型内容
有鉴于此,本实用新型提供一种半导体基板封装构造,以解决现有半导体基板封装构造因为基板与封装胶体受到应力变化脱离,从而造成内部组件损坏的技术问题。
本实用新型的主要目的在于提供一种半导体基板封装构造,其基板的上表面具有至少一凹槽,所述凹槽呈长条状、直角三边环绕状或直角四边环绕圈状。当封装胶体封装于所述基板的上表面时,部分的所述封装胶体填入所述至少一凹槽之内,因此可增强所述封装胶体与所述基板的结合强度,使两者的黏合界面不易产生脱离,并可确保导线与焊垫的焊接结合可靠度或其它应力集中区域的结构完整性,从而提高所述半导体基板封装构造的封装品质。
为达成本实用新型的前述目的,本实用新型提供一种半导体基板封装构造,所述半导体基板封装构造包含:
一基板,具有一上表面及一下表面;
至少一芯片,设于所述基板的上表面;及
一封装胶体,封装于所述基板的上表面,包覆所述至少一芯片;
其中所述基板的上表面具有至少一凹槽,部分所述封装胶体填入所述至少一凹槽之内。
为达成本实用新型的前述目的,本实用新型另提供一种半导体基板封装构造,所述半导体基板封装构造包含:
一基板,具有一上表面及一下表面;
至少一芯片,设于所述基板的上表面;
数个焊垫,设于所述基板的上表面,所述至少一芯片通过数条导线电性连接至所述数个焊垫;及
一封装胶体,封装于所述基板的上表面,包覆所述至少一芯片、所述数个焊垫及所述数条导线;
其中所述基板的上表面具有至少一凹槽,部分所述封装胶体填入所述至少一凹槽之内。
在本实用新型的一实施例中,所述至少一凹槽呈长条状,所述至少一凹槽邻接于所述数个焊垫。
在本实用新型的一实施例中,所述至少一凹槽设于所述至少一芯片与所述数个焊垫之间。
在本实用新型的一实施例中,所述至少一凹槽数量为两个并呈长条状,所述凹槽分别设于靠近所述数个焊垫对应的两侧边。
在本实用新型的一实施例中,所述至少一凹槽呈直角三边环绕状。
在本实用新型的一实施例中,所述至少一凹槽呈直角四边环绕圈状。
在本实用新型的一实施例中,所述至少一凹槽的一内底部的宽度大于所述凹槽的一开口部的宽度。
附图说明
图1是一种现有的半导体基板封装构造的侧剖视图。
图2A是本实用新型第一实施例的半导体基板封装构造封装前的局部俯视图。
图2B是图2A的半导体基板封装构造封装后的局部侧剖视图。
图3A是本实用新型第二实施例的半导体基板封装构造封装前的局部俯视图。
图3B是图3A的半导体基板封装构造封装后的局部侧剖视图。
图4是本实用新型第三实施例的半导体基板封装构造封装前的局部俯视图。
图5是本实用新型第四实施例的半导体基板封装构造封装前的局部俯视图。
图6是本实用新型第五实施例的半导体基板封装构造封装前的局部俯视图。
图7揭示本实用新型第六实施例的半导体基板封装构造封装后的局部侧剖视图。
图8揭示本实用新型第七实施例的半导体基板封装构造封装后的局部侧剖视图。
具体实施方式
为让本实用新型上述目的、特征及优点更明显易懂,下文特举本实用新型较佳实施例,并配合附图,作详细说明如下。再者,本实用新型所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本实用新型,而非用以限制本实用新型。
请参照图2A及2B所示,图2A揭示本实用新型第一实施例的半导体基板封装构造封装前的局部俯视图;及图2B揭示图2A的半导体基板封装构造封装后的局部侧剖视图,需要特别说明的是,为了方便显示出半导体基板封装构造的内部,图2A中选择呈现的是封装前不包含封装胶体的状态,图2B中选择呈现的是封装后包含封装胶体的状态。
如图2A及2B所示,本实用新型第一实施例的半导体基板封装构造100包含:一基板10、至少一芯片20及一封装胶体30。所述基板10具有一上表面11及一下表面12,所述基板10的上表面11承载所述至少一芯片20。所述基板10的上表面11另包含数个焊垫13,所述芯片20通过数条导线21电性连接至所述数个焊垫13。
另外,所述基板10的下表面12设有数个接垫(未标示),所述基板10上表面11的所述数个焊垫13通过基板内部线路电性连接至所述基板10下表面12的所述数个接垫,并且所述数个接垫上设有数个锡球40,以做为连接其它基板或装置的讯号输出端。
再者,如图2A所示,所述基板10的上表面11靠近所述数个焊垫13的外侧具有至少一凹槽50,所述凹槽50呈长条状。如图2B所示,所述封装胶体30封装于所述基板10的上表面后,其包覆所述芯片20、所述数个焊垫13及所述数条导线21。并且,部分的所述封装胶体30填入所述至少一凹槽50之内,因此可增强所述封装胶体30与所述基板10的结合强度。例如,当所述封装胶体30与所述基板10受到如热胀冷缩所产生的应力影响时,两者的黏合界面不致产生脱离,从而使所述封装胶体93内的组件保持完善,确保产品质量。
本实用新型通过在所述基板10的上表面11上设置所述凹槽50来增强所述封装胶体30与所述基板10的结合强度,所述凹槽50设置的位置尽可能是靠近所谓的应力敏感区,例如所述焊垫13及或所述导线21,又或者所述凹槽50是靠近其它所述封装胶体30所要封装保护的组件,如所述基板10上的所述芯片20或组件(未绘示)。因此,本实用新型并不限制所述凹槽50的形状、数量及具体设置位置,使用者可依实际需求于所述基板10的上表面11上设计所述凹槽50的形态。本文将于后面的实施例中列举其中可能的样态,但非用以限制本实用新型。
另外,本实用新型亦不限制所述凹槽50形成的方式,使用者可选用机械或雷射加工的方式在所述基板10上制作出所述凹槽50,或者是在压合所述基板10时直接压出或迭合来形成所述凹槽50。
再者,在另一可能的实施例中,本实用新型也可适用于倒装芯片式的半导体基板封装构造。
请参照图3A及3B所示,图3A揭示本实用新型第二实施例的半导体基板封装构造封装前的局部俯视图;及图3B揭示图3A的半导体基板封装构造封装后的局部侧剖视图。本实用新型第二实施例的半导体基板封装构造相似于本实用新型第一实施例,并大致沿用相同组件名称及图号,但第二实施例的差异特征在于:在本实施例中,所述凹槽50数量为两个,所述凹槽50仍是呈长条状,分别设于靠近所述数个焊垫13对应的两侧边。特别是其中一个所述凹槽50是设于所述至少一芯片20与所述数个焊垫13之间,也就是在所述导线21的下方,因此所述凹槽50更能增加所述封装胶体30在此区域的的结合强度,从而保护较为脆弱的所述导线21。
请参照图4所示,图4揭示本实用新型第三实施例的半导体基板封装构造封装前的局部俯视图。本实用新型第三实施例的半导体基板封装构造相似于本实用新型第一实施例,并大致沿用相同组件名称及图号,但第三实施例的差异特征在于:在本实施例中,所述至少一凹槽50进一步变化为以所述数个焊垫13为中心的直角三边环绕状,因此能增强所述封装胶体30在所述数个焊垫13区域的结合强度。
请参照图5所示,图5揭示本实用新型第四实施例的半导体基板封装构造封装前的局部俯视图。本实用新型第四实施例的半导体基板封装构造相似于本实用新型第一实施例、第二实施例及第三实施例,并大致沿用相同组件名称及图号,但第四实施例的差异特征在于:在本实施例中,所述至少一凹槽50进一步变化为以所述数个焊垫13为中心的直角四边环绕圈状(方形圈状),因此更能增强所述封装胶体30在所述数个焊垫13及所述导线21区域的结合强度。
请参照图6所示,图6揭示本实用新型第五实施例的半导体基板封装构造封装前的局部俯视图。本实用新型第五实施例的半导体基板封装构造相似于本实用新型第四实施例,并大致沿用相同组件名称及图号,但第五实施例的差异特征在于:在本实施例中,所述直角四边环绕圈状(方形圈状)的凹槽50是以所述至少一芯片20为中心,或者是环绕靠近所述基板10的外围,因此更能增强所述封装胶体30对所述至少一芯片20或对整体所述基板10的结合强度。
请参照图7所示,图7揭示本实用新型第六实施例的半导体基板封装构造封装后的局部侧剖视图。本实用新型第六实施例的半导体基板封装构造相似于本实用新型第一实施例,并大致沿用相同组件名称及图号,但第六实施例的差异特征在于:所述凹槽50底部进一步形成一种过切(under cut)的形态,也就是所述凹槽50的一内底部的宽度大于所述凹槽50的一开口部的宽度,因此,可再进一步提高所述封装胶体30对所述基板10的结合强度。
请参照图8所示,图8揭示本实用新型第七实施例的半导体基板封装构造封装后的局部侧剖视图。本实用新型第七实施例的半导体基板封装构造相似于本实用新型第六实施例,并大致沿用相同组件名称及图号,但第七实施例的差异特征在于:所述凹槽50底部进一步形成一种具有倒锥角的形态,也就是所述凹槽50的一内底部的宽度大于所述凹槽50的一开口部的宽度,因此,也可提高所述封装胶体30对所述基板10的结合强度。
在上述本实用新型的第六实施例及第七实施例中,所述凹槽50可以是以机械或雷射加工的方式在所述基板10上制作出来,或者是在压合所述基板10时直接压出或迭合所形成。
综上所述,相较于现有半导体基板封装构造因为基板与封装胶体受到应力变化脱离,从而造成内部组件损坏的技术问题,图2至8的本实用新型是提供一种半导体基板封装构造100包含一基板10、至少一芯片20及一封装胶体30。所述基板10的上表面11承载所述至少一芯片20并另包含数个焊垫13,所述芯片20通过数条导线21电性连接至所述数个焊垫13。所述基板10的上表面11另具有至少一凹槽50,所述凹槽50呈长条状、直角三边环绕状或直角四边环绕圈状。当所述封装胶体30封装于所述基板10的上表面时,其包覆所述芯片20、所述数个焊垫13及所述数条导线21。并且,部分的所述封装胶体30填入所述至少一凹槽50之内,因此可增强所述封装胶体30与所述基板10的结合强度,使两者的黏合界面不易产生脱离,并可确保导线与焊垫的焊接结合可靠度或其它应力集中区域的结构完整性,从而提高所述半导体基板封装构造100的封装品质。
本实用新型已由上述相关实施例加以描述,然而上述实施例仅为实施本实用新型的范例。必需指出的是,已公开的实施例并未限制本实用新型的范围。相反地,包含于权利要求书的精神及范围的修改及均等设置均包括于本实用新型的范围内。

Claims (10)

1.一种半导体基板封装构造,其特征在于:所述半导体基板封装构造包含:
一基板,具有一上表面及一下表面;
至少一芯片,设于所述基板的上表面;及
一封装胶体,封装于所述基板的上表面,包覆所述至少一芯片;
其中所述基板的上表面具有至少一凹槽,部分所述封装胶体填入所述凹槽之内。
2.如权利要求1所述的半导体基板封装构造,其特征在于:所述至少一凹槽呈长条状、直角三边环绕状或直角四边环绕圈状。
3.如权利要求1所述的半导体基板封装构造,其特征在于:所述凹槽的一内底部的宽度大于所述凹槽的一开口部的宽度。
4.一种半导体基板封装构造,其特征在于:所述半导体基板封装构造包含:
一基板,具有一上表面及一下表面;
至少一芯片,设于所述基板的上表面;
数个焊垫,设于所述基板的上表面,所述至少一芯片通过数条导线电性连接至所述数个焊垫;及
一封装胶体,封装于所述基板的上表面,包覆所述至少一芯片、所述数个焊垫及所述数条导线;
其中所述基板的上表面具有至少一凹槽,部分所述封装胶体填入所述凹槽之内。
5.如权利要求4所述的半导体基板封装构造,其特征在于:所述至少一凹槽呈长条状,所述至少一凹槽邻接于所述数个焊垫。
6.如权利要求4所述的半导体基板封装构造,其特征在于:所述至少一凹槽设于所述至少一芯片与所述数个焊垫之间。
7.如权利要求4所述的半导体基板封装构造,其特征在于:所述至少一凹槽数量为两个并呈长条状,所述凹槽分别设于靠近所述数个焊垫对应的两侧边。
8.如权利要求4所述的半导体基板封装构造,其特征在于:所述至少一凹槽呈直角三边环绕状。
9.如权利要求4所述的半导体基板封装构造,其特征在于:所述至少一凹槽呈直角四边环绕圈状。
10.如权利要求4所述的半导体基板封装构造,其特征在于:所述凹槽的一内底部的宽度大于所述凹槽的一开口部的宽度。
CN2012200353368U 2012-02-03 2012-02-03 半导体基板封装构造 Expired - Lifetime CN202443963U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012200353368U CN202443963U (zh) 2012-02-03 2012-02-03 半导体基板封装构造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012200353368U CN202443963U (zh) 2012-02-03 2012-02-03 半导体基板封装构造

Publications (1)

Publication Number Publication Date
CN202443963U true CN202443963U (zh) 2012-09-19

Family

ID=46825397

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012200353368U Expired - Lifetime CN202443963U (zh) 2012-02-03 2012-02-03 半导体基板封装构造

Country Status (1)

Country Link
CN (1) CN202443963U (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304582A (zh) * 2014-07-25 2016-02-03 矽品精密工业股份有限公司 封装结构及其制法
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN108877501A (zh) * 2018-07-02 2018-11-23 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN113138476A (zh) * 2021-04-13 2021-07-20 武汉华星光电技术有限公司 液晶显示模组
US11652038B2 (en) 2013-11-19 2023-05-16 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package with front side and back side redistribution structures and fabricating method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11652038B2 (en) 2013-11-19 2023-05-16 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package with front side and back side redistribution structures and fabricating method thereof
CN105304582A (zh) * 2014-07-25 2016-02-03 矽品精密工业股份有限公司 封装结构及其制法
CN105304582B (zh) * 2014-07-25 2019-04-23 矽品精密工业股份有限公司 封装结构及其制法
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN108877501A (zh) * 2018-07-02 2018-11-23 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
US11337308B2 (en) 2018-07-02 2022-05-17 Ordos Yuansheng Optoelectronics Co., Ltd. Display panel and display apparatus
CN113138476A (zh) * 2021-04-13 2021-07-20 武汉华星光电技术有限公司 液晶显示模组
CN113138476B (zh) * 2021-04-13 2022-12-06 武汉华星光电技术有限公司 液晶显示模组

Similar Documents

Publication Publication Date Title
KR100652397B1 (ko) 매개 인쇄회로기판을 사용하는 적층형 반도체 패키지
CN203456452U (zh) 集成电路封装件
CN102867800B (zh) 将功能芯片连接至封装件以形成层叠封装件
KR101710178B1 (ko) 임베디이드 칩 온 칩 패키지 및 이를 포함하는 패키지 온 패키지
US7619305B2 (en) Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
CN202443963U (zh) 半导体基板封装构造
US20120267782A1 (en) Package-on-package semiconductor device
US7291906B2 (en) Stack package and fabricating method thereof
KR20140028014A (ko) 두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층
CN101232004A (zh) 芯片堆叠封装结构
JP2005203776A (ja) マルチチップパッケージ、これに使われる半導体装置及びその製造方法
CN111968958B (zh) 一种封装芯片及基于封装芯片的信号传输方法
CN101236940B (zh) 重配置线路层的线路结构
CN100470786C (zh) 基板底部封胶的球格阵列封装构造
CN102044528A (zh) 层叠封装件及其制造方法
US20120049359A1 (en) Ball grid array package
CN207409484U (zh) 一种集成芯片
CN101295697A (zh) 半导体封装构造
TWI387090B (zh) Reverse staggered stack structure of integrated circuit module
US8519522B2 (en) Semiconductor package
CN105845642A (zh) 层叠封装及移动终端
US8441129B2 (en) Semiconductor device
KR20020057351A (ko) 볼 그리드 어레이 패키지와 그 실장 구조
CN110444527A (zh) 一种芯片封装结构、装置及方法
CN204516737U (zh) 一种新型半导体防脱落封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20120919

CX01 Expiry of patent term