JP2005203776A - マルチチップパッケージ、これに使われる半導体装置及びその製造方法 - Google Patents
マルチチップパッケージ、これに使われる半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2005203776A JP2005203776A JP2005001942A JP2005001942A JP2005203776A JP 2005203776 A JP2005203776 A JP 2005203776A JP 2005001942 A JP2005001942 A JP 2005001942A JP 2005001942 A JP2005001942 A JP 2005001942A JP 2005203776 A JP2005203776 A JP 2005203776A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- semiconductor chip
- semiconductor
- dimensional space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 215
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000000853 adhesive Substances 0.000 claims description 48
- 230000001070 adhesive effect Effects 0.000 claims description 48
- 206010019133 Hangover Diseases 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 23
- 238000005530 etching Methods 0.000 description 9
- 238000000465 moulding Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- -1 tape Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】マルチチップパッケージ170は、上面に形成された複数の基板ボンディングパッド112を含む基板と、基板上に実装された少なくとも一つの第1半導体チップ120と、下面に少なくとも一つの第1半導体チップが置かれる少なくとも一つの3次元空間140を具備し、少なくとも一つの3次元空間により少なくとも一つの第1半導体チップを包む形態で基板上に実装された少なくとも一つの第2半導体チップ130を含む。
【選択図】図2
Description
111、112 基板ボンディングパッド
115 ターミナル
120 第1チップ
121 チップパッド
130 第2チップ
131 チップパッド
140 キャビティ
141 絶縁層
151 第1ボンディングワイヤー
152 第2ボンディングワイヤー
160 接着剤
170 パッケージ本体
180 ソルダボール
210 基板
211、212、213 基板ボンディングパッド
215 ターミナル
220 第1チップ
221 チップパッド
222 第1ボンディングワイヤー
230 第2チップ
231 チップパッド
232 第2ボンディングワイヤー
240 第3チップ
241 チップパッド
242 第3ボンディングワイヤー
250 第1キャビティ
251 第1絶縁層
260 第2キャビティ
261 第2絶縁層
270 絶縁性接着剤
280 パッケージ本体
290 ソルダボール
310 基板
311 第1基板ボンディングパッド
312 第2基板ボンディングパッド
315 ターミナル
320 第1チップ
321 チップパッド
322 第1ボンディングワイヤー
330 第2チップ
331 チップパッド
332 第2ボンディングワイヤー
340 溝
350 絶縁性接着剤
360 パッケージ本体
370 ソルダボール
410 基板
411、412、413 基板ボンディングパッド
415 ターミナル
420 第1チップ
421 チップパッド
422 第1ボンディングワイヤー
430 第2チップ
431 チップパッド
432 第2ボンディングワイヤー
440 第3チップ
441 チップパッド
442 第3ボンディングワイヤー
450 第1溝
460 第2溝
480 パッケージ本体
490 ソルダボール
510 基板
511 第1基板ボンディングパッド
512 第2基板ボンディングパッド
513 第3基板ボンディングパッド
515 ターミナル
520 第1チップ
521 チップパッド
522 第1ボンディングワイヤー
530 第2チップ
531 チップパッド
532 第2ボンディングワイヤー
540 第3チップ
541 チップパッド
542 第3ボンディングワイヤー
550 キャビティ
551 絶縁層
560 溝
570 接着剤
580 パッケージ本体
590 ソルダボール
610 基板
611、612 基板ボンディングパッド
615 ターミナル
620 第1チップ
621 チップパッド
622 第1ボンディングワイヤー
631 第1受動形素子
632 第2受動形素子
640 第2チップ
641 チップパッド
642 第2ボンディングワイヤー
650 キャビティ
651 絶縁層
670 接着剤
680 パッケージ本体
690 ソルダボール
710 基板
711、712、713、714 基板ボンディングパッド
715 ターミナル
720 第1チップ
721 チップパッド
722 第1ボンディングワイヤー
730 第2チップ
731 チップパッド
732 第2ボンディングワイヤー
740 第3チップ
741 チップパッド
742 第3ボンディングワイヤー
750 第4チップ
751 チップパッド
752 第4ボンディングワイヤー
761、762 3次元空間
781、782 パッケージ本体
790 ソルダボール
Claims (42)
- 上面に形成された複数の基板ボンディングパッドを含む基板と、
前記基板上に実装された少なくとも一つの第1半導体チップと、
下面に前記少なくとも一つの第1半導体チップが置かれる少なくとも一つの3次元空間を具備して、前記少なくとも一つの3次元空間により前記少なくとも一つの第1半導体チップを包む形態で前記基板上に実装された少なくとも一つの第2半導体チップと、を含むことを特徴とするマルチチップパッケージ。 - 前記少なくとも一つの3次元空間は、前記少なくとも一つの第2半導体チップの前記底面に形成されたキャビティ、溝またはこれらの組合せであることを特徴とする請求項1に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1及び第2半導体チップは前記基板ボンディングパッドにそれぞれワイヤーボンディング、フリップチップボンディングまたはこれらの組合せによりボンディングすることを特徴とする請求項2に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1半導体チップは前記基板に導電性接着剤により付着して、
前記少なくとも一つの3次元空間内部の前記少なくとも一つの第1半導体チップとその実装手段及びその付着部分が封止されたことを特徴とする請求項1に記載のマルチチップパッケージ。 - 前記少なくとも一つの第1半導体チップは前記基板に絶縁性接着剤により付着して、
前記少なくとも一つの3次元空間内部の前記少なくとも一つの第1半導体チップとその実装手段及びその付着部分が封止されたり露出されることを特徴とする請求項1に記載のマルチチップパッケージ。 - 前記少なくとも一つの第2半導体チップとその実装手段及び付着部分はパッケージ本体により封止したことを特徴とする請求項1に記載のマルチチップパッケージ。
- 前記基板はモールディングされたリードフレーム、印刷回路基板、DBC、フレキシブルフィルム、またはインターポーザであることを特徴とする請求項1に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1半導体チップはRFチップであって、前記少なくとも一つの第2半導体チップはメモリーまたはロジック回路用チップであることを特徴とする請求項1に記載のマルチチップパッケージ。
- 上面に形成された複数の基板ボンディングパッドを含む基板と、
前記基板上に実装された少なくとも一つの第1半導体チップと、
前記基板上に実装された少なくとも一つの受動形素子と、
下面に前記少なくとも一つの第1半導体チップ及び前記少なくとも一つの受動形素子が置かれる少なくとも一つの3次元空間を具備して、前記少なくとも一つの3次元空間により前記少なくとも一つの第1半導体チップ及び前記少なくとも一つの受動形素子を包む形態で前記基板上に実装された少なくとも一つの第2半導体チップと、を含むことを特徴とするマルチチップパッケージ。 - 前記少なくとも一つの3次元空間は、前記少なくとも一つの第2半導体チップの前記底面に形成されたキャビティ、溝またはこれらの組合せであることを特徴とする請求項9に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1及び第2半導体チップは前記基板ボンディングパッドにそれぞれワイヤーボンディング、フリップチップボンディングまたはこれらの組合せによりボンディングすることを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記少なくとも一つの受動形素子は前記基板に導電性接着剤により付着して、前記少なくとも一つの第1半導体チップは前記基板に絶縁性接着剤により付着することを特徴とする請求項9に記載のマルチチップパッケージ。
- 前記少なくとも一つの第2半導体チップとその実装手段及び付着部分が封止されたことを特徴とする請求項9に記載のマルチチップパッケージ。
- 前記基板はモールディングされたリードフレーム、印刷回路基板、DBC、フレキシブルフィルム、またはインターポーザであることを特徴とする請求項9に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1半導体チップはRFチップであって、前記少なくとも一つの第2半導体チップはメモリーまたはロジック回路用チップであることを特徴とする請求項9に記載のマルチチップパッケージ。
- 上面及び下面に形成された複数の基板ボンディングパッドを含む基板と、
前記基板上面に実装された少なくとも一つの第1半導体チップと、
前記基板下面に実装された少なくとも一つの第2半導体チップと、
非活性面上に形成された少なくとも一つの3次元空間を具備して、前記少なくとも一つの3次元空間により前記少なくとも一つの第1半導体チップを包む形態で前記基板上面に実装された少なくとも一つの第3半導体チップと、
非活性面上に形成された少なくとも一つの3次元空間を具備して、前記少なくとも一つの3次元空間により前記少なくとも一つの第2半導体チップを包む形態で前記基板下面に実装された少なくとも一つの第4半導体チップと、を含むことを特徴とするマルチチップパッケージ。 - 前記少なくとも一つの第3半導体チップと前記少なくとも一つの第4半導体チップにおける前記少なくとも一つの3次元空間は、前記少なくとも一つの第3及び第4半導体チップの非活性面上に形成されたキャビティ、溝またはこれらの組合せであることを特徴とする請求項16に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1ないし第4半導体チップは前記基板ボンディングパッドにそれぞれワイヤーボンディング、フリップチップボンディングまたはこれらの組合せによりボンディングすることを特徴とする請求項17に記載のマルチチップパッケージ。
- 前記少なくとも一つの第2及び第4半導体チップとその実装手段及び付着部分が封止されたことを特徴とする請求項16に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1及び第3半導体チップとその実装手段及び付着部分が封止されたことを特徴とする請求項16に記載のマルチチップパッケージ。
- 前記基板はモールディングされたリードフレーム、印刷回路基板、DBC、フレキシブルフィルム、またはインターポーザであることを特徴とする請求項16に記載のマルチチップパッケージ。
- 前記少なくとも一つの第1半導体チップと前記少なくとも一つの第3半導体チップはRFチップであって、前記少なくとも一つの第2半導体チップと前記少なくとも一つの第4半導体チップはメモリーまたはロジック回路用チップであることを特徴とする請求項16に記載のマルチチップパッケージ。
- 活性面とその反対面である非活性面を有する基板、及び
前記基板の前記活性面上に形成されたチップパッドを含んで、
少なくとも一つの3次元空間が前記基板の活性面または非活性面に形成されたことを特徴とするマルチチップパッケージに使われる半導体装置。 - 前記少なくとも一つの3次元空間は前記半導体装置の一面に形成されたキャビティ、溝またはこれらの組合せの形態に形成されたことを特徴とする請求項23に記載のマルチチップパッケージに使われる半導体装置。
- 前記少なくとも一つの3次元空間は前記非活性面上に形成されており、前記チップパッドは外部の基板上にワイヤーボンディングすることを特徴とする請求項24に記載のマルチチップパッケージに使われる半導体装置。
- 前記少なくとも一つの3次元空間は前記活性面上に形成されており、前記チップパッドは外部の基板上にフリップチップボンディングすることを特徴とする請求項24に記載のマルチチップパッケージに使われる半導体装置。
- 活性面上に形成された複数の基板ボンディングパッドとこれによる非活性面を含む基板、及び
前記基板上に実装された少なくとも2個の半導体チップを含んで、
前記少なくとも2個の半導体チップのうち一つは少なくとも一つの3次元空間を含んでいて、前記少なくとも一つの3次元空間により前記少なくとも2個の半導体チップのうち他の一つを包むようにすることを特徴とするマルチチップパッケージ。 - 前記少なくとも一つの3次元空間は前記活性面に形成されたことを特徴とする請求項27に記載のマルチチップパッケージ。
- 前記少なくとも一つの3次元空間は前記基板の非活性面に形成されたことを特徴とする請求項27に記載のマルチチップパッケージ。
- 前記少なくとも一つの3次元空間は、前記少なくとも2個の半導体チップのうち一つの一面に形成されたキャビティ、溝またはこれらの組合せであることを特徴とする請求項27に記載のマルチチップパッケージ。
- 前記少なくとも2個の半導体チップは、ワイヤーボンディングまたはフリップチップボンディングのうち少なくとも一つにより前記基板ボンディングパッドにボンディングすることを特徴とする請求項27に記載のマルチチップパッケージ。
- 前記少なくとも2個の半導体チップとその実装手段及び付着部分が封止されたことを特徴とする請求項27に記載のマルチチップパッケージ。
- 基板の活性面上に複数の基板ボンディングパッドを形成する段階と、
前記基板上に少なくとも一つの第1半導体チップを実装する段階と、
前記基板上に少なくとも一つの第2半導体チップを実装する段階と、を含んで、
前記少なくとも一つの第2半導体チップは、一面に少なくとも一つの3次元空間を具備して、前記少なくとも一つの3次元空間により前記少なくとも一つの第1半導体チップを包むようにすることを特徴とするマルチチップパッケージの製造方法。 - 前記少なくとも一つの3次元空間は前記基板の活性面上に形成されたことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 前記少なくとも一つの3次元空間は、前記少なくとも一つの第2半導体チップの底面に形成されたキャビティ、溝またはこれらの組合せであることを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- ワイヤーボンディングまたはフリップチップボンディングのうち少なくとも一つにより前記少なくとも一つの第1半導体チップと前記少なくとも一つの第2半導体チップを前記基板ボンディングパッドに連結する段階をさらに含むことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 導電性接着剤を利用して前記基板に前記少なくとも一つの第1半導体チップを付着する段階をさらに含むことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 絶縁性接着剤を利用して前記基板に前記少なくとも一つの第1半導体チップを付着する段階をさらに含むことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 前記少なくとも一つの第1半導体チップとその実装手段及び付着部分を前記少なくとも一つの3次元空間内部で封止したことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 前記少なくとも一つの第2半導体チップとその実装手段及び付着部分をパッケージ本体により封止したことを特徴とする請求項33に記載のマルチチップパッケージの製造方法。
- 第33項の製造方法により製造されたことを特徴とするマルチチップパッケージ。
- 第33項の製造方法により製造されたことを特徴とするマルチチップパッケージに使われる半導体装置。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2004-002369 | 2004-01-13 | ||
KR20040002369 | 2004-01-13 | ||
KR1020040040420A KR100632476B1 (ko) | 2004-01-13 | 2004-06-03 | 멀티칩 패키지 및 이에 사용되는 반도체칩 |
KR2004-040420 | 2004-06-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005203776A true JP2005203776A (ja) | 2005-07-28 |
JP4808408B2 JP4808408B2 (ja) | 2011-11-02 |
Family
ID=36121603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005001942A Active JP4808408B2 (ja) | 2004-01-13 | 2005-01-06 | マルチチップパッケージ、これに使われる半導体装置及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7327020B2 (ja) |
JP (1) | JP4808408B2 (ja) |
CN (1) | CN1641873A (ja) |
DE (1) | DE102005002631B4 (ja) |
NL (1) | NL1027962C2 (ja) |
TW (1) | TWI278947B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007103680A (ja) * | 2005-10-05 | 2007-04-19 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US8330278B2 (en) | 2008-10-28 | 2012-12-11 | Samsung Electronics Co., Ltd. | Semiconductor package including a plurality of stacked semiconductor devices |
KR101222474B1 (ko) | 2011-07-01 | 2013-01-15 | (주)에프씨아이 | 반도체 패키지 및 그 반도체 패키지 제조방법 |
JP2017168533A (ja) * | 2016-03-14 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6297548B1 (en) | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
US6351028B1 (en) * | 1999-02-08 | 2002-02-26 | Micron Technology, Inc. | Multiple die stack apparatus employing T-shaped interposer elements |
JP4553720B2 (ja) * | 2004-12-21 | 2010-09-29 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP2006210402A (ja) * | 2005-01-25 | 2006-08-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP4408832B2 (ja) * | 2005-05-20 | 2010-02-03 | Necエレクトロニクス株式会社 | 半導体装置 |
KR100721353B1 (ko) * | 2005-07-08 | 2007-05-25 | 삼성전자주식회사 | 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조 |
KR100764682B1 (ko) * | 2006-02-14 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | 집적회로 칩 및 패키지. |
US7420206B2 (en) | 2006-07-12 | 2008-09-02 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
US20080032451A1 (en) * | 2006-08-07 | 2008-02-07 | Sandisk Il Ltd. | Method of providing inverted pyramid multi-die package reducing wire sweep and weakening torques |
US20080029885A1 (en) * | 2006-08-07 | 2008-02-07 | Sandisk Il Ltd. | Inverted Pyramid Multi-Die Package Reducing Wire Sweep And Weakening Torques |
JP2008103571A (ja) * | 2006-10-19 | 2008-05-01 | Toshiba Corp | 半導体装置及びその製造方法 |
CN101279709B (zh) * | 2007-04-04 | 2011-01-19 | 财团法人工业技术研究院 | 微型声波传感器的多层式封装结构 |
JP2009176978A (ja) * | 2008-01-25 | 2009-08-06 | Rohm Co Ltd | 半導体装置 |
SG142321A1 (en) | 2008-04-24 | 2009-11-26 | Micron Technology Inc | Pre-encapsulated cavity interposer |
KR101118719B1 (ko) * | 2008-06-30 | 2012-03-13 | 샌디스크 코포레이션 | 와이어 접합을 위한 국소 공동을 구비한 적층 반도체 패키지 및 그 제조 방법 |
US8470640B2 (en) * | 2008-06-30 | 2013-06-25 | Sandisk Technologies Inc. | Method of fabricating stacked semiconductor package with localized cavities for wire bonding |
US8294251B2 (en) * | 2008-06-30 | 2012-10-23 | Sandisk Technologies Inc. | Stacked semiconductor package with localized cavities for wire bonding |
JP2010199286A (ja) * | 2009-02-25 | 2010-09-09 | Elpida Memory Inc | 半導体装置 |
JP2013501380A (ja) | 2009-08-06 | 2013-01-10 | ラムバス・インコーポレーテッド | 高性能メモリ用およびロジック用パッケージ半導体デバイス |
JP5646830B2 (ja) * | 2009-09-02 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及びリードフレーム |
US8018027B2 (en) * | 2009-10-30 | 2011-09-13 | Murata Manufacturing Co., Ltd. | Flip-bonded dual-substrate inductor, flip-bonded dual-substrate inductor, and integrated passive device including a flip-bonded dual-substrate inductor |
TWI501380B (zh) * | 2010-01-29 | 2015-09-21 | Nat Chip Implementation Ct Nat Applied Res Lab | 多基板晶片模組堆疊之三維系統晶片結構 |
US8598695B2 (en) * | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
KR20120062366A (ko) * | 2010-12-06 | 2012-06-14 | 삼성전자주식회사 | 멀티칩 패키지의 제조 방법 |
KR101465968B1 (ko) * | 2010-12-20 | 2014-11-28 | 인텔 코포레이션 | 칩 장치, 그 제조 방법 및 컴퓨터 시스템 |
US8637981B2 (en) | 2011-03-30 | 2014-01-28 | International Rectifier Corporation | Dual compartment semiconductor package with temperature sensor |
TWI473244B (zh) * | 2011-10-05 | 2015-02-11 | Chipsip Technology Co Ltd | 堆疊式半導體封裝結構 |
CN104681510A (zh) * | 2013-12-03 | 2015-06-03 | 晟碟信息科技(上海)有限公司 | 用于嵌入半导体裸片的桥结构 |
BR112015025989A8 (pt) | 2014-11-12 | 2020-01-14 | Intel Corp | soluções de sistema em embalagem flexível para dispositivos trajáveis |
JP6755842B2 (ja) * | 2017-08-28 | 2020-09-16 | 株式会社東芝 | 半導体装置、半導体装置の製造方法及び半導体パッケージの製造方法 |
JP2019161007A (ja) * | 2018-03-13 | 2019-09-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN108766974A (zh) * | 2018-08-08 | 2018-11-06 | 苏州晶方半导体科技股份有限公司 | 一种芯片封装结构以及芯片封装方法 |
DE102019126028A1 (de) * | 2019-09-26 | 2021-04-01 | Robert Bosch Gmbh | Multichipanordnung und entsprechendes Herstellungsverfahren |
CN110828442A (zh) * | 2019-11-04 | 2020-02-21 | 弘凯光电(深圳)有限公司 | 封装结构及其制作方法 |
US20220270997A1 (en) * | 2021-02-22 | 2022-08-25 | Mediatek Inc. | Semiconductor package |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003086734A (ja) * | 2001-09-12 | 2003-03-20 | Nec Corp | Cspのチップスタック構造 |
JP2003282817A (ja) * | 2002-03-27 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2004128356A (ja) * | 2002-10-04 | 2004-04-22 | Fujitsu Ltd | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100393094B1 (ko) | 1999-12-09 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | 지지각을 갖는 기판을 이용한 반도체 패키지 |
JP3888854B2 (ja) * | 2001-02-16 | 2007-03-07 | シャープ株式会社 | 半導体集積回路の製造方法 |
JP4633971B2 (ja) | 2001-07-11 | 2011-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR20030018204A (ko) | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | 스페이서를 갖는 멀티 칩 패키지 |
DE10142119B4 (de) * | 2001-08-30 | 2007-07-26 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zu seiner Herstellung |
US7332819B2 (en) * | 2002-01-09 | 2008-02-19 | Micron Technology, Inc. | Stacked die in die BGA package |
JP3507059B2 (ja) * | 2002-06-27 | 2004-03-15 | 沖電気工業株式会社 | 積層マルチチップパッケージ |
DE10209204B4 (de) * | 2002-03-04 | 2009-05-14 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben |
US6737738B2 (en) * | 2002-07-16 | 2004-05-18 | Kingston Technology Corporation | Multi-level package for a memory module |
-
2004
- 2004-12-22 TW TW093139967A patent/TWI278947B/zh active
-
2005
- 2005-01-05 NL NL1027962A patent/NL1027962C2/nl active Search and Examination
- 2005-01-05 CN CNA2005100039727A patent/CN1641873A/zh active Pending
- 2005-01-06 JP JP2005001942A patent/JP4808408B2/ja active Active
- 2005-01-12 DE DE102005002631A patent/DE102005002631B4/de active Active
- 2005-01-13 US US11/033,997 patent/US7327020B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003086734A (ja) * | 2001-09-12 | 2003-03-20 | Nec Corp | Cspのチップスタック構造 |
JP2003282817A (ja) * | 2002-03-27 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2004128356A (ja) * | 2002-10-04 | 2004-04-22 | Fujitsu Ltd | 半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007103680A (ja) * | 2005-10-05 | 2007-04-19 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP4716836B2 (ja) * | 2005-10-05 | 2011-07-06 | パナソニック株式会社 | 半導体装置 |
US8330278B2 (en) | 2008-10-28 | 2012-12-11 | Samsung Electronics Co., Ltd. | Semiconductor package including a plurality of stacked semiconductor devices |
KR101222474B1 (ko) | 2011-07-01 | 2013-01-15 | (주)에프씨아이 | 반도체 패키지 및 그 반도체 패키지 제조방법 |
JP2017168533A (ja) * | 2016-03-14 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1641873A (zh) | 2005-07-20 |
DE102005002631B4 (de) | 2007-05-03 |
US7327020B2 (en) | 2008-02-05 |
JP4808408B2 (ja) | 2011-11-02 |
NL1027962C2 (nl) | 2006-02-20 |
DE102005002631A1 (de) | 2005-08-11 |
NL1027962A1 (nl) | 2005-07-14 |
TWI278947B (en) | 2007-04-11 |
TW200525671A (en) | 2005-08-01 |
US20050194673A1 (en) | 2005-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4808408B2 (ja) | マルチチップパッケージ、これに使われる半導体装置及びその製造方法 | |
KR101070913B1 (ko) | 반도체 칩 적층 패키지 | |
US7119427B2 (en) | Stacked BGA packages | |
JP4703980B2 (ja) | 積層型ボールグリッドアレイパッケージ及びその製造方法 | |
US6555917B1 (en) | Semiconductor package having stacked semiconductor chips and method of making the same | |
KR20050119414A (ko) | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 | |
US20060284298A1 (en) | Chip stack package having same length bonding leads | |
JPH11135670A (ja) | ボールグリッドアレイパッケージ | |
JP2000101016A (ja) | 半導体集積回路装置 | |
TWI416700B (zh) | 晶片堆疊封裝結構及其製造方法 | |
KR100632476B1 (ko) | 멀티칩 패키지 및 이에 사용되는 반도체칩 | |
KR100994209B1 (ko) | 반도체 적층 패키지 | |
KR100443516B1 (ko) | 적층 패키지 및 그 제조 방법 | |
KR100388211B1 (ko) | 멀티 칩 패키지 | |
KR20050027384A (ko) | 재배선 패드를 갖는 칩 사이즈 패키지 및 그 적층체 | |
JP3418759B2 (ja) | 半導体パッケージ | |
US8026615B2 (en) | IC package reducing wiring layers on substrate and its carrier | |
KR100401019B1 (ko) | 반도체패키지 및 그 제조방법 | |
TWI447869B (zh) | 晶片堆疊封裝結構及其應用 | |
US9966364B2 (en) | Semiconductor package and method for fabricating the same | |
KR100480908B1 (ko) | 적층 칩 패키지의 제조 방법 | |
KR20020064415A (ko) | 반도체 패키지 | |
KR100406447B1 (ko) | 반도체패키지 및 그 제조방법 | |
TWI534978B (zh) | 晶片封裝結構 | |
JP2001291818A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071227 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100712 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100823 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100914 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101025 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110719 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110817 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140826 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4808408 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |