JP4553720B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4553720B2 JP4553720B2 JP2004369876A JP2004369876A JP4553720B2 JP 4553720 B2 JP4553720 B2 JP 4553720B2 JP 2004369876 A JP2004369876 A JP 2004369876A JP 2004369876 A JP2004369876 A JP 2004369876A JP 4553720 B2 JP4553720 B2 JP 4553720B2
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Description
まず、図1及び図2を参照して、この発明の半導体装置の構成例につき説明する。
ここで、図3を参照して、この発明の半導体装置において、第1の半導体チップとして適用して好適な加速度センサチップの構成例につき説明する。
次に、この発明の半導体装置の変形例の構成例につき、図2(B)を参照して説明する。
図4から図7を参照して、この発明の半導体装置の製造方法例につき説明する。なお、この発明の半導体装置の製造工程は、従来公知の材料を用いて、従来公知の製造工程により形成できる。従って、各製造工程における材料、条件等の詳細な説明は省略する場合もある。
20:リードフレーム
20a:個片領域
21:フレーム部
21a:スプロケットホール
22:基部
23:チップ搭載部
23a:チップ搭載領域
24:絶縁膜
25:空隙部
26:配線部
27:支持リード
28:リード
28a:露出部
29:チップ搭載凹部
30:第1の半導体チップ(加速度センサチップ)
30a:表面
30b:裏面
31:開口部
32:第1電極パッド
33:可動構造体
34:可動部(錘部)
34a:上面
34b:下面
35:梁部
36:検出素子
37:枠体部
42:第1ボンディングワイヤ
44:第2ボンディングワイヤ
46:第3ボンディングワイヤ
50:第2の半導体チップ(制御チップ)
50a:第1の主表面
50b:第2の主表面
50c:底面
52:凹部
54:第2電極パッド
60:封止部
Claims (6)
- 基部、該基部の表面を覆って設けられている絶縁膜、前記基部の端縁に沿って、前記絶縁膜上に配列されている複数の配線部、及び複数の当該配線部の配列より内側に設けられているチップ搭載領域を有するチップ搭載部、並びに該チップ搭載部から離間して設けられていて、該チップ搭載部の周囲を囲んでいる複数のリードを含むリードフレームと、
前記リードフレームの前記チップ搭載領域上に搭載されている、複数の第1電極パッドを有する第1の半導体チップと、
前記第1電極パッド及び前記配線部を電気的に接続している第1ボンディングワイヤと、
第1の主表面及び該第1の主表面と対向する第2の主表面を有していて、前記複数の配線部の一部分を露出させて、前記チップ搭載部上に搭載されている第2の半導体チップであって、前記第2の主表面から該第2の半導体チップの内部に形成されている凹部及び前記第1の主表面から露出されて、かつ前記第1の主表面の端縁に沿って設けられている複数の第2電極パッドを有している前記第2の半導体チップと、
前記第2の半導体チップから露出する前記配線部及び前記リードを電気的に接続している第2ボンディングワイヤと、
前記第2電極パッド及び前記リードを電気的に接続している第3ボンディングワイヤと、
前記第2及び第3ボンディングワイヤ、前記第2の半導体チップ、及び前記リードを該リードの一部分を露出部として残して封止して、該リードの露出部を外部端子とする封止部と
を具え、
前記第1の半導体チップ及び前記第1ボンディングワイヤが、前記第2の半導体チップが有する前記凹部内に、前記第2の半導体チップと離間して格納されており、
前記第1の半導体チップは、可動部を含む可動構造体を有しているMEMSチップであり、
前記第1電極パッドは、前記可動構造体の動作に起因する信号が出力されるか、又は前記可動構造体に対して信号を入力するための電極パッドであり、及び
前記第2の半導体チップは前記MEMSチップを制御する制御チップである
ことを特徴とする半導体装置。 - 前記チップ搭載部の基部は、前記チップ搭載領域に、前記第1半導体チップを搭載する搭載凹部をさらに有しており、前記絶縁膜は、前記基部の表面を覆っており、及び前記第1の半導体チップは、前記搭載凹部内に納められて搭載されていることを特徴とする請求項1に記載の半導体装置。
- 前記第1の半導体チップは、表面及び該表面と対向する裏面を有していて、前記表面から前記裏面に至る開口部を囲む枠体部と、該枠体部から前記開口部内に延在している梁部と、前記開口部内に納められていて、前記梁部により可動に支持されている可動部とを含む可動構造体、及び当該可動構造体の変位を検出する検出素子を有している加速度センサチップであって、前記第1電極パッドは、前記検出素子と電気的に接続されて、前記枠体部に設けられていることを特徴とする請求項1又は2に記載の半導体装置。
- 基部、該基部の表面を覆って設けられている絶縁膜、前記基部の端縁に沿って、前記絶縁膜上に配列されている複数の配線部、及び複数の当該配線部の配列より内側に設けられているチップ搭載領域を有するチップ搭載部、並びに該チップ搭載部から離間して設けられていて、該チップ搭載部の周囲を囲んでいる複数のリードを含むリードフレームを準備する工程と、
複数の第1電極パッドを有する第1の半導体チップを、前記チップ搭載領域上に搭載する工程と、
前記第1電極パッド及び前記配線部を、第1ボンディングワイヤを用いて電気的に接続する工程と、
第1の主表面及び該第1の主表面と対向する第2の主表面を有している第2の半導体チップであって、前記第2の主表面から該第2の半導体チップの内部に形成されている凹部及び前記第1の主表面から露出されて、かつ前記第1の主表面の端縁に沿って設けられている複数の第2電極パッドを有している前記第2の半導体チップを準備する工程と、
前記第2の半導体チップを、前記複数の配線部の一部分を露出させて、前記チップ搭載部上に、搭載する工程と、
前記第2の半導体チップから露出する前記配線部及び前記リードを、第2ボンディングワイヤを用いて、電気的に接続する工程と、
前記第2電極パッド及び前記リードを、第3ボンディングワイヤを用いて、電気的に接続する工程と、
前記第2及び第3ボンディングワイヤ、前記第2の半導体チップ、及び前記リードを該リードの一部分を露出部として残して封止する封止部を形成する工程と、
前記封止部から露出する前記リード及び前記支持リードを切断して、個片化する工程と
を含み、
前記第1の半導体チップ及び前記第1ボンディングワイヤが、前記第2の半導体チップが有する前記凹部内に、前記第2の半導体チップと離間して格納されており、
前記第1の半導体チップは、可動部を含む可動構造体を有しているMEMSチップであり、
前記第1電極パッドは、前記可動構造体の動作に起因する信号が出力されるか、又は前記可動構造体に対して信号を入力するための電極パッドであり、及び
前記第2の半導体チップは前記MEMSチップを制御する制御チップである
ことを特徴とする半導体装置の製造方法。 - 前記第1の半導体チップを前記チップ搭載部に搭載する工程は、前記基部が、前記チップ搭載領域にさらに有している搭載凹部内に、前記第1の半導体チップを搭載する工程である
ことを特徴とする請求項4に記載の半導体装置の製造方法。 - 前記第1の半導体チップを前記チップ搭載領域に搭載する工程は、表面及び該表面と対向する裏面を有していて、前記表面から前記裏面に至る開口部を囲む枠体部と、該枠体部から前記開口部内に延在している梁部と、前記開口部内に納められていて、前記梁部により可動に支持されている可動部とを含む可動構造体、及び当該可動構造体の変位を検出する検出素子を有している加速度センサチップを、前記チップ搭載領域に搭載する工程であり、
前記第2の半導体チップを前記チップ搭載部に搭載する工程は、前記加速度センサチップを制御する制御チップである前記第2の半導体チップを、前記チップ搭載部に搭載する工程である
ことを特徴とする請求項4又は5に記載の半導体装置の製造方法。
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JP2004369876A JP4553720B2 (ja) | 2004-12-21 | 2004-12-21 | 半導体装置及びその製造方法 |
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JP2009063550A (ja) * | 2007-09-10 | 2009-03-26 | Rohm Co Ltd | 半導体センサ装置 |
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JP5172254B2 (ja) * | 2007-09-11 | 2013-03-27 | ローム株式会社 | 半導体装置 |
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US20060130582A1 (en) | 2006-06-22 |
JP2006179607A (ja) | 2006-07-06 |
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