JP5646830B2 - 半導体装置、半導体装置の製造方法、及びリードフレーム - Google Patents
半導体装置、半導体装置の製造方法、及びリードフレーム Download PDFInfo
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- JP5646830B2 JP5646830B2 JP2009203040A JP2009203040A JP5646830B2 JP 5646830 B2 JP5646830 B2 JP 5646830B2 JP 2009203040 A JP2009203040 A JP 2009203040A JP 2009203040 A JP2009203040 A JP 2009203040A JP 5646830 B2 JP5646830 B2 JP 5646830B2
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Description
第2多層配線層と、前記第2多層配線層に形成された第2インダクタとを有する第2半導体チップと、
を備え、
前記第1半導体チップと前記第2半導体チップは、前記第1多層配線層と前記第2多層配線層が互いに対向する向きに互いに重ねられており、
平面視において前記第1インダクタと前記第2インダクタが重なっており、
前記第1半導体チップ及び前記第2半導体チップは、それぞれ互いに対向していない非対向領域を有しており、
前記第1多層配線層は、前記非対向領域に第1外部接続端子を有しており、
前記第2多層配線層は、前記非対向領域に第2外部接続端子を有している半導体装置が提供される。
第2多層配線層、前記第2多層配線層に形成された第2インダクタ、及び前記第2多層配線層に形成された第2外部接続端子を有する第2半導体チップを、前記第1半導体チップ上に、前記第1多層配線層と前記第2多層配線層が互いに対向する向きに互いに重ねる工程と、
を備え、
前記第1半導体チップと前記第2半導体チップとを互いに重ねる工程において、
前記第1半導体チップ及び前記第2半導体チップそれぞれに、互いに対向していない領域を設け、かつ前記第1外部接続端子及び前記第2外部接続端子を当該領域に位置させる半導体装置の製造方法が提供される。
前記ダイパッドの一辺の近くから外側に向かって延伸している第1リードと、
前記ダイパッドの前記一辺とは異なる辺の近くから外側に向かって延伸している第2リードと、
を備え、
前記第1リードの先端から前記ダイパッドまでの距離は、前記第2リードの先端から前記ダイパッドまでの距離とは異なるリードフレームが提供される。
(付記1)
第1多層配線層、前記第1多層配線層に形成された第1インダクタ、及び前記第1多層配線層に形成された第1外部接続端子を有する第1半導体チップの裏面を、第1リードフレーム又は第1配線基板に固定する工程と、
第2多層配線層、前記第2多層配線層に形成された第2インダクタ、及び前記第2多層配線層に形成された第2外部接続端子を有する第2半導体チップを、前記第1半導体チップ上に対して位置決めしてから固定し、前記第1インダクタと前記第2インダクタを平面視において互いに重ねる工程と、
前記第1リードフレーム又は第1配線基板に対して第2リードフレームの位置決めを行い、その後前記第2半導体チップに前記第2リードフレームを固定する工程と、
を備える半導体装置の製造方法。
102 辺
110 第1多層配線層
120 配線
130 第1インダクタ
140 第1外部接続端子
160 第1ポリイミド層
162 開口
164 開口
170 第1保護絶縁膜
200 第2半導体チップ
202 辺
210 第2多層配線層
220 配線
230 第2インダクタ
240 第2外部接続端子
250 保護層
260 第2ポリイミド層
262 開口
264 開口
270 第2保護絶縁膜
300 第1リードフレーム
302 ダイパッド
304 吊りリード
305 吊りリード
306 リード
308 リード
310 第1ボンディングワイヤ
312 第2ボンディングワイヤ
320 第2リードフレーム
322 ダイパッド
340 封止樹脂
400 送信回路
402 変調処理部
404 送信側ドライバ回路
420 受信側回路
422 受信回路
424 受信側ドライバ回路
500 接着層
Claims (11)
- 第1多層配線層と、前記第1多層配線層に形成された第1インダクタとを有する第1半導体チップと、
第2多層配線層と、前記第2多層配線層に形成された第2インダクタとを有する第2半導体チップと、
を備え、
前記第1半導体チップと前記第2半導体チップは、前記第1多層配線層と前記第2多層配線層が互いに対向する向きに互いに重ねられており、
平面視において前記第1インダクタと前記第2インダクタが重なっており、
前記第1半導体チップ及び前記第2半導体チップは、それぞれ互いに対向していない非対向領域を有しており、
前記第1多層配線層は、前記非対向領域に第1外部接続端子を有しており、
前記第2多層配線層は、前記非対向領域に第2外部接続端子を有しており、
ダイパッド、第1リード、及び第2リードを有するリードフレームを有しており、
前記第1半導体チップは前記ダイパッドに搭載されており、
前記第1リードは、第1ボンディングワイヤを介して前記第1外部接続端子に接続しており、前記第2リードは、第2ボンディングワイヤを介して前記第2外部接続端子に接続しており、
前記第1半導体チップ及び前記第2半導体チップが積層されている方向において、前記第1リード及び前記第2リードは、いずれも、前記第1半導体チップ側に位置する第1面と、前記第2半導体チップ側に位置する第2面とを有しており、
前記第1ボンディングワイヤは前記第1リードの前記第2面に接続しており、
前記第2ボンディングワイヤは前記第2リードの前記第1面に接続しており、
前記ダイパッド、前記第1リード、及び前記第2リードは、一枚のリードフレーム材から構成されており、
前記ダイパッド、前記第1リードの一部、前記第2リードの一部、前記第1半導体チップ、前記第2半導体チップ、前記第1ボンディングワイヤ、および前記第2ボンディングワイヤは、封止樹脂によって封止されている半導体装置。 - 請求項1に記載の半導体装置において、
前記第1多層配線層は、平面視において前記第2半導体チップと重なる領域には、前記第1インダクタに接続する配線以外の配線を有していない半導体装置。 - 請求項2に記載の半導体装置において、
前記第2多層配線層は、平面視において前記第1半導体チップと重なる領域には、前記第2インダクタに接続する配線以外の配線を有していない半導体装置。 - 請求項1〜3のいずれか一つに記載の半導体装置において、
前記第1半導体チップと前記第2半導体チップを互いに固定する絶縁性の接着層をさらに備える半導体装置。 - 請求項1〜4のいずれか一項に記載の半導体装置において、
前記第2半導体チップの基板側に設けられ、平面視において前記第2半導体チップを覆っている保護層を備える半導体装置。 - 請求項1〜5のいずれか一つに記載の半導体装置において、
前記第1半導体チップは、前記第1多層配線層上に位置する第1ポリイミド層を有しており、
前記第2半導体チップは、前記第2多層配線層上に位置する第2ポリイミド層を有している半導体装置。 - 請求項6に記載の半導体装置において、
前記第1半導体チップは、前記第1多層配線層と前記第1ポリイミド層の間に第1保護絶縁膜を有しており、
前記第2半導体チップは、前記第2多層配線層と前記第2ポリイミド層の間に第2保護絶縁膜を有している半導体装置。 - 請求項6又は7に記載の半導体装置において、
前記第1ポリイミド層は、前記第1インダクタの上方に位置する領域には形成されておらず、
前記第2ポリイミド層は、前記第2インダクタの上方に位置する領域には形成されていない半導体装置。 - 請求項1〜8のいずれか一つに記載の半導体装置において、
前記第1半導体チップは、第1の辺の近傍に前記第1外部接続端子を有しており、
前記第2半導体チップは、平面視において前記第1の辺とは反対側に位置する第2の辺の近傍に前記第2外部接続端子を有している半導体装置。 - 請求項1〜9のいずれか一つに記載の半導体装置において、
前記第1インダクタ及び前記第2インダクタの直径をD、前記第1インダクタから前記第2インダクタまでの距離をxとしたときに、x≦Dである半導体装置。 - 第1多層配線層、前記第1多層配線層に形成された第1インダクタ、及び前記第1多層配線層に形成された第1外部接続端子を有する第1半導体チップを、第1リードフレームのダイパッドにフェイスアップ実装する工程と、
第2多層配線層、前記第2多層配線層に形成された第2インダクタ、及び前記第2多層配線層に形成された第2外部接続端子を有する第2半導体チップを、前記第1半導体チップ上に、前記第1多層配線層と前記第2多層配線層が互いに対向する向きに互いに重ね、前記第1インダクタと前記第2インダクタとを重ねる工程と、
を備え、
前記第1半導体チップと前記第2半導体チップとを互いに重ねる工程において、
前記第1半導体チップ及び前記第2半導体チップそれぞれに、互いに対向していない領域を設け、かつ前記第1外部接続端子及び前記第2外部接続端子を当該領域に位置させ、
前記第1リードフレームは、第1リード及び第2リードを備えており、
さらに、前記第2半導体チップを前記第1半導体チップ上に重ねる工程の後に、前記第1リードと前記第1外部接続端子とを第1ボンディングワイヤで接続し、かつ前記第2リードと前記第2外部接続端子とを第2ボンディングワイヤで接続する工程と、
前記ダイパッド、前記第1リードの一部、前記第2リードの一部、前記第1半導体チップ、前記第2半導体チップ、前記第1ボンディングワイヤ、および前記第2ボンディングワイヤを、封止樹脂によって封止する工程と、
を備え、
前記第1半導体チップ及び前記第2半導体チップが積層されている方向において、前記第1リード及び前記第2リードは、いずれも、前記第1半導体チップ側に位置する第1面と、前記第2半導体チップ側に位置する第2面とを有しており、
前記第1ボンディングワイヤを前記第1リードの前記第2面に接続し、かつ前記第2ボンディングワイヤを前記第2リードの前記第1面に接続する半導体装置の製造方法。
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