TWI668821B - 電子零件模組及其製造方法 - Google Patents
電子零件模組及其製造方法 Download PDFInfo
- Publication number
- TWI668821B TWI668821B TW106136342A TW106136342A TWI668821B TW I668821 B TWI668821 B TW I668821B TW 106136342 A TW106136342 A TW 106136342A TW 106136342 A TW106136342 A TW 106136342A TW I668821 B TWI668821 B TW I668821B
- Authority
- TW
- Taiwan
- Prior art keywords
- electronic component
- mounting substrate
- conductive film
- component module
- masking tape
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 39
- 239000011347 resin Substances 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 38
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 239000011241 protective layer Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 57
- 230000000873 masking effect Effects 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 22
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000002184 metal Substances 0.000 description 20
- 239000010949 copper Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 11
- 238000007747 plating Methods 0.000 description 9
- 239000000945 filler Substances 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 239000007864 aqueous solution Substances 0.000 description 6
- 238000004901 spalling Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007788 roughening Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003063 flame retardant Substances 0.000 description 3
- 239000013067 intermediate product Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000010191 image analysis Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Led Device Packages (AREA)
Abstract
本說明書揭示之電子零件模組係具備電子零件、對上述電子零件進行密封之密封樹脂、覆蓋上述密封樹脂之表面的導電膜、與覆蓋上述導電膜之表面的保護膜。上述保護膜係包含低反射層與保護層。上述低反射層係不與導電膜相接。
Description
本發明係關於電子零件模組及其製造方法。
以防止從內藏於電子零件模組等之電子零件所產生的電磁波雜訊之洩漏,並且阻止由周邊環境所產生的電磁波雜訊之侵入為目的,已進行藉由由金屬膜構成的電磁波屏蔽覆蓋電子零件周圍。近年來,隨著電子零件的小型化及高性能化的要求,對電磁波屏蔽亦要求小型化及高性能化。
已揭示有藉由於電子零件模組的表面直接形成金屬膜而減少空間的技術。
例如,日本專利特開2012-151326號公報中記載的電子零件的屏蔽方法,係具有藉由含有填料的密封樹脂密封安裝於基板的半導體裝置的步驟,削除密封樹脂的表面使填料之一部分露出的步驟,藉由對露出的填料進行蝕刻而在密封樹脂的表面形成孔的步驟,與在包含孔內面的密封樹脂的表面形成金屬膜的步驟。根據此屏蔽方法,金屬膜的錨定效應提高,金屬膜對密封樹脂表面的密黏性提高。另外,由於在密封樹脂的表面直接形成成為電磁屏蔽層的金屬膜,故相較於以金屬板包圍零件整體的情況,可使包含電磁屏蔽之電子零件模組整體小型化。
然而,若在電子零件模組的表面形成金屬膜則光的反射率增高,在進行由圖像識別之位置檢測時,有因暈影而圖像識別裝置無法正確識別電子零件模組、位置檢測精度降低的情形。
為了提高圖像識別的精度,較佳係金屬膜的反射率低。作為使金屬膜的反射率降低的方法,可舉例如進行金屬膜的粗化處理(黑化處理)的方法,但若進行金屬膜的粗化處理(黑化處理)時,金屬膜從側面被蝕刻,有由金屬膜構成的屏蔽發明剝離之虞。
因此,本發明的目的之一在於提供一種具備密黏性高且光反射率低之導電膜的電子零件模組。
為了解決上述課題,本案發明人等進行了深入研究,結果發明一種電子零件模組,其特徵在於具備電子零件、對上述電子零件進行密封之密封樹脂、覆蓋上述密封樹脂之表面的導電膜、與覆蓋上述導電膜之表面的保護膜,上述保護膜係分為低反射區域與導電區域,上述低反射區域係不與導電膜相接。
根據本發明,能夠提供一種具備密黏性高且光反射率低之導電膜的電子零件模組。
1‧‧‧電子零件模組
1a‧‧‧電子零件模組
2‧‧‧電子零件模組
10‧‧‧安裝基板
10a‧‧‧佈線圖案
10b‧‧‧佈線圖案
10c‧‧‧通孔導體
11‧‧‧電子零件
11a‧‧‧焊盤電極
12‧‧‧密封樹脂
12a‧‧‧上表面
12b‧‧‧側面
13‧‧‧導電膜
14‧‧‧保護膜
14a‧‧‧保護層
14b‧‧‧低反射層
16‧‧‧接合線
31‧‧‧遮罩膠帶
32‧‧‧遮罩膠帶
圖1為表示本發明較佳第一實施形態之電子零件模組之構造的簡略剖視圖。
圖2為圖1所示電子零件模組的局部放大圖。
圖3A及圖3B為用於說明保護層與低反射層之邊界線的示意圖。
圖4A至圖4D、圖5A至圖5C為用於說明圖1所示電子零件模組之製造方法的流程圖。
圖6為表示本發明較佳第二實施形態之電子零件模組之構造的簡略剖視圖。
圖7為圖6所示電子零件模組的局部放大圖。
圖8A至圖8C為用於說明比較例2~4之樣本之製造方法的流程圖。
圖9為表示實施例1~5及比較例1~4的評價結果的表。
以下,參照圖式並對本發明較佳實施形態詳細進行說明。
圖1為表示本發明較佳第一實施形態之電子零件模組1之構造的簡略剖視圖。另外,圖2為電子零件模組1的局部放大圖。
如圖1及圖2所示,電子零件模組1具備安裝基板10、安裝於安裝基板10上的電子零件11、對電子零件11進行密封的密封樹脂(塑型樹脂)12、覆蓋密封樹脂12之露出面的導電膜13、與覆蓋導電膜13的保護膜14。
安裝基板10係在絕緣基板之表面及背面分別形成有佈線圖案10a、10b的印刷佈線基板。作為絕緣基板,例如可使用FR4(阻燃型4,Flame Retardant Type 4)等玻璃環氧樹脂片材,亦可使用氧化鋁或SiC、氮化鋁等陶瓷基板,並無特別限定。安裝基板10具有貫通絕緣基板並連接佈線圖案10a和佈線圖案10b的通孔導體10c。安裝基板10之背面的佈線圖案10b係經由通孔導體10c及 接合線16而與電子零件11的焊盤電極11a電連接。
電子零件11的代表例為半導體IC晶片,藉由焊接安裝在安裝基板10上。電子零件11的焊盤電極11a係經由接合線16連接至佈線圖案10a。電子零件11亦可為片式電容器、片式電感等分立零件。另外,亦可將複數之電子零件11搭載於安裝基板10。
密封樹脂12係發揮保護電子零件11不受外部應力、濕氣、污染物質等影響之功能者。作為密封樹脂12的材料可使用環氧樹脂。密封樹脂12中包含由氧化物粒子構成的填料(充填劑),藉此可達到熱膨脹係數的降低、熱傳導度的提高等。
導電膜13係發揮作為遮蔽入射至電子零件11內之電磁場雜訊或由電子零件11輻射出之電磁場雜訊的電磁波屏蔽的作用者。導電膜13係覆蓋密封樹脂12的表面。在此,所謂密封樹脂12的表面是指未形成導電膜13之狀態的密封樹脂12之露出面,位於與電子零件11之安裝面(安裝基板10的上表面)相反側的密封樹脂12之上表面12a、及與安裝面正交的密封樹脂12的四個側面12b。導電膜13由於形成於密封樹脂12的露出面整體、亦即不僅形成於密封樹脂12的上表面12a、尚形成於側面12b,所以能夠提高屏蔽效果。進而,導電膜13亦形成於安裝基板10的側面。
作為導電膜13的材料,較佳為Cu(銅)。Cu的導電率高,在加工性及成本方面亦有利,因此適合作為電磁波屏蔽的材料。
導電膜13亦可為以Cu為主成分的合金膜,該情況下,較佳係合金膜進一步包含選自Ni、Co、Fe的至少一種金屬。在以Cu為主成分的金屬膜進一步包含此等金屬的至少一種的情況下,能夠降低導電膜13的應力。
保護膜14具有將保護層14a與低反射層14b依序積層的二層構造。低反射層14b為光反射率較導電膜13低的層,較佳係光反射率未滿20%。藉此可抑制暈影,能夠提高圖像識別性。低反射層14b可藉由利用鍍覆法或蝕刻法形成粗表面、或使平滑的表面粗糙化而製作。
於此,在藉由使保護膜14的表面粗糙化而形成低反射層14b的情況下,如圖3A所示,將連結形成於保護膜14表面之凹部的線L定義為保護層14a與低反射層14b的邊界。邊界未達到導電膜13。亦即,低反射層14b與導電膜13不直接相接,在低反射層14b與導電膜13之間必須介存保護層14a。相對於此,如屬於比較例的圖3B所示,當表示邊界的線L到達導電膜13時,低反射層14b與導電膜13相接,產生了在低反射層14b和導電膜13之間不介存保護層14a的部分。
作為保護層14a的材料,較佳為Ni。Ni係耐腐蝕性高,具有抑制導電膜腐蝕的效果。
保護層14a亦可為以Ni為主成分的合金膜,該情況下,較佳係含有P(磷),P的濃度較佳為2~19原子%。若將P濃度設定在此範圍內,能夠得到高的耐腐蝕性、耐磨損性。
圖4A至圖4D、圖5A至圖5C為用於說明電子零件模組1之製造方法的流程圖。如圖4A所示,在電子零件模組1的製造時,首先,準備在安裝基板10上安裝電子零件11、並藉由含有填料的密封樹脂12對電子零件11進行了密封的作為中間製品的電子零件模組1a(步驟1)。
接著,如圖4B所示,在構成電子零件模組的安裝基 板10的背面貼附遮罩膠帶31,利用遮罩膠帶31覆蓋形成於安裝基板10之背面的佈線圖案10b(步驟2)。遮罩膠帶31的平面尺寸係較安裝基板10的平面尺寸大,因此,藉由遮罩膠帶31覆蓋安裝基板10之背面的整面。
接著,如圖4C所示,在密封樹脂12的表面形成以Cu為主成分的導電膜13(步驟3)。
接著,如圖4D所示,剝離遮罩膠帶31後,利用另外的遮罩膠帶32覆蓋形成於安裝基板10之背面的佈線圖案10b(步驟4)。此時,其他的遮罩膠帶32係使用尺寸較最初的遮罩膠帶31小的遮罩膠帶,以使導電膜13的端面、亦即導電膜13與最初的遮罩膠帶31的接觸面露出。遮罩膠帶32的平面尺寸亦可與安裝基板10的平面尺寸相同。該情況下,藉由遮罩膠帶32覆蓋安裝基板10之背面的整面。
接著,如圖5A所示,在導電膜13的表面形成以Ni為主成分的保護膜14(步驟5)。
導電膜13及保護膜14的形成方法並無特別限定,亦可藉由非電解鍍覆法或濺射法、印刷法等進行。
接著,如圖5B所示,對保護膜14進行黑化處理,使保護膜14的表面變化為低反射層14b(步驟6)。保護膜14中未變化為低反射層14b的剩餘部分成為保護層14a。
黑化處理可藉由非電解鍍覆法或蝕刻法等進行。藉由非電解鍍覆形成低反射層14b的理由在於,因為非電解鍍覆所造成之析出物堆積在保護膜14的表面,在保護膜14的表面形成凹凸所致。為了抑制暈影,較佳係低反射層14b的表面較粗糙。
接著,如圖5C所示,剝離遮罩膠帶(步驟7)。
如上,完成具有利用導電膜13覆蓋密封樹脂12之表面的構造的電子零件模組1。如此,在本實施形態的電子零件模組的製造方法中,在用平面尺寸大的遮罩膠帶31覆蓋的狀態下形成導電膜13後,剝離遮罩膠帶31,在利用平面尺寸小的其它的遮罩膠帶32覆蓋的狀態下,形成保護膜14,因此,能夠利用保護膜14完全覆蓋導電膜13的端面。
圖6為表示本發明較佳第二實施形態之電子零件模組2之構造的略剖視圖。另外,圖7為電子零件模組2的局部放大圖。
如圖6及圖7所示,電子零件模組2與上述電子零件模組1之差異點在於導電膜13、保護層14a及低反射層14b的一部分迂回到安裝基板10之背面。其它構成則與上述電子零件模組1相同,因此對相同的要件標註相同的符號,重複之說明省略。根據本實施形態的電子零件模組2,因導電膜13的密黏性更高,所以導電膜13剝落更不易發生。此外,形成於安裝基板10之背面的保護層14a的端面亦可不被低反射層14b覆蓋而露出。
本實施形態的電子零件模組2可藉由使圖4D所示之遮罩膠帶32的寬度較安裝基板之寬度短而製作。
以上,對本發明較佳實施形態進行了說明,但本發明並不限定於上述的實施形態,在不脫離本發明主旨的範圍內可進行各種變更,不言而喻,此等亦包含於本發明範圍內。
‧實施例1~5
實際製作具有與圖1所示電子零件模組1相同構造的實施例1~4之樣本、及具有與圖6所示電子零件模組2相同構造的實施例5之樣本。
首先,準備在安裝基板上安裝電子零件、並藉由含有由二氧化矽所構成之填料的密封樹脂(塑型樹脂)密封電子零件而作為中間製品的電子零件模組的樣本(參照圖4A)。作為安裝基板,使用了FR4(阻燃型4,Flame Retardant Type 4)樹脂印刷佈線基板。
接著,在安裝基板的底面黏貼遮罩膠帶,覆蓋安裝基板的底面整體(參照圖4B)。接著,藉由非電解鍍覆法形成導電膜(參照圖4C)。在非電解鍍覆步驟中,首先,將電子零件模組浸漬在包含Sn和Pd之膠體的水溶液5分鐘後,利用純水進行洗淨後,在非電解鍍Cu液中浸漬50分鐘後,用純水進行洗淨,得到厚度2.0μm的Cu膜。
接著,剝除遮罩膠帶,依使先前製作之Cu膜之端面露出的方式再次黏貼遮罩膠帶,覆蓋佈線圖案(參照圖4D)。此時,對於實施例1~4的樣本,使用具有與安裝基板相同之平面尺寸的遮罩膠帶。另一方面,對於實施例5的樣本,使用平面尺寸較安裝基板小的遮罩膠帶,藉此使安裝基板之背面的最外周部分露出,只覆蓋被最外周部分包圍的中心部分。
接著,在含有Pd離子的水溶液中浸漬5分鐘,用純水進行洗淨後,在非電解鍍Ni液中浸漬10分鐘,用純水進行洗淨,得到2.0μm的Ni膜(參照圖5A)。在實施例5的樣本中,因遮罩膠帶的平面尺寸較安裝基板小,所以在安裝基板之背面的最外周部分 亦形成有Ni膜。
接著,藉由浸漬在過硫酸鈉10%水溶液中,對非電解鍍Ni進行黑化處理(參照圖5B)。藉此,非電解鍍Ni的表面變化為低反射層。藉由改變黑化處理的時間,製作實施例1~5的樣本。最後剝離遮罩膠帶(參照圖5C)。
‧比較例1
除了省略了藉黑化處理所進行的低反射層形成之外,其餘依與實施例1相同的手續作成比較例1之樣本。
‧比較例2、3、4
實際製作具有與圖3B所示電子零件模組相同構造的比較例2~4之樣本。
首先,準備在安裝基板上安裝電子零件、並藉由含有由二氧化矽所構成之填料的密封樹脂(塑型樹脂)密封電子零件而作為中間製品的電子零件模組的樣本(參照圖4A)。作為安裝基板,使用了FR4(阻燃型4,Flame Retardant Type 4)樹脂印刷佈線基板。
接著,在安裝基板的底面黏貼遮罩膠帶,覆蓋安裝基板的底面整體(參照圖4B)。接著,藉由非電解鍍覆法形成導電膜(參照圖4C)。在非電解鍍覆步驟中,首先,將電子零件模組浸漬在包含Sn和Pd之膠體的水溶液5分鐘後,利用純水進行洗淨後,在非電解鍍Cu液中浸漬50分鐘後,用純水進行洗淨,得到厚度2.0μm的Cu膜。接著,維持黏貼著遮罩膠帶,在含有Pd離子的水溶液中浸漬5分鐘,用純水進行洗淨後,在非電解鍍Ni液中浸漬10 分鐘,用純水進行洗淨,得到2.0μm的Ni膜(參照圖8A)。
接著,藉由浸漬在過硫酸鈉10%水溶液中,對非電解鍍Ni進行黑化處理(參照圖8B)。藉此,非電解鍍Ni的表面變化為低反射層。藉由改變黑化處理的時間,製作比較例2~4的樣本。最後剝離遮罩膠帶(參照圖8C)。
對以上的電子零件模組的實施例1~5、比較例1~4,進行圖像解析及帶剝離試驗。可見光反射率係使用Spectrophotometer CM-5(Konica-Minolta製),在360nm至740nm的波長域測定反射光,評價平均值。低反射層係進行剖面研磨,評價保護層與低反射層的邊界。在看不到邊界線的情況,係藉由連結剖面之凹部之底的外側(低反射區域)與內側(保護層區域)定義邊界(參照圖3A、3B所示的虛線L),評價低反射層之凹部的底是否達到導電層。分別藉由1個樣本對相同部位重複進行圖像解析10次,將檢測位置相對於實際樣本的側面位置的偏差為10μm以下的情況視為◎,將20μm以下的情況視為○,將偏差最大50μm以上的情況視為×。
密黏性係將膠帶牢固地黏貼於樣本的底面,約3分鐘後歷時0.5~1.0秒以接近於60°的角度進行膠帶的剝離而進行評價。
膠帶剝離後,藉由目視確認表面狀態,藉由以下5階段評價金屬膜對於密封樹脂的密黏性(剝落狀態)。
在此,5階段評價為:「1」為具有小範圍之剝落的情況(剝落率為5%以下);「2」為剝落為5~15%左右的情況;「3」為局部或全面性大幅剝落,及/或局部或全面性剝落的情 況(剝落15~35%左右);「4」為局部或全面性大幅剝落,及/或局部或全面性剝落的情況(剝落35%以上);「5」為剝落較「4」更大的情況。
「1」、「2」為金屬膜的密黏性良好,「3」、「4」、「5」為金屬膜的密黏性不良。
將結果示於圖9。如圖9所示,比較例1的樣本雖然導電膜的密黏性佳,但反射率高而在藉由圖像識別時有超過20μm的偏差。比較例2~4的樣本係反射率低但密黏性差。實施例1~4的樣本係圖像識別性良好、密黏性亦佳。特別是實施例5的樣本係圖像識別性良好,密黏性更佳。
Claims (14)
- 一種電子零件模組,其特徵在於具備:電子零件;對上述電子零件進行密封的密封樹脂;覆蓋上述密封樹脂之表面的導電膜;與覆蓋上述導電膜之表面的保護膜;上述保護膜係包含低反射層與保護層;上述低反射層係不與導電膜相接,且上述低反射層係光反射率為20%以下。
- 如請求項1之電子零件模組,其中,進一步具備在表面搭載有上述電子零件的安裝基板;上述導電膜及上述保護膜係覆蓋上述安裝基板之背面的一部分。
- 如請求項1之電子零件模組,其中,上述導電膜之端部係不露出而由上述保護膜覆蓋。
- 一種電子零件模組,其特徵在於具備:安裝基板;搭載於上述安裝基板之表面的電子零件;以埋覆上述電子零件的方式形成於上述安裝基板之上述表面的密封樹脂;覆蓋上述密封樹脂之表面及上述安裝基板之側面的導電膜;與覆蓋上述導電膜的保護膜;上述保護膜係具有使保護層與低反射層依序積層的構成;上述低反射層之光反射率為20%以下;上述導電膜的端部係不露出而由上述保護膜覆蓋。
- 如請求項4之電子零件模組,其中,上述導電膜之端部係位於上述安裝基板之上述側面。
- 如請求項4之電子零件模組,其中,上述導電膜之端部係位於上述安裝基板之背面。
- 如請求項4之電子零件模組,其中,上述低反射層係不與上述導電膜相接。
- 一種電子零件模組之製造方法,其特徵在於包括:對在表面形成有電子零件及覆蓋上述電子零件之密封樹脂的安裝基板的背面,以第一遮罩膠帶覆蓋的步驟;依藉由上述第一遮罩膠帶覆蓋上述安裝基板之上述背面的狀態,於上述密封樹脂之表面及上述安裝基板之側面形成導電膜的步驟;在形成上述導電膜後剝除上述第一遮罩膠帶的步驟;藉由較上述安裝基板小的第二遮罩膠帶覆蓋上述安裝基板之背面的步驟;依藉由上述第二遮罩膠帶覆蓋上述安裝基板之上述背面的狀態,於上述導電膜上形成保護膜的步驟;與將上述保護膜之表面加工為低反射層的步驟。
- 如請求項8之電子零件模組之製造方法,其中,上述加工為低反射層的步驟係藉由對上述保護膜之上述表面進行蝕刻而進行。
- 如請求項8之電子零件模組之製造方法,其中,上述加工為低反射層的步驟係藉由在上述保護膜之上述表面實施非電解鍍覆而進行。
- 如請求項8之電子零件模組之製造方法,其中,上述第一遮罩膠帶係覆蓋上述安裝基板之上述背面的整面。
- 如請求項11之電子零件模組之製造方法,其中,上述第二遮罩膠帶係不覆蓋上述導電膜之端部而覆蓋上述安裝基板之上述背面。
- 如請求項12之電子零件模組之製造方法,其中,上述第二遮罩膠帶係覆蓋上述安裝基板之上述背面的整面。
- 如請求項12之電子零件模組之製造方法,其中,上述安裝基板之上述背面係包含最外周部分及由上述最外周部分包圍的中心部分;上述第二遮罩膠帶係不覆蓋上述最外周部分而覆蓋上述中心部分。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662412371P | 2016-10-25 | 2016-10-25 | |
US62/412371 | 2016-10-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201830610A TW201830610A (zh) | 2018-08-16 |
TWI668821B true TWI668821B (zh) | 2019-08-11 |
Family
ID=61970438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106136342A TWI668821B (zh) | 2016-10-25 | 2017-10-23 | 電子零件模組及其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10304779B2 (zh) |
CN (2) | CN107978589A (zh) |
TW (1) | TWI668821B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6512298B2 (ja) * | 2015-08-11 | 2019-05-15 | 株式会社村田製作所 | 高周波モジュールおよびその製造方法 |
WO2023090335A1 (ja) * | 2021-11-19 | 2023-05-25 | Agc株式会社 | 透明電子デバイス、合わせガラス、及び透明電子デバイスの製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201605010A (zh) * | 2014-07-25 | 2016-02-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3406817B2 (ja) * | 1997-11-28 | 2003-05-19 | 株式会社東芝 | 金属層へのマーク付け方法および半導体装置 |
JP3937945B2 (ja) * | 2002-07-04 | 2007-06-27 | セイコーエプソン株式会社 | 表示装置及びこれを備えた電子機器 |
JP2004119726A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP4052915B2 (ja) * | 2002-09-26 | 2008-02-27 | 三洋電機株式会社 | 回路装置の製造方法 |
JP4665631B2 (ja) * | 2005-07-07 | 2011-04-06 | セイコーエプソン株式会社 | 電子基板とその製造方法及び電気光学装置の製造方法並びに電子機器の製造方法 |
JP5169071B2 (ja) * | 2007-08-21 | 2013-03-27 | セイコーエプソン株式会社 | 電子部品、電子装置、電子部品の実装構造体及び電子部品の実装構造体の製造方法 |
JP4317245B2 (ja) * | 2007-09-27 | 2009-08-19 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
JP2012151326A (ja) | 2011-01-20 | 2012-08-09 | Toshiba Corp | 半導体装置の製造方法、半導体装置及び電子部品のシールド方法 |
JP5779227B2 (ja) * | 2013-03-22 | 2015-09-16 | 株式会社東芝 | 半導体装置の製造方法 |
US9269673B1 (en) * | 2014-10-22 | 2016-02-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages |
KR20160093403A (ko) * | 2015-01-29 | 2016-08-08 | 엘지이노텍 주식회사 | 전자파차폐구조물 |
-
2017
- 2017-10-23 TW TW106136342A patent/TWI668821B/zh active
- 2017-10-24 US US15/791,888 patent/US10304779B2/en active Active
- 2017-10-25 CN CN201711008406.4A patent/CN107978589A/zh active Pending
- 2017-10-25 CN CN202010781491.3A patent/CN111785705A/zh active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201605010A (zh) * | 2014-07-25 | 2016-02-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
Also Published As
Publication number | Publication date |
---|---|
CN107978589A (zh) | 2018-05-01 |
CN111785705A (zh) | 2020-10-16 |
TW201830610A (zh) | 2018-08-16 |
US20180114759A1 (en) | 2018-04-26 |
US10304779B2 (en) | 2019-05-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100543481B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP5485110B2 (ja) | 配線基板及びその製造方法、電子装置 | |
TWI235439B (en) | Wiring structure on semiconductor substrate and method of fabricating the same | |
KR100841499B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR100659625B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4743631B2 (ja) | 半導体装置及びその製造方法 | |
US9760754B2 (en) | Printed circuit board assembly forming enhanced fingerprint module | |
EP1450400A1 (en) | Module part | |
TWI383717B (zh) | 印刷電路板製造方法及由此製造之印刷電路板 | |
TW201533860A (zh) | 配線基板及使用其之半導體裝置 | |
US10217711B2 (en) | Semiconductor package and manufacturing method thereof | |
TWI668821B (zh) | 電子零件模組及其製造方法 | |
JPWO2019181761A1 (ja) | 高周波モジュール | |
TW200816407A (en) | Window manufacture method of semiconductor package type printed circuit board | |
JP2014504034A (ja) | リードクラックが強化された電子素子用テープ | |
JP2010016395A5 (zh) | ||
JPH06105827B2 (ja) | プリント配線板 | |
JP4401330B2 (ja) | 半導体装置及びその製造方法 | |
KR20030013288A (ko) | 수지봉지형 반도체장치 | |
US6420207B1 (en) | Semiconductor package and enhanced FBG manufacturing | |
TWI608776B (zh) | 軟性電路板的製作方法 | |
CN100470781C (zh) | 半导体装置及其制造方法 | |
JP2002313930A (ja) | 半導体装置およびその製造方法 | |
CN108666293B (zh) | 线路载板及其制造方法 | |
JP6901201B2 (ja) | 半導体素子搭載用基板及びその製造方法 |