CN103915408A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103915408A
CN103915408A CN201310024271.6A CN201310024271A CN103915408A CN 103915408 A CN103915408 A CN 103915408A CN 201310024271 A CN201310024271 A CN 201310024271A CN 103915408 A CN103915408 A CN 103915408A
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CN
China
Prior art keywords
substrate body
conduction
semiconductor package
metal level
perforation
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CN201310024271.6A
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English (en)
Inventor
黄富堂
柯俊吉
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103915408A publication Critical patent/CN103915408A/zh
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：承载件，其具有接置区及至少一接地垫；基板本体，其具有多个导电穿孔及相对的第一表面与第二表面，各该导电穿孔具有对应该第一表面与第二表面的第一端部及第二端部，该导电穿孔的第一端部外露于该基板本体的第一表面，该基板本体并以该第二表面设置于该承载件的接置区上；金属层，其形成于该基板本体的第一表面上，并外露出该导电穿孔的第一端部；导电体，其电性连接该金属层与该承载件的接地垫；以及半导体组件，其设置于该基板本体上，并电性连接该导电穿孔的第一端部。由此，本发明具有电磁干扰屏蔽的效果，以避免该基板本体与该半导体组件所产生的电磁波或电性信号互相干扰。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，特别是指一种具有电磁干扰屏蔽的半导体封装件及其制法。
背景技术
随着半导体的技术不断地增长，愈来愈多的电子组件可以整合在一个半导体封装件内，且随着电子产品的轻薄短小的趋势，半导体封装件的体积也愈来愈小，因而发展出立体(3D)封装的技术，也就是将多个芯片安装在同一半导体封装件中。
同时，为了达到该些芯片互相堆栈的需求，因而发展出所谓的硅穿孔(Through Silicon Vias;TSV)的技术，也就是在硅基板中形成多个贯穿孔。由此，可提高该半导体封装件的处理速度，并大幅降低功率的损耗。
但是，当该些芯片中含有射频(RF)芯片或通讯芯片时，该些芯片之间容易发生电磁波或电性信号互相干扰的问题。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺点，本发明的主要目的在于提供一种半导体封装件及其制法，具有电磁干扰屏蔽(EMI shielding)的效果，以避免该基板本体与该半导体组件所产生的电磁波或电性信号互相干扰。
本发明的半导体封装件，其包括：承载件，其具有接置区及至少一接地垫；基板本体，其具有多个导电穿孔及相对的第一表面与第二表面，各该导电穿孔具有对应该第一表面与第二表面的第一端部及第二端部，该导电穿孔的第一端部外露于该基板本体的第一表面，该基板本体并以该第二表面设置于该承载件的接置区上；金属层，其形成于该基板本体的第一表面上，并外露出该导电穿孔的第一端部；导电体，其电性连接该金属层与该承载件的接地垫；以及半导体组件，其设置于该基板本体上，并电性连接该导电穿孔的第一端部。
本发明也提供一种半导体封装件的制法，其包括：提供一具有多个导电穿孔及相对的第一表面与第二表面的基板本体，各该导电穿孔具有对应该第一表面与第二表面的第一端部及第二端部，该导电穿孔的第一端部外露于该基板本体的第一表面；于该基板本体的第一表面上形成一金属层，该导电穿孔的第一端部外露于该金属层；将该基板本体以其第二表面设置于一具有至少一接地垫的承载件上；以及电性连接半导体组件与该导电穿孔的第一端部，并通过至少一导电体电性连接该金属层与该承载件的至少一接地垫。
由上可知，本发明的半导体封装件及其制法，主要是在基板本体的第一表面上形成金属层，并将该基板本体设置于具有接地垫的承载件上，再通过导电体电性连接该金属层与该接地垫。由此，本发明能具有电磁干扰屏蔽(EMI  shielding)的效果，以避免该基板本体与该半导体组件所产生的电磁波或电性信号互相干扰。
附图说明
图1A至图1K为绘示本发明的第一实施例中半导体封装件及其制法的剖视示意图。
图1H’为绘示本发明图1H的俯视示意图。
图1I’为绘示本发明图1I的俯视示意图。
图1J’为绘示本发明图1J于另一实施例的俯视示意图。
图2A至图2C为绘示本发明的第二实施例中半导体封装件及其制法的部分剖视示意图。
符号说明
1            半导体封装件
10           基板本体
10a          第一表面
10b       第二表面
101       导电穿孔
102       第一端部
103       第二端部
104       侧面
11        绝缘层
12        导电材
13        金属层
131       开孔
14        粘着层
141       承载件
15        导电凸块
16        底胶
161       侧边
162       底胶
17        承载件
17a       顶面
17b       底面
171       第一接地垫
172       第二接地垫
173       导电穿孔
174       接置区
18        导电体
19        半导体组件
191       导电组件
20        封装胶体
AA       切割线。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“一”、“第一”、“第二”、“表面”及“端部”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图1A至图1K为绘示本发明的第一实施例中半导体封装件及其制法的剖视示意图，图1H’为绘示本发明图1H的俯视示意图，图1I’为绘示本发明图1I的俯视示意图，图1J’为绘示本发明图1J于另一实施例的俯视示意图。
如图1A所示，提供一具有多个导电穿孔101及相对的第一表面10a与第二表面10b的基板本体10，各该导电穿孔101具有对应该第一表面10a与该第二表面10b的第一端部102及第二端部103，且该导电穿孔101的第一端部102外露于该基板本体10的第一表面10a。该导电穿孔101可为硅穿孔(TSV)或贯穿孔(vias)等，该基板本体10可为硅基板、中介板(interposer)或具有硅穿孔的芯片等。
如图1B所示，形成绝缘层11于该基板本体10的第一表面10a上，且该绝缘层11外露出该导电穿孔101的第一端部102。继而，形成多个导电材12于该导电穿孔101的第一端部102上。该绝缘层11可为保护层(passivation layer)等，该导电材12可为金属材料等。
如图1C所示，形成金属层13于该基板本体10的第一表面10a的绝缘层11上。该金属层13具有多个开孔131，以外露出该导电穿孔101的第一端部102的导电材12。同时，该导电材12与该金属层13之间具有间隙，以避免该导电材12接触该金属层13而接地。该金属层13可为铜层等。
如图1D所示，形成粘着层14于该金属层13上，且该粘着层14包覆该导电材12及该开孔131。接着，设置承载件141于该粘着层14上。
如图1E所示，利用研磨、切割或其它方式，自该第二表面10b薄化该基板本体10的厚度，以外露出该导电穿孔101的第二端部103。然后，自该第二表面10b形成多个导电凸块15于该导电穿孔101的外露第二端部103上。
如图1F所示，分别移除该承载件141及该粘着层14，以外露出该导电材12、金属层13与开孔131。
如图1G所示，沿着图1F的切割线AA一并切割该基板本体10、绝缘层11及金属层13，以将该基板本体10、绝缘层11、导电材12、金属层13及导电凸块15所形成的结构分离为多个结构体。
如图1H及图1H’所示，先将该基板本体10以其第二表面10b接置于承载件17的接置区174上，并通过该导电凸块15电性连接该导电穿孔101的第二端部103与该承载件17，再形成底胶16于该基板本体10的第二表面10b与该承载件17的接置区174间。或者，先形成底胶16于该承载件17的顶面17a上，并将该基板本体10以其第二表面10b接置于该承载件17的接置区174上，再通过该导电凸块15电性连接该导电穿孔101的第二端部103与该承载件17。
在本实施例中，该承载件17具有至少一第一接地垫171、第二接地垫172、导电穿孔173及相对的顶面17a与底面17b。该第一接地垫171与第二接地垫172分别形成于该顶面17a及该底面17b上，该导电穿孔173形成于该承载件17的内部、或贯穿该顶面17a与底面17b，并电性连接该第一接地垫171及该第二接地垫172。
如图1I及图1I’所示，通过至少一导电体18电性连接该金属层13与该承载件17的第一接地垫171。该导电体18可为导电胶，自该金属层13沿着该基板本体10的侧面104及该底胶16的侧边161延伸至该承载件17的第一接地垫171。
如图1J所示，形成多个导电组件191于半导体组件19、或外露于该金属层13的多个开孔131中的该导电材12上。接着，以覆晶方式将该半导体组件19接置于该基板本体10的第一表面10a上，而令该半导体组件19位于该金属层13的上方，以通过该导电组件191电性连接该半导体组件19与外露于该开孔131中的导电材12。该导电组件191可为导电凸块，该半导体组件19可为半导体芯片、射频(RF)芯片或通讯芯片等。
如图1J’所示，该半导体组件19与该金属层13之间也可形成底胶162，用以包覆该导电组件191及该开孔131。
如图1K所示，自图1J(或图1J’)中，形成封装胶体20于该承载件17的顶面17a上，以包覆该基板本体10、绝缘层11、导电材12、金属层13、导电体18与半导体组件19。
图2A至图2C为绘示本发明的第二实施例中半导体封装件及其制法的部分剖视示意图。第二实施例与上述第一实施例的半导体封装件1的制法大致相同，其主要差异详如下述：
如图2A所示，以覆晶方式将半导体组件19接置于基板本体10的第一表面10a上，而令该半导体组件19位于金属层13的上方，并通过多个导电组件191电性连接该半导体组件19与外露于该金属层13的多个开孔131中的导电材12。
如图2B所示，通过至少一导电体18电性连接该金属层13与承载件17的至少一第一接地垫171。该导电体18可为导电胶，其自该金属层13沿着基板本体10的侧面104及底胶16的侧边161延伸至该承载件17的至少一第一接地垫171。
如图2C所示，形成封装胶体20于该承载件17的顶面17a上，以包覆该基板本体10、绝缘层11、导电材12、金属层13、导电体18与半导体组件19。
关于第二实施例的半导体封装件1的其余制法，则同于上述第一实施例的图1A至图1H’所示者，故不再重还赘述。
本发明另提供一种半导体封装件1，如图1K所示，该半导体封装件1包括承载件17、基板本体10、金属层13、导电体18、半导体组件19以及封装胶体20。
该承载件17具有至少一导电穿孔173、相对的顶面17a与底面17b，该顶面17a上定义有接置区174并具有形成于该接置区174外的至少一第一接地垫171，且该底面17b具有至少一第二接地垫172。
该基板本体10具有多个导电穿孔101及相对的第一表面10a与第二表面10b，各该导电穿孔101具有对应该第一表面10a与第二表面10b的第一端部102及第二端部103，该导电穿孔101的第一端部102外露于该基板本体10的第一表面10a。
该基板本体10藉其第二表面10b设置于该承载件17的接置区174上。该基板本体10可为硅基板、中介板或具有硅穿孔的芯片等，该导电穿孔101可为硅穿孔或贯穿孔等。
该金属层13形成于该基板本体10的第一表面10a上，并外露出该导电穿孔101的第一端部102。该金属层13可为铜层等。
该导电体18用以电性连接该金属层13与该承载件17的第一接地垫171。
该半导体组件19以覆晶方式设置于该金属层13的上方，并电性连接该导电穿孔101的第一端部102。该半导体组件19可为半导体芯片、射频芯片或通讯芯片等。
该封装胶体20形成于该承载件17的顶面17a上，以包覆该基板本体10、金属层13、导电体18与半导体组件19。
该半导体封装件1可包括绝缘层11，形成于该基板本体10的第一表面10a与该金属层13之间，并外露出该导电穿孔101的第一端部102。该绝缘层11可为保护层等。
该半导体封装件1可包括导电材12，形成于该导电穿孔101的第一端部102上。该导电材12可为金属材料等。
上述的金属层13可具有多个开孔131，以外露出该导电材12，以使该导电材12与该金属层13之间形成有间隙，故能避免该导电材12接触该金属层13而接地。
该半导体封装件1可包括多个导电凸块15，该导电穿孔101贯穿该基板本体10的第一表面10a与第二表面10b，以供该导电凸块15分别形成于该导电穿孔101的第二端部103上。
该半导体封装件1可包括底胶16，其形成于该承载件17的顶面17a上，用以包覆该导电凸块15。上述的承载件17并电性连接该导电凸块15的外露部分。
上述的导电体18可为导电胶，其自该金属层13沿着该基板本体10的侧面104及该底胶16的侧边161延伸至该承载件17的第一接地垫171。
该半导体封装件1可包括多个导电组件191，形成于该半导体组件19、或外露于该开孔131中的导电材12上，以电性连接该半导体组件19与该导电材12。该导电组件191可为导电凸块。
由上可知，本发明的半导体封装件及其制法，主要是在基板本体的第一表面上形成金属层(如铜层)，并在该基板本体的第二表面上设置具有接地垫的承载件，再通过导电体(如导电胶)电性连接该金属层与该接地垫。由此，本发明能具有电磁干扰屏蔽的效果，以避免半导体组件(如射频芯片)与基板本体(如另一芯片)所产生的电磁波或电性信号互相干扰。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种半导体封装件，其包括：
承载件，其具有接置区及至少一接地垫；
基板本体，其具有多个导电穿孔及相对的第一表面与第二表面，各该导电穿孔具有对应该第一表面与第二表面的第一端部及第二端部，且该导电穿孔的第一端部外露于该基板本体的第一表面，该基板本体并以该第二表面设置于该承载件的接置区上；
金属层，其形成于该基板本体的第一表面上，并外露出该导电穿孔的第一端部；
导电体，其电性连接该金属层与该承载件的至少一接地垫；以及
半导体组件，其设置于该基板本体上，并电性连接该导电穿孔的第一端部。
2.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括绝缘层，其形成于该基板本体的第一表面与该金属层之间，并外露出该导电穿孔的第一端部。
3.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括多个导电材，其形成于该导电穿孔的第一端部上。
4.根据权利要求3所述的半导体封装件，其特征在于，该金属层具有多个开孔，以外露出该导电材，以使该导电材与该金属层之间形成有间隙。
5.根据权利要求1所述的半导体封装件，其特征在于，该导电穿孔贯穿该基板本体的第一表面与第二表面，且该半导体封装件还包括多个导电凸块，其分别形成于该导电穿孔的第二端部上。
6.根据权利要求1所述的半导体封装件，其特征在于，该导电体为导电胶，其自该金属层沿着该基板本体的侧面延伸至该承载件的接地垫。
7.根据权利要求1所述的半导体封装件，其特征在于，该至少一接地垫形成于该接置区外。
8.根据权利要求1所述的半导体封装件，其特征在于还包括封装胶体，其形成于该承载件上，用以包覆该基板本体、金属层、导电体及半导体组件。
9.一种半导体封装件的制法，其包括：
提供一具有多个导电穿孔及相对的第一表面与第二表面的基板本体，各该导电穿孔具有对应该第一表面与该第二表面的第一端部及第二端部，该导电穿孔的第一端部外露于该基板本体的第一表面；
于该基板本体的第一表面上形成一金属层，该导电穿孔的第一端部外露于该金属层；
将该基板本体以其第二表面设置于具有至少一接地垫的承载件上；以及
电性连接半导体组件与该导电穿孔的第一端部，并通过至少一导电体电性连接该金属层与该承载件的至少一接地垫。
10.根据权利要求9所述的半导体封装件的制法，其特征在于，具有该金属层的基板本体的制备包括：
形成绝缘层于该基板本体的第一表面上，且该绝缘层外露出该导电穿孔的第一端部；
形成多个导电材于该导电穿孔的第一端部上；以及
形成该金属层于该绝缘层上，且该金属层具有多个开孔以外露出该导电材。
11.根据权利要求9所述的半导体封装件的制法，其特征在于，该导电体为导电胶，其自该金属层沿着该基板本体的侧面延伸至该承载件的接地垫。
12.根据权利要求9所述的半导体封装件的制法，其特征在于还包括自该第二表面薄化该基板本体的厚度，以外露出该导电穿孔的第二端部。
13.根据权利要求9所述的半导体封装件的制法，其特征在于，其先通过该导电体电性连接该金属层与该承载件的接地垫，再于该基板本体的第一表面侧电性连接该半导体组件。
14.根据权利要求9所述的半导体封装件的制法，其特征在于，先于该基板本体的第一表面侧电性连接该半导体组件，再通过该导电体电性连接该金属层与该承载件的接地垫。
15.根据权利要求9所述的半导体封装件的制法，其特征在于，该制法还包括形成封装胶体于该承载件上，以包覆该基板本体、金属层、导电体及半导体组件。
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