CN102024802A - 集成电路结构及其形成方法 - Google Patents

集成电路结构及其形成方法 Download PDF

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Publication number
CN102024802A
CN102024802A CN2010102822746A CN201010282274A CN102024802A CN 102024802 A CN102024802 A CN 102024802A CN 2010102822746 A CN2010102822746 A CN 2010102822746A CN 201010282274 A CN201010282274 A CN 201010282274A CN 102024802 A CN102024802 A CN 102024802A
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Prior art keywords
nude film
moulding compound
integrated circuit
circuit structure
film
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CN102024802B (zh
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李柏毅
王宗鼎
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供集成电路结构及其形成方法，该结构包含第一裸片，其包含穿透基底的导孔；第二裸片粘合至第一裸片之上，第一裸片具有一表面，面对第二裸片；以及模塑料，其包含一部分在第一裸片与第二裸片之上。模塑料接触第二裸片的表面，此外，模塑料包含一部分延伸至第二裸片的表面下方。本发明具有许多优点，借由让模塑料延伸至硅穿孔裸片面对顶端裸片的表面下方，可以降低在裸片切割工艺中发生脱层与裂开的可能性，因此可改善所产生的封装组件的可靠度。

Description

集成电路结构及其形成方法
技术领域
本发明涉及集成电路，特别涉及堆叠裸片的方法，且更涉及包含堆叠裸片的封装组件以及其封装方法。
背景技术
由于各种电子元件，例如晶体管、二极管、电阻器、电容器等在集成密度上的持续改进，集成电路的制造以及半导体工业已经持续快速地成长。在集成密度上的改进大多数来自于最小特征尺寸的重复缩减，其可以让更多的元件被整合在特定的面积内。
这些在集成密度上的改进原本是二维(two-dimensional：2D)的，其中集成元件占据的体积实质上是在半导体晶片的表面上。虽然在光刻技术上显著的改进已经对于二维集成电路的形成产生相当大的改进，但是在二维尺度上可以达到的集成密度仍然有其物理上的限制。这些限制之一为制造这些元件所需的最小尺寸，并且当更多的装置(device)被放置在一个芯片内时，需要更复杂的设计。
另一额外的限制来自于随着装置数量的增加，装置之间的内连线长度与数量也显著地增加。当内连线的长度与数量增加时，电路的RC延迟以及功率消耗都会增加。
目前解决上述限制的方式，通常是使用三维集成电路(3D ICs)以及堆叠的裸片，在三维集成电路与堆叠的裸片中常使用硅穿孔(through-silicon vias；TSVs)来连接裸片，在此例中，使用硅穿孔连接一个裸片上的集成电路至此裸片的背面。此外，硅穿孔也可提供较短的接地路径，以连接集成电路中的接地至此裸片的背面，其通常被接地的铝膜覆盖住。因此，需要寻求可以对于含有TSVs的裸片的堆叠提升品质的方法。
发明内容
为克服上述现有技术的缺陷，依据一实施例，集成电路结构包含第一裸片，其包含至少一个硅穿孔(TSV)；第二裸片粘合至第一裸片之上，第一裸片具有面对第二裸片的一表面；以及模塑料，其包含一部分在第一裸片与第二裸片之上。模塑料接触第二裸片的一表面，此外，模塑料包含一部分延伸至第二裸片的表面下方。
依据另一实施例，一种集成电路结构的形成方法，包括：提供一底部裸片，包括多个穿透基底导孔；将一顶端裸片接合至该底部裸片之上，其中该底部裸片包括一表面，面对该顶端裸片；以及在该底部裸片与该顶端裸片上塑造一模塑料，其中该模塑料接触该顶端裸片及该底部裸片表面的该表面，且其中该模塑料包括一部分延伸至该底部裸片且包覆住该底部裸片的侧边。其他实施例也揭示如下。
本发明实施例具有许多优点，借由让模塑料延伸至硅穿孔裸片面对顶端裸片的表面下方，可以降低在裸片切割工艺中发生脱层与裂开的可能性，因此可改善所产生的封装组件的可靠度。
为了让本发明之上述目的、特征、及优点能更明显易懂，以下配合附图，作详细说明如下：
附图说明
图1A至图8为依据一实施例，制造封装组件的各中间阶段的剖面示意图与透视图，其中裸片的重分布线与凸块在此裸片粘合至另一裸片之前形成；以及
图9A至图17为依据另一实施例，制造封装组件的各中间阶段的剖面示意图与透视图，其中裸片的重分布线与凸块在此裸片粘合至另一裸片之后形成。
其中，附图标记说明如下：
4～载体；6～接着材料；10～硅穿孔裸片；12～重分布线；14～凸块；16～硅穿孔；20～顶端裸片；22、38～底部填胶；24～模塑料；25～切口线；26～切割胶带；27～硅穿孔裸片的边缘；28～切割框架；29～顶端裸片的边缘；30～晶片级模塑单元；32～硅穿孔裸片面对顶端裸片的表面；36～封装基底；40～锡球。
具体实施方式
以下详述各实施例的制造与使用，然而，可以理解的是，这些实施例提供许多可应用的发明概念，其可以在各种不同的特定背景中实施，在此所讨论的特定实施例仅用于说明实施例的制造与使用的特定方式，并非用以限定实施例的范围。
以下提出新的封装组件，包括具有硅穿孔(TSVs)(也可以是穿透半导体的导孔(through-semiconductor vias)或穿透基底的导孔(through-substrate vias))的裸片(die)，以及其形成方法。在此说明制造一实施例的各中间阶段，然后讨论实施例的各种变化。在全部的说明实施例与各种示意图中，使用相似的标号来标示相似的元件。
图1A与图1B分别显示依据一实施例，最初阶段的透视图与剖面示意图。首先提供载体(carrier)4，并且在载体4的一侧施加接着材料(mountingmaterial)6，使得接着材料6具有平坦的表面。接着材料6可以用液态形式施加至载体4上，然后进行固化。在一实施例中，接着材料6于后续的工艺步骤中移除，并且接着材料6可包括可重复使用的材料，例如蜡(wax)、粘着剂(胶)、b阶材料(b-stage materials)以及类似的材料。将可重复使用的材料从载体4移除之后，收集可重复使用的材料，并且可以将此材料重复使用在其他载体上，因此，接着材料6也称为可重复使用的材料6。
硅穿孔(TSV)裸片10被固定在接着材料6上，其包括硅穿孔(TSVs)16在其中。在一实施例中，将硅穿孔裸片10固定在接着材料6上之前，在硅穿孔裸片10的正面上(正面为图1B中所示的朝下的面)预先形成重分布线(redistribution lines；RDLs)12与凸块(bump)14(如图1B所示)，硅穿孔16则在硅穿孔裸片10的半导体基底(未绘出)例如硅基底中形成。在一实施例中，如图1B所示，硅穿孔16穿透半导体基底，且突出于硅穿孔裸片10的背面(背面为图1B中所示的朝上的面)，成为含有铜的凸块形状，例如为铜垫(copperpost)。在另一实施例中，硅穿孔16连接至接合垫(bond pad)(未绘出)，接合垫形成于硅穿孔裸片10的背面上。
参阅图2A与图2B，将顶端裸片(top die)20粘合至硅穿孔裸片10上，例如经由覆晶接合(flip-chip bonding)的方式。顶端裸片20中的电路电性连接至硅穿孔裸片10中的硅穿孔16，顶端裸片20与硅穿孔裸片10可包含集成电路(未绘出)在其中，例如为互补式金属氧化物半导体(CMOS)晶体管，顶端裸片20的尺寸可小于或等于硅穿孔裸片10的尺寸。在图3中，底部填胶(underfill)22涂布在顶端裸片20与硅穿孔裸片10之间的空间内，以保护此接合结构，然后将底部填胶22固化。
参阅图4A与图4B，其分别显示相同结构的透视图与剖面示意图，在此进行晶片级的塑模工艺(wafer-level molding)，并且将模塑料(moldingcompound)24塑造成覆盖顶端裸片20与硅穿孔裸片10。于固化之后所产生的模塑料24具有平坦的顶部表面，模塑料24可保护堆叠结构，并且在最终结构中留下，因此，模塑料24可使用常用的塑模材料，例如树脂。图4B显示模塑料24填充在硅穿孔裸片10与接触的接着材料6之间的空间内，模塑料24的底部表面大抵上也可与硅穿孔裸片10的底部表面齐平，因此，顶端裸片20可借由模塑料24而彼此互相分开，并且硅穿孔裸片10也可借由模塑料24而彼此互相分开。
图5显示将切割胶带(dicing tape)26固定至模塑料24上，切割胶带26可包含切割框架(dicing frame)28在其中，于固定切割胶带之后，切割胶带26粘着至模塑料24上。接着。如图6A与图6B所示，其分别显示透视图与剖面示意图，经由移除接着材料6，载体4从模塑料24脱离(de-bonded)，取决于接着材料6所使用的材料，此移除步骤可使用水或其他溶剂进行。在接着材料6可重复使用的实施例中，如图6A与图6B所示的步骤进行之后，可以将被移除的可重复使用材料6收集并且再利用。在可重复使用的材料被再利用的过程中，重复进行如第1及5图所示的工艺步骤，以接合其他的顶端裸片至其他的硅穿孔裸片，并且可以将收集到的可重复使用材料6应用在与载体4类似的其他载体上，形成另一接着材料6，其与图2所示的接着材料相似。在其他实施例中，载体4可经由紫外光胶(UV glue)与硅穿孔裸片10粘接，并且可借由将紫外光胶暴露在紫外光下而脱离载体4。
接着，对图6A与图6B所示的结构进行裸片切割，所产生的一个堆叠裸片(之后称为晶片级模塑单元(wafer-level molding unit)30)的剖面示意图如图7所示。于裸片切割时，切口线(kerf lines)25与硅穿孔裸片的边缘27以及顶端裸片20的边缘29相隔一段距离，在所产生的晶片级模塑单元30中，顶端裸片20与硅穿孔裸片10都被模塑料24覆盖，并且硅穿孔裸片的边缘27与顶端裸片20的边缘29也被模塑料24覆盖。由于模塑料24延伸至表面32(硅穿孔裸片10的背面，面对顶端裸片20)下方，因此在切割堆叠结构的期间，会降低可能发生的脱层现象，并且也会改善所产生的封装组件的可靠度测试结果。
参阅图8，经由凸块14将晶片级模塑单元30接合至封装基底36上。在其他实施例中，晶片级模塑单元30可经由导线接合(wire bonding)(未绘出)的方式接合至封装基底36上。在晶片级模塑单元30与封装基底36之间也涂布底部填胶38，此外，球栅阵列型(ball-grid-array；BGA)球体40，其为锡球(solder ball)，也可以固定至封装基底36上。
图9A至图17显示另一实施例，在此实施例中，重分布线(RDLs)12与凸块14(参阅图15)在载体4脱离之后形成，以取代其在硅穿孔裸片10固定至接着材料6之前的预先形成工艺。除非特别指明，在此实施例中所使用的相似标号代表上述实施例中所使用的相似元件，此实施例的材料与详细工艺也可参照图1A至图8所示的实施例。参阅图9A与图9B，其分别显示相同结构的透视图与剖面示意图，硅穿孔裸片10固定至接着材料6上，接着材料6更进一步施加在载体4上，在硅穿孔裸片10的正面(正面为图9B中所示的朝下的面)上无重分布线(RDLs)与凸块形成。
图10A至图15所示的工艺步骤实质上与图2至图6所示的工艺步骤相同，在图10A与图10B中，顶端裸片20粘合至硅穿孔裸片10上。然后，如图11A与图11B所示，将底部填胶22涂布至顶端裸片20与硅穿孔裸片10之间。参阅图12A与图12B，进行晶片级模塑步骤，以模塑料24覆盖顶端裸片20与硅穿孔裸片10。在图13中，将切割胶带26固定至模塑料24上，接着，如图14A与图14B所示，进行载体4的脱离步骤。
接着，如图15所示，形成重分布线(RDLs)12与凸块14，重分布线(RDLs)12与凸块14的详细形成方式为公知，在此不予以讨论。接着，在图15所示的结构上进行裸片切割，并且所产生的一个晶片级模塑单元30如图16所示。再次地，切口线与顶端裸片20与硅穿孔裸片10的边缘相隔一段距离，因此顶端裸片20与硅穿孔裸片10的边缘不会暴露出来。图17显示将晶片级模塑单元30粘合至封装基底36上。
上述实施例具有许多优点，借由让模塑料延伸至硅穿孔裸片10面对顶端裸片20的表面下方，可以降低在裸片切割工艺中发生脱层与裂开的可能性，因此可改善所产生的封装组件的可靠度。
虽然本发明已揭示优选实施例如上，然而其并非用以限定本发明，本领域技术人员当可了解，在不脱离本发明的精神和范围内，当可做些许更动与润饰。因此，本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (10)

1.一种集成电路结构，包括：
一第一裸片，包括至少一个穿透基底导孔；
一第二裸片，接合于该第一裸片之上，其中该第一裸片包括一第一表面，面对该第二裸片；以及
一模塑料，包括一部分在该第一裸片与该第二裸片之上，其中该模塑料接触该第一裸片的该第一表面，且其中该模塑料包括一第一部分延伸至该第一裸片的该第一表面下方。
2.如权利要求1所述的集成电路结构，还包括一封装基底接合至该第一裸片底下。
3.如权利要求1所述的集成电路结构，其中该模塑料还包括一第二部分直接在该第一裸片之上，且其中该第一部分与该第二部分由一相同材料形成。
4.如权利要求1所述的集成电路结构，其中该第二裸片接合至该第一裸片中的该穿透基底导孔。
5.如权利要求1所述的集成电路结构，其中该模塑料包括一底部表面与该第一裸片的一第二表面齐平，且其中该第一裸片的该第二表面与该第一裸片的该第一表面为相反侧。
6.如权利要求1所述的集成电路结构，其中该第二裸片的尺寸小于该第一裸片。
7.一种集成电路结构的形成方法，包括：
提供一底部裸片，包括多个穿透基底导孔；
将一顶端裸片接合至该底部裸片之上，其中该底部裸片包括一表面，面对该顶端裸片；以及
在该底部裸片与该顶端裸片上塑造一模塑料，其中该模塑料接触该顶端裸片及该底部裸片表面的该表面，且其中该模塑料包括一部分延伸至该底部裸片且包覆住该底部裸片的侧边。
8.如权利要求7所述的集成电路结构的形成方法，于接合该顶端裸片至该底部裸片之上的该步骤之前，还包括：
将一液态形式的接着材料固定至一载体上；
固化该接着材料；以及
将该底部裸片放置在该接着材料上。
9.如权利要求7所述的集成电路结构的形成方法，还包括：
将一切割胶带固定至该模塑料上；
移除该接着材料，使该载体与该模塑料、该顶端裸片及该底部裸片分离；以及
以切口线切割该模塑料，该切口线与该底部裸片的边缘及该顶端裸片的边缘隔开。
10.如权利要求7所述的集成电路结构的形成方法，还包括在该底部裸片上形成重分布线与凸块。
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