KR100753415B1 - 스택 패키지 - Google Patents

스택 패키지 Download PDF

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Publication number
KR100753415B1
KR100753415B1 KR20060025054A KR20060025054A KR100753415B1 KR 100753415 B1 KR100753415 B1 KR 100753415B1 KR 20060025054 A KR20060025054 A KR 20060025054A KR 20060025054 A KR20060025054 A KR 20060025054A KR 100753415 B1 KR100753415 B1 KR 100753415B1
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South Korea
Prior art keywords
semiconductor chip
solder ball
conductive pattern
pattern
circuit board
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KR20060025054A
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English (en)
Inventor
이승현
서민석
Original Assignee
주식회사 하이닉스반도체
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Priority to KR20060025054A priority Critical patent/KR100753415B1/ko
Priority to TW095149654A priority patent/TWI351092B/zh
Priority to US11/647,703 priority patent/US7598617B2/en
Priority to JP2007031205A priority patent/JP2007251145A/ja
Priority to CNB2007100877831A priority patent/CN100541789C/zh
Application granted granted Critical
Publication of KR100753415B1 publication Critical patent/KR100753415B1/ko

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Abstract

본 발명은 스택 패키지를 개시한다. 개시된 본 발명의 방법은, 인쇄회로기판; 상기 인쇄회로기판 상에 적어도 둘 이상이 스택되며, 상면에 본딩패드와 연결된 제1도전패턴을 구비하고, 가장자리 내부에 상기 제1도전패턴과 연결된 비아패턴을 구비하며, 하면에 상기 비아패턴과 연결된 제2도전패턴을 구비한 반도체 칩과, 상기 스택된 반도체칩들의 대응하는 제1도전패턴과 제2도전패턴 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제1솔더볼과, 상기 스택된 반도체칩들 중 최하부 반도체칩의 제1도전패턴과 인쇄회로기판 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제2솔더볼 및 상기 인쇄회로기판의 하면에 부착되어 실장 수단으로 기능하는 제3솔더볼을 포함하는 것을 특징으로 한다.

Description

스택 패키지{Stack Package}
도 1은 종래의 3D-스택 패키지를 도시한 단면도.
도 2a 및 2b는 본 발명의 실시예에 따른 스택 패키지의 제조 공정을 설명하기 위한 단면도.
도 3은 본 발명의 실시예에 따른 솔더 볼이 반도체 칩 전면에 부착된 모습을 설명하기 위한 도면.
* 도면의 주요 부분에 대한 부호의 설명 *
100,200,300: 반도체 칩 101,201,301: 본딩패드
102,202,302: 제1도전패턴 103,203,303: 비아패턴
104,204,304: 제2도전패턴 105,205,305: 솔더 레지스트
400,500,700: 솔더볼 600: 인쇄회로기판
본 발명은 반도체 스택 패키지에 관한 것으로서, 보다 상세하게는, 3D-스택 패키지에 관한 것이다.
전기/전자 제품의 고성능화가 진행됨에 따라, 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 많은 기술들이 제안·연구되고 있다. 그런데, 패키지는 하나의 반도체 칩이 탑재되는 것을 기본으로 하기 때문에 소망하는 용량을 얻는데 한계가 있다.
메모리 칩의 용량 증대, 즉, 고집적화를 이룰 수 있는 방법으로는 한정된 공간 내에 보다 많은 수의 셀을 제조해 넣는 기술이 일반적으로 알려져 있지만, 이와 같은 방법은 정밀한 미세 선폭을 요구하는 등, 고난도의 공정 기술과 많은 개발 시간을 필요로 한다. 따라서, 최근들어 보다 용이하게 고집적화를 이룰 수 있는 방법으로서 스택킹(stacking) 기술이 개발되었고, 이에 대한 연구가 활발히 진행되고 있다.
반도체 업계에서 말하는 스택킹이란, 적어도 2개 이상의 반도체 칩을 스택하여 메모리 용량을 배가시키는 기술이다. 이러한 스택킹 기술에 의하면, 2개의 64M DRAM급 칩을 스택하여 128M DRAM급으로 구성할 수 있고, 또한, 2개의 128M DRAM급 칩을 스택하여 256M DRAM급으로 구성할 수 있다. 게다가, 스택킹 기술에 의하면, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 잇점을 갖는다.
여기서, 3개의 반도체 칩을 스택하는 방법으로는 스택된 3개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 3개의 패키지를 스택하는 방법이 있다.
도 1은 전자의 방법에 따라 제조된 종래의 반도체 칩 스택 구조의 스택 패키지, 즉, 3D-스택 패키지를 도시한 단면도로서, 도시된 바와 같이, 칩 스택 구조의 스택 패키지는 서로 다른 크기이면서 각각 가장자리에 본딩패드(11a, 12a, 13a)를 구비한 3개의 반도체 칩(11, 12, 13)이 회로패턴(도시안됨)을 구비한 PCB(Printed Circuit Board : 14) 상에 적층되고, 각 칩(11, 12, 13)의 본딩패드들(11a, 12a, 13a)과 PCB(14)의 회로패턴이 금속와이어(15)에 의해 상호 연결되며, 반도체 칩들(11, 12, 13)과 금속와이어(15)를 포함한 PCB(14)의 상면은 봉지제(미도시)로 몰딩되고, 그리고, PCB(14)의 하부면에 외부 회로와의 전기적 접속 수단인 솔더 볼(16)이 부착된 구조를 갖는다.
그러나, 전술한 바와 같이 반도체 칩 스택 구조의 스택 패키지는 반도체 칩의 본딩패드들과 PCB의 회로패턴이 금속와이어를 이용하여 접합하기 때문에 특별한 완충제가 함유된 테이프를 사용하지 않을 경우 동일한 반도체 칩 적층이 불가능하며, 또한, 와이어(wire)로 인해 하이 스피드(high speed) 제품에 대응하기가 여러우며, 아울러, 와이어로 인해 패키지의 사이즈(size)가 증가한다.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 패키지의 사이 축소 및 하이 스피드(high speed)를 가능하게 할 수 있는 3D-스택 패키지를 제공함에 그 목적이 있다.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 인쇄회로기판; 상기 인쇄회로기판 상에 적어도 둘 이상이 스택되며, 상면에 본딩패드와 연결된 제1도전패턴을 구비하고, 가장자리 내부에 상기 제1도전패턴과 연결된 비아패턴을 구비하며, 하면에 상기 비아패턴과 연결된 제2도전패턴을 구비한 반도체 칩; 상기 스택된 반도체칩들의 대응하는 제1도전패턴과 제2도전패턴 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제1솔더볼; 상기 스택된 반도체칩들 중 최하부 반도체칩의 제1도전패턴과 인쇄회로기판 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제2솔더볼; 및 상기 인쇄회로기판의 하면에 부착되어 실장 수단으로 기능하는 제3솔더볼;을 포함하는 스택 패키지를 제공한다.
여기서, 상기 본딩패드는 비아패턴의 크기 및 비아패턴의 위치와 관계없이 반도체 칩의 전면에 형성된 것을 특징으로 한다.
상기 제1 및 제2도전패턴은 구리 인 것을 특징으로 한다.
상기 제1 및 제2도전패턴의 일부분을 제외한 기판 부분을 감싸는 솔더 레지스트를 더 포함하는 것을 특징으로 한다.
삭제
(실시예)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.
도 2a 및 도 2b는 본 발명의 실시예에 따른 스택 패키지의 제조 공정을 도시한 단면도로서, 이를 설명하면 다음과 같다.
도 2a를 참조하면, 상면에 본딩패드(101)와 연결된 제1도전패턴(102)을 구비하고, 가장자리 내부에 상기 제1도전패턴(102)과 연결된 비아패턴(103)을 구비하며, 하면에 상기 비아패턴(103)과 연결된 제2도전패턴(104)을 구비한 반도체 칩(100)을 마련한다. 이때, 상기 본딩패드(10)는 비아패턴의 크기 및 비아패턴의 위 치와 관계없이 반도체 칩의 전면에 형성되며, 상기 비아패턴(103)은 상기 반도체 칩(100)에 형성된 비아홀에 Ti, Cu 전도성 물질로 채워진 것을 의미하며, 상기 제1(102) 및 제2도전패턴(104)은 Cu로 형성된다.
여기서, 본 발명은 본딩패드(101)가 비아패턴의 크기 및 위치에 관계없이 반도체 칩(100)의 전면에 형성됨에 따라 반도체 칩에 가해지는 스트레스(stress)가 반도체 칩의 한부분에 집중되지 않고 반도체 칩의 전면에 분산되기 때문에 패키지의 신뢰성이 향상된다.
그런다음, 상기 제1(102) 및 제2도전패턴(104)의 일부분을 제외한 반도체 칩 부분을 솔더 레지스트(solder resist; 105)로 감싼다.
도 2b를 참조하면, 상기 반도체 칩(100)과 동일한 구조를 갖는 반도체 칩(200,300)이 적어도 둘 이상이 인쇄회로기판(600) 상에 스택(stack)된다.
다시말해, 상기 스택된 상기 반도체 칩(100,200,300)들의 대응하는 제1도전패턴(102,202)과 제2도전패턴(204,304) 상에 제1솔더볼(1st solder ball, 400)이 개재되어 상호간의 전기적 및 기계적 연결을 이루며, 상기 스택된 반도체 칩(100,200,300)들 중에서 최하부 반도체 칩(300)의 제1도전패턴(302)과 인쇄회로기판(600) 사이에 제2솔더볼(2nd solder ball, 500)이 개재되어 상호간의 전기적 및 기계적 연결을 이룬다.
여기서, 상기 제1솔더볼(400)과 제2솔더볼(500)은 본딩패드(101)와 비아패턴(103)의 재배열로 인해 반도체 칩(100)의 전면 상에 부착된다. 이처럼, 상기 제1솔더볼 및 제2솔더볼이 반도체 칩의 전면 상에 부착됨에 따라, 크기가 서로 다른 반도체 칩, 또는, 비아패턴의 위치가 서로 다른 반도체 칩, 또는, 스크라이브 라인(scribe line) 영역이 서로 다른 반도체 칩에 상관없이 스택 패키지를 형성할 수 있는 잇점이 있다.
그런다음, 상기 인쇄회로기판(600)의 하면에 제3솔더볼(3rd solder ball, 700)이 부착되어 실장 수단으로서 역할을 한다.
전술한 바와 같이, 본 발명은 인쇄회로기판 상에 적어도 둘 이상의 반도체 칩 스택시, 칩 간의 전기적인 연결을 위하여 와이어를 사용하지 않고, 도전패턴과 솔더볼을 사용함으로써, 이를 통해, 하이 스피드(high speed) 및 단소한 제품이 가능하다.
또한, 본 발명은 반도체 칩 스택시 추가적인 기판을 사용하지 않기 때문에 패키지의 높이를 줄일 수 있다.
아울러, 본 발명은 본딩패드와 비아패턴의 재배열로 인해 솔더볼이 비아패턴의 위치와 관계없이 반도체 칩 전면에 부착됨에 따라 크기가 서로 다른 반도체 칩, 또는, 비아패턴의 위치가 서로 다른 반도체 칩, 또는, 스크라이브 라인(scribe line) 영역이 서로 다른 반도체 칩에 상관없이 패키지를 스택할 수 있는 잇점이 있다.
게다가, 본 발명은 본딩패드가 비아패턴의 크기 및 위치에 관계없이 반도체 칩의 전면에 부착됨에 따라 반도체 칩이 받는 스트레스가 넓게 분산되므로, 이를 통해, 스택 패키지의 신뢰성을 향상시킬 수 있다.
한편, 도시하지는 않았으나, 본 발명의 실시예에서는 동일한 크기의 반도체 칩을 사용하였지만, 본 발명의 실시예에 따라 서로 다른 크기의 반도체 칩을 스택하여 스택 패키지의 제조가 가능하다.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지 만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.
이상에서와 같이, 본 발명은 반도체칩과 인쇄회로기판간을 전기적으로 연결시키기 위해 와이어를 사용하지 않고 도전패턴과 솔더볼을 사용함으로서 하이 스피드를 구현할 수 있으며, 단소한 제품이 가능하다.
또한, 본 발명은 반도체 칩 스택시 추가적인 기판을 사용하지 않기 때문에 패키지의 높이를 줄일 수 있는 효과를 볼 수 있다.
아울러, 본 발명은 본딩패드와 비아패턴의 재배열로 인해 솔더볼이 비아패턴의 위치와 관계없이 반도체 칩 전면에 부착됨에 따라 크기가 서로 다른 반도체 칩, 또는, 비아패턴의 위치가 서로 다른 반도체 칩, 또는, 스크라이브 라인(scribe line) 영역이 서로 다른 반도체 칩에 상관없이 패키지를 스택할 수 있는 잇점이 있다.
게다가, 본 발명은 본딩패드가 비아패턴의 크기 및 위치에 관계없이 반도체 칩의 전면에 부착됨에 따라 반도체 칩이 받는 스트레스가 넓게 분산되어 신뢰성을 향상시킬 수 있다.

Claims (5)

  1. 인쇄회로기판;
    상기 인쇄회로기판 상에 적어도 둘 이상이 스택되며, 상면에 본딩패드와 연결된 제1도전패턴을 구비하고, 가장자리 내부에 상기 제1도전패턴과 연결된 비아패턴을 구비하며, 하면에 상기 비아패턴과 연결된 제2도전패턴을 구비한 반도체 칩;
    상기 스택된 반도체칩들의 대응하는 제1도전패턴과 제2도전패턴 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제1솔더볼;
    상기 스택된 반도체칩들 중 최하부 반도체칩의 제1도전패턴과 인쇄회로기판 사이에 개재되도록 상기 반도체 칩의 전면에 구비되어 상호 간의 전기적 및 기계적 연결을 이루는 제2솔더볼; 및
    상기 인쇄회로기판의 하면에 부착되어 실장 수단으로 기능하는 제3솔더볼;
    을 포함하는 것을 특징으로 하는 스택 패키지.
  2. 제 1 항에 있어서,
    상기 본딩패드는 비아패턴의 크기 및 비아패턴의 위치와 관계없이 반도체 칩의 전면에 형성된 것을 특징으로 하는 스택 패키지.
  3. 제 1 항에 있어서,
    상기 제1 및 제2도전패턴은 구리 인 것을 특징으로 하는 스택 패키지.
  4. 제 1 항에 있어서,
    상기 제1 및 제2도전패턴의 일부분을 제외한 반도체 칩 부분을 감싸는 솔더 레지스트를 더 포함하는 것을 특징으로 하는 스택 패키지.
  5. 삭제
KR20060025054A 2006-03-17 2006-03-17 스택 패키지 KR100753415B1 (ko)

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US11/647,703 US7598617B2 (en) 2006-03-17 2006-12-29 Stack package utilizing through vias and re-distribution lines
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