CN101038908A - 使用通路和重配线的层叠封装 - Google Patents

使用通路和重配线的层叠封装 Download PDF

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Publication number
CN101038908A
CN101038908A CNA2007100877831A CN200710087783A CN101038908A CN 101038908 A CN101038908 A CN 101038908A CN A2007100877831 A CNA2007100877831 A CN A2007100877831A CN 200710087783 A CN200710087783 A CN 200710087783A CN 101038908 A CN101038908 A CN 101038908A
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semiconductor chip
reprovision
laminate packaging
line
circuit board
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CNA2007100877831A
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CN100541789C (zh
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李升铉
徐敏硕
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

一种层叠封装包括：印刷电路板；至少两个半导体芯片，以面向下的方式层叠在印刷电路板上，每个半导体芯片具有形成于其上表面并连接到接合焊垫的第一重配线、形成为贯穿该半导体芯片且连接到第一重配线的硅通路、和形成于该半导体芯片的下表面并连接到该硅通路的第二重配线；第一和第二焊球，夹置于彼此相对的第一和第二重配线之间以及最下面的半导体芯片的第一重配线和印刷电路板的电极端子之间；成型材料，用于成型包括该层叠半导体芯片的印刷电路板的上表面；以及第三焊球，附着在该印刷电路板的下表面的焊球盘上，作为安装装置。

Description

使用通路和重配线的层叠封装
技术领域
本发明涉及层叠封装，更具体地涉及使用重配线和焊球的层叠封装。
背景技术
随着电子产品的性能的改进，已经开发将数量越来越多的封装安装到尺寸有限的基板的技术。一般来说，在层叠封装中，将一个半导体芯片安装在基板上，这增大了得到期望容量的困难。
增加存储芯片容量的方法之一是提高集成度，也就是在有限空间中增加单元数目。然而该方法需要使用涉及精细设计规则的高精度工艺并导致较长的研发时间。因此，有人开发层叠技术以容易地实现高集成度，而层叠技术的开发也越来越受到注目。
在半导体产业中，术语“层叠”表示垂直地布置至少两个半导体芯片以增加存储容量。例如将两个256M DRAM芯片层叠在一起，可以在单一封装内配置形成512M DRAM。此外层叠技术具有提高封装密度和封装面积的使用效率的优点。
对于层叠至少两个半导体芯片，本领域中已知的是将至少两个半导体芯片层叠在一个封装中的方法，以及层叠至少两个封装的方法。
图1是示出了以第一方法制造的传统层叠封装的剖面视图。参考图1，在芯片周围具有接合焊垫112、122和132的三个不同尺寸的半导体芯片110、120和130，堆叠在印刷电路板(以下简称为PCB)100上。半导体芯片110、120和130的接合焊垫112、122和132分别和PCB 100的电路图形102通过金属布线140连接。由成型材料150成型包括半导体芯片110，120和130以及金属布线140的PCB 100上表面。提供与外部电路电连接的焊球160附着在PCB 100的下表面。
然而，在从上述构造方法得到的传统层叠封装中，由于接合焊垫112、122和132形成于半导体芯片110、120和130的周围并通过金属布线140连接到PCB 100的电路图形102，因此无法堆叠相同尺寸的半导体芯片，除非在两个相接的半导体芯片之间加入包含吸振材质的胶带。此外，由于传统层叠封装中是由金属布线140形成电连接，因此难以将该层叠封装应用于高速产品。此外传统层叠封装中的布线回路(wire loop)也会增大封装的尺寸。
发明内容
本发明的实施例涉及一种层叠封装，其可以层叠相同尺寸的半导体芯片而不需要使用包含吸振材质的胶带。
此外，本发明的实施例涉及一种层叠封装，其可以容易地应用于高速产品。
另外，本发明的实施例涉及一种层叠封装，其可以减小整体尺寸。
在一个实施例中，层叠封装包括：印刷电路板(PCB)，其形成有电路图形，且其上表面上具有电极端子而下表面具有焊球盘；至少两个半导体芯片，以面向下的方式层叠在PCB上，每个半导体芯片具有形成于其上表面并连接到接合焊垫的第一重配线、形成为贯穿该半导体芯片且连接到第一重配线的硅通路、和形成于该半导体芯片的下表面并连接到该硅通路的第二重配线；第一焊球，夹置于彼此相对的层叠的半导体芯片的第一和第二重配线之间，由此在其间形成电连接和物理连接；第二焊球，夹置于层叠的半导体芯片最下面的半导体芯片的第一重配线和该印刷电路板的电极端子之间，由此在其间形成电连接和物理连接；成型材料，成型包括该层叠的半导体芯片的印刷电路板的上表面；以及第三焊球，附着在该印刷电路板的下表面的焊球盘上，作为安装装置。
该第一和第二重配线由铜形成。
该硅通路由铜或镍/金形成。
每个硅通路包括形成于半导体芯片和硅通路之间的绝缘层。
层叠封装包括形成于每个半导体芯片的上表面和下表面上的防焊漆(solder resist)，其仅露出部分的第一和第二重配线。
半导体芯片的尺寸相同，且半导体芯片的第一和第二重配线的尺寸也相同。
半导体芯片具有不同尺寸，且其中一个半导体芯片的第二重配线长度足以将第二重配线连接到另一个半导体芯片的对应的第一重配线。
附图说明
图1是示出了传统层叠封装的剖面视图。
图2A和图2B是根据本发明一个实施例的层叠封装剖面视图。
图3是说明本发明实施例的层叠封装的焊球固定结构的仰视图。
图4是根据本发明另一实施例的层叠封装剖面视图。
具体实施方式
在本发明中，硅通路(以下简称为“TSV”)和重配线分别形成于将被层叠的各个半导体芯片内，并藉由彼此连接重配线而形成上述半导体芯片的层叠。
在本发明的层叠封装中，TSV、重配线和焊球形成半导体芯片之间的电连接，这提供了诸多优点。第一，藉由使电信号传输路径最小化而使得可以将层叠封装应用于高速产品。第二，相同尺寸和不同尺寸的半导体芯片都可以容易地相互堆叠，而不需要在两个相接的半导体芯片之间放置包含吸振材质的胶带。第三，由于不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
接下来，参考图2A和2B说明本发明实施例的层叠封装。图2A是示出了形成有重配线和TSV的半导体芯片的剖面视图。图2B是示出了形成有重配线和TSV层叠在印刷电路板(PCB)上的层叠封装的剖面视图。
参考图2A，半导体芯片210具有位于其上表面的周围部分的接合焊垫212。穿过半导体芯片210确定毗邻接合焊垫212的TSV 214。第一重配线216和第二重配线217形成于半导体芯片210的上表面和下表面上，使得第一重配线216和第二重配线217分别连接到TSV 214的上端和下端。第一重配线216连接到TSV 214的上端以及接合焊垫212。防焊漆218形成于包括第一重配线216和第二重配线217的半导体芯片210的上表面和下表面上，使得第一重配线216和第二重配线217只有部分被暴露。
接合焊垫212形成于半导体芯片210的上表面，而与TSV 214的尺寸和位置无关。每个TSV 214按照使得铜或镍/金填入穿过半导体芯片210确定的通路内的方式形式。具体而言，TSV 214包括用于电绝缘的绝缘层(未示出)，该绝缘层形成于半导体芯片210和TSV 214之间的界面上。第一重配线216和第二重配线217由铜形成。
参考图2B中的PCB 200。PCB 200形成有电路图形(未示出)，并具有位于其上表面的电极端子202和位于其下表面的焊球盘204。至少两个，例如图2B中三个具有上述结构的半导体芯片210、220和230，以面向下的方式堆叠在PCB 200上。
这里，层叠的半导体芯片210、220和230通过第一焊球260a彼此电和物理连接，其中第一焊球260a夹置于彼此面对的第一重配线226和236和第二重配线217和227之间。层叠的半导体芯片210、220和230中最下面的半导体芯片210和PCB 200通过第二焊球260b彼此电连接和物理连接，其中第二焊球260b夹置于彼此面对的接合焊垫212和电极端子202之间。
为了避免半导体芯片210、220和230受到外界环境损害，包括层叠的半导体芯片210、220和230的PCB 200的上表面通过成型材料250成型。用做与外部电路安装装置的第三焊球260c附着在PCB 200下表面上的焊球盘204。在图2B中，参考数字224和234表示分别形成为穿过半导体芯片220和230的TSV；参考数字222和232表示分别形成于半导体芯片220和230上的接合焊垫；参考数字237表示形成于半导体芯片230上的第二重配线。
在根据本发明的层叠封装中，半导体芯片之间的电连接以及半导体芯片和PCB之间的电连接由TSV、重配线和焊球所构成而非由金属布线构成。因此根据本发明可以将电信号的传输路径缩短至最小距离，且该层叠封装因此可以应用于高速产品。此外，在本发明中，由于未使用金属布线，所以不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
此外，在本发明中，如图3所示，焊球360可以通过接合焊垫和TSV的重新排列而附着在半导体芯片310的整个表面上。因此，相同尺寸和不同尺寸的半导体芯片都可以容易地堆叠而不需要使用包含吸振材料的胶带。
图4是示出根据本发明另一实施例的层叠封装的剖面视图。参考图4，在根据一个实施例的层叠封装中，每个具有不同尺寸的半导体芯片410、420和430彼此堆叠。这是通过下述情况实现的，即，第一焊球460a和第二焊球460b的附着位置可以通过重新排列接合焊垫412、422和432和TSV 414、424和434来进行调整。也就是说，在本实施例中，通过调整第一重配线416、426和436以及第二重配线417、427和437的长度并调整各个半导体芯片410、420和430中从防焊漆418、428和438的暴露位置，可以随意调整第一焊球460a和第二焊球460b的附着位置，由此可以容易地堆叠不同尺寸的半导体芯片。
然而，在如上所述以及图2所示的本发明的一个实施例的层叠封装中，如果层叠的半导体芯片210、220和230为相同尺寸，则各个半导体芯片210、220和230的第一重配线216、226和236以及第二重配线217、227和237形成为具有相同的长度。相反地，在如上所述以及图4所示的本发明的另一个实施例的层叠封装中，如果层叠的半导体芯片410、420和430为不同尺寸，则各个半导体芯片410、420和430的第一重配线416、426和436以及第二重配线417、427、437形成为具有不同的长度。例如，各个半导体芯片410、420和430的第二重配线417、427和437的长度必须足以让第二重配线417、427和437连接到位于上方的半导体芯片420和430的相对应的第一重配线426和436。
在该层叠封装中，包括层叠的半导体芯片410、420和430的PCB 400的上表面由成型材料成型。在图4中，参考数字460c表示第三焊球。
通过上述描述显而易见的是，根据本发明的各种实施例的层叠封装的优点包括：由于半导体芯片之间的电连接以及半导体芯片和PCB之间的电连接是由TSV和重配线形成而无需使用金属布线，因此该层叠封装可以容易地应用于高速产品。此外，在本发明中，由于不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
此外，由于在本发明中可以适当地调整焊球位置，因此相同尺寸和不同尺寸的半导体芯片都可以容易地堆叠而不需要使用包含吸振材料的特殊胶带。
另外，由于在本发明中焊球可以附着在半导体芯片的整个表面上，半导体芯片中所产生的应力可以分布于大的区域，因此可以提高层叠封装的可靠度。
本发明并不限于上述具体实施例，本领域技术人员在不偏离本发明的精神及发明范围内对本发明进行各种变更、添加和替代。
本专利申请主张于2006年3月17日提交的韩国专利申请No.10-2006-0025054的优先权，其全部内容于此引入作为参考。

Claims (9)

1.一种层叠封装，包括：
印刷电路板，形成有电路图形，且具有位于其上表面上的电极端子以及位于其下表面上的焊球盘；
至少两个半导体芯片，以面向下的方式层叠在所述印刷电路板上，每个半导体芯片具有形成于其上表面并连接到接合焊垫的第一重配线、形成为贯穿所述半导体芯片且连接到所述第一重配线的硅通路、以及形成于所述半导体芯片的下表面并连接到所述硅通路的第二重配线；
第一焊球，夹置于彼此相对的层叠的半导体芯片的所述第一和第二重配线之间，由此在其间形成电连接和物理连接；
第二焊球，夹置于所述层叠的半导体芯片最下面的半导体芯片的所述第一重配线和所述印刷电路板的所述电极端子之间，由此在其间形成电连接和物理连接；
成型材料，用于成型包括所述层叠的半导体芯片的所述印刷电路板的上表面；以及
第三焊球，附着在所述印刷电路板的下表面的所述焊球盘上，作为安装装置。
2.如权利要求1的层叠封装，其中所述第一和第二重配线由铜形成。
3.如权利要求1的层叠封装，其中所述硅通路由铜或镍/金形成。
4.如权利要求1的层叠封装，其中每个硅通路具有形成于所述半导体芯片和所述硅通路之间的界面上的绝缘层。
5.如权利要求1的层叠封装，还包括形成于每个半导体芯片的上和下表面上的防焊漆，其仅露出部分的所述第一和第二重配线。
6.如权利要求1的层叠封装，其中所述半导体芯片的尺寸相同。
7.如权利要求6的层叠封装，其中所述半导体芯片的所述第一和第二重配线的尺寸相同。
8.如权利要求1的层叠封装，其中所述半导体芯片具有不同尺寸。
9.如权利要求8的层叠封装，其中一个半导体芯片的所述第二重配线的长度足以将所述第二重配线连接到另一个半导体芯片的对应的第一重配线。
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