CN100541789C - 使用通路和重配线的层叠封装 - Google Patents

使用通路和重配线的层叠封装 Download PDF

Info

Publication number
CN100541789C
CN100541789C CNB2007100877831A CN200710087783A CN100541789C CN 100541789 C CN100541789 C CN 100541789C CN B2007100877831 A CNB2007100877831 A CN B2007100877831A CN 200710087783 A CN200710087783 A CN 200710087783A CN 100541789 C CN100541789 C CN 100541789C
Authority
CN
China
Prior art keywords
semiconductor chip
reprovision
laminate packaging
pcb
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2007100877831A
Other languages
English (en)
Other versions
CN101038908A (zh
Inventor
李升铉
徐敏硕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101038908A publication Critical patent/CN101038908A/zh
Application granted granted Critical
Publication of CN100541789C publication Critical patent/CN100541789C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
    • B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
    • B42D1/00—Books or other bound products
    • B42D1/003—Books or other bound products characterised by shape or material of the sheets
    • B42D1/004—Perforated or punched sheets
    • B42D1/005—Perforated or punched sheets having plural perforation lines, e.g. for detaching parts of the sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
    • B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
    • B42D5/00—Sheets united without binding to form pads or blocks
    • B42D5/001—Sheets united without binding to form pads or blocks perforated or punched sheets
    • B42D5/002—Sheets united without binding to form pads or blocks perforated or punched sheets having plural perforation lines, e.g. for detaching parts of the sheets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B44—DECORATIVE ARTS
    • B44D—PAINTING OR ARTISTIC DRAWING, NOT OTHERWISE PROVIDED FOR; PRESERVING PAINTINGS; SURFACE TREATMENT TO OBTAIN SPECIAL ARTISTIC SURFACE EFFECTS OR FINISHES
    • B44D5/00—Surface treatment to obtain special artistic surface effects or finishes
    • B44D5/10—Mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Educational Administration (AREA)
  • Educational Technology (AREA)
  • Mechanical Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种层叠封装包括：印刷电路板；至少两个半导体芯片，以面向下的方式层叠在印刷电路板上，每个半导体芯片具有形成于其上表面并连接到接合焊垫的第一重配线、形成为贯穿该半导体芯片且连接到第一重配线的硅通路、和形成于该半导体芯片的下表面并连接到该硅通路的第二重配线；第一和第二焊球，夹置于彼此相对的第一和第二重配线之间以及最下面的半导体芯片的第一重配线和印刷电路板的电极端子之间；成型材料，用于成型包括该层叠半导体芯片的印刷电路板的上表面；以及第三焊球，附着在该印刷电路板的下表面的焊球盘上，作为安装装置。

Description

使用通路和重配线的层叠封装
技术领域
本发明涉及层叠封装，更具体地涉及使用重配线和焊球的层叠封装。
背景技术
随着电子产品的性能的改进，已经开发将数量越来越多的封装安装到尺寸有限的基板的技术。一般来说，在层叠封装中，将一个半导体芯片安装在基板上，这增大了得到期望容量的困难。
增加存储芯片容量的方法之一是提高集成度，也就是在有限空间中增加单元数目。然而该方法需要使用涉及精细设计规则的高精度工艺并导致较长的研发时间。因此，有人开发层叠技术以容易地实现高集成度，而层叠技术的开发也越来越受到注目。
在半导体产业中，术语“层叠”表示垂直地布置至少两个半导体芯片以增加存储容量。例如将两个256M DRAM芯片层叠在一起，可以在单一封装内配置形成512M DRAM。此外层叠技术具有提高封装密度和封装面积的使用效率的优点。
对于层叠至少两个半导体芯片，本领域中已知的是将至少两个半导体芯片层叠在一个封装中的方法，以及层叠至少两个封装的方法。
图1是示出了以第一方法制造的传统层叠封装的剖面视图。参考图1，在芯片周围具有接合焊垫112、122和132的三个不同尺寸的半导体芯片110、120和130，堆叠在印刷电路板(以下简称为PCB)100上。半导体芯片110、120和130的接合焊垫112、122和132分别和PCB 100的电路图形102通过金属布线140连接。由成型材料150成型包括半导体芯片110，120和130以及金属布线140的PCB 100上表面。提供与外部电路电连接的焊球160附着在PCB 100的下表面。
然而，在从上述构造方法得到的传统层叠封装中，由于接合焊垫112、122和132形成于半导体芯片110、120和130的周围并通过金属布线140连接到PCB 100的电路图形102，因此无法堆叠相同尺寸的半导体芯片，除非在两个相接的半导体芯片之间加入包含吸振材质的胶带。此外，由于传统层叠封装中是由金属布线140形成电连接，因此难以将该层叠封装应用于高速产品。此外传统层叠封装中的布线回路(wire loop)也会增大封装的尺寸。
发明内容
本发明的实施例涉及一种层叠封装，其可以层叠相同尺寸的半导体芯片而不需要使用包含吸振材质的胶带。
此外，本发明的实施例涉及一种层叠封装，其可以容易地应用于高速产品。
另外，本发明的实施例涉及一种层叠封装，其可以减小整体尺寸。
在一个实施例中，层叠封装包括：印刷电路板(PCB)，其形成有电路图形，且其上表面上具有电极端子而下表面具有焊球盘；至少两个半导体芯片，以面向下的方式层叠在PCB上，每个半导体芯片具有形成于其上表面并连接到接合焊垫的第一重配线、形成为贯穿该半导体芯片且连接到第一重配线的硅通路、和形成于该半导体芯片的下表面并连接到该硅通路的第二重配线；第一焊球，夹置于彼此相对的层叠的半导体芯片的第一和第二重配线之间，由此在其间形成电连接和物理连接；第二焊球，夹置于层叠的半导体芯片最下面的半导体芯片的第一重配线和该印刷电路板的电极端子之间，由此在其间形成电连接和物理连接；成型材料，成型包括该层叠的半导体芯片的印刷电路板的上表面；以及第三焊球，附着在该印刷电路板的下表面的焊球盘上，作为安装装置。
该第一和第二重配线由铜形成。
该硅通路由铜或镍/金形成。
每个硅通路包括形成于半导体芯片和硅通路之间的绝缘层。
层叠封装包括形成于每个半导体芯片的上表面和下表面上的防焊漆(solder resist)，其仅露出部分的第一和第二重配线。
半导体芯片的尺寸相同，且半导体芯片的第一和第二重配线的尺寸也相同。
半导体芯片具有不同尺寸，且其中一个半导体芯片的第二重配线长度足以将第二重配线连接到另一个半导体芯片的对应的第一重配线。
附图说明
图1是示出了传统层叠封装的剖面视图。
图2A和图2B是根据本发明一个实施例的层叠封装剖面视图。
图3是说明本发明实施例的层叠封装的焊球固定结构的仰视图。
图4是根据本发明另一实施例的层叠封装剖面视图。
具体实施方式
在本发明中，硅通路(以下简称为“TSV”)和重配线分别形成于将被层叠的各个半导体芯片内，并藉由彼此连接重配线而形成上述半导体芯片的层叠。
在本发明的层叠封装中，TSV、重配线和焊球形成半导体芯片之间的电连接，这提供了诸多优点。第一，藉由使电信号传输路径最小化而使得可以将层叠封装应用于高速产品。第二，相同尺寸和不同尺寸的半导体芯片都可以容易地相互堆叠，而不需要在两个相接的半导体芯片之间放置包含吸振材质的胶带。第三，由于不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
接下来，参考图2A和2B说明本发明实施例的层叠封装。图2A是示出了形成有重配线和TSV的半导体芯片的剖面视图。图2B是示出了形成有重配线和TSV层叠在印刷电路板(PCB)上的层叠封装的剖面视图。
参考图2A，半导体芯片210具有位于其上表面的周围部分的接合焊垫212。穿过半导体芯片210确定毗邻接合焊垫212的TSV 214。第一重配线216和第二重配线217形成于半导体芯片210的上表面和下表面上，使得第一重配线216和第二重配线217分别连接到TSV 214的上端和下端。第一重配线216连接到TSV 214的上端以及接合焊垫212。防焊漆218形成于包括第一重配线216和第二重配线217的半导体芯片210的上表面和下表面上，使得第一重配线216和第二重配线217只有部分被暴露。
接合焊垫212形成于半导体芯片210的上表面，而与TSV 214的尺寸和位置无关。每个TSV 214按照使得铜或镍/金填入穿过半导体芯片210确定的通路内的方式形式。具体而言，TSV 214包括用于电绝缘的绝缘层(未示出)，该绝缘层形成于半导体芯片210和TSV 214之间的界面上。第一重配线216和第二重配线217由铜形成。
参考图2B中的PCB 200。PCB 200形成有电路图形(未示出)，并具有位于其上表面的电极端子202和位于其下表面的焊球盘204。至少两个，例如图2B中三个具有上述结构的半导体芯片210、220和230，以面向下的方式堆叠在PCB 200上。
这里，层叠的半导体芯片210、220和230通过第一焊球260a彼此电和物理连接，其中第一焊球260a夹置于彼此面对的第一重配线226和236和第二重配线217和227之间。层叠的半导体芯片210、220和230中最下面的半导体芯片210和PCB 200通过第二焊球260b彼此电连接和物理连接，其中第二焊球260b夹置于彼此面对的接合焊垫212和电极端子202之间。
为了避免半导体芯片210、220和230受到外界环境损害，包括层叠的半导体芯片210、220和230的PCB 200的上表面通过成型材料250成型。用做与外部电路安装装置的第三焊球260c附着在PCB 200下表面上的焊球盘204。在图2B中，参考数字224和234表示分别形成为穿过半导体芯片220和230的TSV；参考数字222和232表示分别形成于半导体芯片220和230上的接合焊垫；参考数字237表示形成于半导体芯片230上的第二重配线。
在根据本发明的层叠封装中，半导体芯片之间的电连接以及半导体芯片和PCB之间的电连接由TSV、重配线和焊球所构成而非由金属布线构成。因此根据本发明可以将电信号的传输路径缩短至最小距离，且该层叠封装因此可以应用于高速产品。此外，在本发明中，由于未使用金属布线，所以不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
此外，在本发明中，如图3所示，焊球360可以通过接合焊垫和TSV的重新排列而附着在半导体芯片310的整个表面上。因此，相同尺寸和不同尺寸的半导体芯片都可以容易地堆叠而不需要使用包含吸振材料的胶带。
图4是示出根据本发明另一实施例的层叠封装的剖面视图。参考图4，在根据一个实施例的层叠封装中，每个具有不同尺寸的半导体芯片410、420和430彼此堆叠。这是通过下述情况实现的，即，第一焊球460a和第二焊球460b的附着位置可以通过重新排列接合焊垫412、422和432和TSV 414、424和434来进行调整。也就是说，在本实施例中，通过调整第一重配线416、426和436以及第二重配线417、427和437的长度并调整各个半导体芯片410、420和430中从防焊漆418、428和438的暴露位置，可以随意调整第一焊球460a和第二焊球460b的附着位置，由此可以容易地堆叠不同尺寸的半导体芯片。
然而，在如上所述以及图2所示的本发明的一个实施例的层叠封装中，如果层叠的半导体芯片210、220和230为相同尺寸，则各个半导体芯片210、220和230的第一重配线216、226和236以及第二重配线217、227和237形成为具有相同的长度。相反地，在如上所述以及图4所示的本发明的另一个实施例的层叠封装中，如果层叠的半导体芯片410、420和430为不同尺寸，则各个半导体芯片410、420和430的第一重配线416、426和436以及第二重配线417、427、437形成为具有不同的长度。例如，各个半导体芯片410、420和430的第二重配线417、427和437的长度必须足以让第二重配线417、427和437连接到位于上方的半导体芯片420和430的相对应的第一重配线426和436。
在该层叠封装中，包括层叠的半导体芯片410、420和430的PCB 400的上表面由成型材料成型。在图4中，参考数字460c表示第三焊球。
通过上述描述显而易见的是，根据本发明的各种实施例的层叠封装的优点包括：由于半导体芯片之间的电连接以及半导体芯片和PCB之间的电连接是由TSV和重配线形成而无需使用金属布线，因此该层叠封装可以容易地应用于高速产品。此外，在本发明中，由于不需要考虑布线回路的问题，因此可以缩小层叠封装的整体尺寸。
此外，由于在本发明中可以适当地调整焊球位置，因此相同尺寸和不同尺寸的半导体芯片都可以容易地堆叠而不需要使用包含吸振材料的特殊胶带。
另外，由于在本发明中焊球可以附着在半导体芯片的整个表面上，半导体芯片中所产生的应力可以分布于大的区域，因此可以提高层叠封装的可靠度。
本发明并不限于上述具体实施例，本领域技术人员在不偏离本发明的精神及发明范围内对本发明进行各种变更、添加和替代。
本专利申请主张于2006年3月17日提交的韩国专利申请No.10-2006-0025054的优先权，其全部内容于此引入作为参考。

Claims (9)

1.一种层叠封装，包括：
印刷电路板，形成有电路图形，且具有位于其上表面上的电极端子以及位于其下表面上的焊球盘；
至少两个半导体芯片，以面向下的方式层叠在所述印刷电路板上，每个半导体芯片具有形成于所述半导体芯片的上表面并连接到接合焊垫的第一重配线、形成为贯穿所述半导体芯片且连接到所述第一重配线的硅通孔、以及形成于与所述上表面相反的下表面并连接到所述硅通孔的第二重配线；
第一焊球，夹置于彼此相对的所述层叠半导体芯片的所述第一和第二重配线之间，由此在其间形成电学和物理连接；
第二焊球，夹置于所述层叠半导体芯片最下面的半导体芯片的所述第一重配线和所述印刷电路板的所述电极端子之间，由此在其间形成电学和物理连接；
成型材料，用于成型包括所述层叠半导体芯片的所述印刷电路板的上表面；以及
第三焊球，附着在所述印刷电路板的下表面的所述焊球盘上，作为安装装置，
其中所述接合焊垫形成在所述半导体芯片的上表面，而与所述硅通孔的尺寸和位置无关。
2.如权利要求1的层叠封装，其中所述第一和第二重配线由铜形成。
3.如权利要求1的层叠封装，其中所述硅通孔由铜或镍/金形成。
4.如权利要求1的层叠封装，其中每个硅通孔具有形成于所述半导体芯片和所述硅通孔之间的界面上的绝缘层。
5.如权利要求1的层叠封装，还包括形成于每个半导体芯片的上和下表面上的防焊漆，其仅露出部分的所述第一和第二重配线。
6.如权利要求1的层叠封装，其中所述半导体芯片的尺寸相同。
7.如权利要求6的层叠封装，其中所述半导体芯片的所述第一和第二重配线的尺寸相同。
8.如权利要求1的层叠封装，其中所述半导体芯片具有不同尺寸。
9.如权利要求8的层叠封装，其中一个半导体芯片的所述第二重配线长度足以将所述第二重配线连接到另一个半导体芯片的对应的第一重配线。
CNB2007100877831A 2006-03-17 2007-03-19 使用通路和重配线的层叠封装 Active CN100541789C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR25054/06 2006-03-17
KR20060025054A KR100753415B1 (ko) 2006-03-17 2006-03-17 스택 패키지

Publications (2)

Publication Number Publication Date
CN101038908A CN101038908A (zh) 2007-09-19
CN100541789C true CN100541789C (zh) 2009-09-16

Family

ID=38532488

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2007100877831A Active CN100541789C (zh) 2006-03-17 2007-03-19 使用通路和重配线的层叠封装

Country Status (5)

Country Link
US (1) US7598617B2 (zh)
JP (1) JP2007251145A (zh)
KR (1) KR100753415B1 (zh)
CN (1) CN100541789C (zh)
TW (1) TWI351092B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542701B (zh) * 2008-06-05 2011-05-25 香港应用科技研究院有限公司 基于硅通孔的三维晶圆叠层的键合方法
CN102479770A (zh) * 2010-11-25 2012-05-30 财团法人工业技术研究院 半导体结构及其制作工艺

Families Citing this family (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4340517B2 (ja) 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7628871B2 (en) * 2005-08-12 2009-12-08 Intel Corporation Bulk metallic glass solder material
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US8294252B1 (en) * 2006-08-31 2012-10-23 Altera Corporation Stacked semiconductor substrates
US7692278B2 (en) * 2006-12-20 2010-04-06 Intel Corporation Stacked-die packages with silicon vias and surface activated bonding
US8030761B2 (en) * 2007-05-23 2011-10-04 United Test And Assembly Center Ltd. Mold design and semiconductor package
TWI362102B (en) * 2007-07-11 2012-04-11 Ind Tech Res Inst Three-dimensional dice-stacking package structure and method for manufactruing the same
SG149710A1 (en) 2007-07-12 2009-02-27 Micron Technology Inc Interconnects for packaged semiconductor devices and methods for manufacturing such devices
US20090032970A1 (en) * 2007-07-31 2009-02-05 Park Chang-Min Stacking of integrated circuits using glassy metal bonding
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
JP4588060B2 (ja) * 2007-09-19 2010-11-24 スパンション エルエルシー 半導体装置及びその製造方法
US7547630B2 (en) * 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
KR100891537B1 (ko) * 2007-12-13 2009-04-03 주식회사 하이닉스반도체 반도체 패키지용 기판 및 이를 갖는 반도체 패키지
US8084854B2 (en) 2007-12-28 2011-12-27 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US8847377B2 (en) 2008-01-02 2014-09-30 SK Hynix Inc. Stacked wafer level package having a reduced size
US8138610B2 (en) * 2008-02-08 2012-03-20 Qimonda Ag Multi-chip package with interconnected stacked chips
US7477811B1 (en) 2008-03-25 2009-01-13 International Business Machines Corporation Method of forming a three-dimensional stacked optical device
US7480426B1 (en) 2008-03-25 2009-01-20 International Business Machines Corporation Method of forming a three-dimensional stacked optical device
US8912654B2 (en) * 2008-04-11 2014-12-16 Qimonda Ag Semiconductor chip with integrated via
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US7683459B2 (en) * 2008-06-02 2010-03-23 Hong Kong Applied Science and Technology Research Institute Company, Ltd. Bonding method for through-silicon-via based 3D wafer stacking
US7745920B2 (en) * 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
KR100997788B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 반도체 패키지
CN101626015B (zh) * 2008-07-11 2011-11-30 南茂科技股份有限公司 封装结构及其形成、量产方法与芯片堆叠结构
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US8334599B2 (en) * 2008-08-21 2012-12-18 Qimonda Ag Electronic device having a chip stack
KR20100023641A (ko) * 2008-08-22 2010-03-04 삼성전자주식회사 회로 기판을 관통하는 비아 플러그를 포함하는 반도체 칩, 반도체 칩 적층 구조 및 반도체 패키지
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8030780B2 (en) 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
JPWO2010047228A1 (ja) * 2008-10-21 2012-03-22 日本電気株式会社 配線基板およびその製造方法
US8102029B2 (en) * 2008-10-31 2012-01-24 Fairchild Semiconductor Corporation Wafer level buck converter
US8080885B2 (en) * 2008-11-19 2011-12-20 Stats Chippac Ltd. Integrated circuit packaging system with multi level contact and method of manufacture thereof
TWI460838B (zh) * 2008-12-08 2014-11-11 United Microelectronics Corp 半導體結構
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US8093711B2 (en) * 2009-02-02 2012-01-10 Infineon Technologies Ag Semiconductor device
JP5389464B2 (ja) 2009-02-10 2014-01-15 フリースケール セミコンダクター インコーポレイテッド 半導体装置の製造方法
JP2010198869A (ja) * 2009-02-24 2010-09-09 Advanced Systems Japan Inc スルーシリコンビア構造を有するウエハーレベルコネクタ
US20100237481A1 (en) * 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US7923290B2 (en) * 2009-03-27 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system having dual sided connection and method of manufacture thereof
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US7892963B2 (en) * 2009-04-24 2011-02-22 Globalfoundries Singapore Pte. Ltd. Integrated circuit packaging system and method of manufacture thereof
KR101078734B1 (ko) * 2009-07-07 2011-11-02 주식회사 하이닉스반도체 반도체 패키지 및 그 제조방법과, 이를 이용한 스택 패키지
KR101583719B1 (ko) 2009-07-21 2016-01-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US7863735B1 (en) * 2009-08-07 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
US9397050B2 (en) * 2009-08-31 2016-07-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant
US8803332B2 (en) * 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US7867821B1 (en) * 2009-09-18 2011-01-11 Stats Chippac Ltd. Integrated circuit package system with through semiconductor vias and method of manufacture thereof
KR101086875B1 (ko) * 2009-09-30 2011-11-25 주식회사 하이닉스반도체 데이터 전송회로 및 이를 포함하는 반도체 장치
KR101069710B1 (ko) 2009-10-29 2011-10-04 주식회사 하이닉스반도체 반도체 장치 및 이의 칩 선택방법
KR101053534B1 (ko) * 2009-10-29 2011-08-03 주식회사 하이닉스반도체 반도체 장치 및 이의 칩 선택방법
KR101123804B1 (ko) * 2009-11-20 2012-03-12 주식회사 하이닉스반도체 반도체 칩 및 이를 갖는 적층 반도체 패키지
KR101069460B1 (ko) 2010-02-25 2011-09-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101094947B1 (ko) * 2010-02-26 2011-12-15 주식회사 하이닉스반도체 반도체 집적회로
KR101667656B1 (ko) * 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
KR20110130017A (ko) * 2010-05-27 2011-12-05 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US8674510B2 (en) * 2010-07-29 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure having improved power and thermal management
US8288201B2 (en) * 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
TW201216439A (en) * 2010-10-08 2012-04-16 Universal Scient Ind Co Ltd Chip stacked structure
KR101157032B1 (ko) * 2010-11-17 2012-06-21 에스케이하이닉스 주식회사 반도체 장치
KR101321170B1 (ko) * 2010-12-21 2013-10-23 삼성전기주식회사 패키지 및 이의 제조 방법
KR101263663B1 (ko) * 2011-02-09 2013-05-22 에스케이하이닉스 주식회사 반도체 장치
US8487447B2 (en) * 2011-05-19 2013-07-16 International Business Machines Corporation Semiconductor structure having offset passivation to reduce electromigration
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
JP2013038100A (ja) * 2011-08-03 2013-02-21 Elpida Memory Inc 半導体装置
US8937309B2 (en) * 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US9418876B2 (en) 2011-09-02 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of three dimensional integrated circuit assembly
US9245773B2 (en) 2011-09-02 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging methods and structures thereof
TWI449152B (zh) 2011-12-21 2014-08-11 Ind Tech Res Inst 半導體元件堆疊結構
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
KR20140041975A (ko) * 2012-09-25 2014-04-07 삼성전자주식회사 범프 구조체 및 이를 포함하는 전기적 연결 구조체
KR101371331B1 (ko) * 2012-10-30 2014-03-10 주식회사 고려반도체시스템 고속 고정도 정렬 스태킹 공정을 위한 칩의 솔더볼 어태치 및 배열 상태의 검사 방법 및 이에 사용되는 검사 장치
KR101451502B1 (ko) * 2013-03-05 2014-10-15 삼성전기주식회사 인쇄회로기판
CN103199071A (zh) * 2013-03-29 2013-07-10 日月光半导体制造股份有限公司 堆迭式封装结构及其制造方法
CN104701292A (zh) * 2013-12-06 2015-06-10 上海北京大学微电子研究院 一种高速ic-qfn封装协同优化设计方法
US9793242B2 (en) * 2013-12-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with die stack including exposed molding underfill
US9583460B2 (en) 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US9679801B2 (en) 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
KR102410992B1 (ko) 2015-11-26 2022-06-20 삼성전자주식회사 적층형 메모리 장치, 이를 포함하는 메모리 패키지 및 메모리 시스템
US9893042B2 (en) * 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102505853B1 (ko) * 2016-07-06 2023-03-03 삼성전자 주식회사 반도체 패키지
DE112018007691A5 (de) 2018-06-05 2021-02-18 Pac Tech - Packaging Technologies Gmbh Halbleiterchip-Stapelanordnung sowie Halbleiterchip zur Herstellung einer derartigen Halbleiterchip-Stapelanordnung
US10978426B2 (en) * 2018-12-31 2021-04-13 Micron Technology, Inc. Semiconductor packages with pass-through clock traces and associated systems and methods
CN110047764B (zh) * 2019-04-01 2021-07-30 京微齐力(北京)科技有限公司 一种集成fpga芯片和人工智能芯片的系统级封装方法
CN110054143B (zh) * 2019-04-30 2021-08-31 西安微电子技术研究所 一种小型化抗高过载硅基微系统装置及其组装方法
KR20230044858A (ko) * 2021-09-27 2023-04-04 삼성전자주식회사 반도체 패키지

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4011695B2 (ja) 1996-12-02 2007-11-21 株式会社東芝 マルチチップ半導体装置用チップおよびその形成方法
KR100282003B1 (ko) * 1997-10-15 2001-02-15 윤종용 칩 스케일 패키지
JP4547728B2 (ja) * 1999-03-29 2010-09-22 ソニー株式会社 半導体装置及びその製造方法
JP3360655B2 (ja) * 1999-07-08 2002-12-24 日本電気株式会社 半導体装置
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
JP2002373957A (ja) * 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
KR100818080B1 (ko) * 2002-06-10 2008-03-31 주식회사 하이닉스반도체 칩 스택 패키지
JP3917484B2 (ja) * 2002-07-18 2007-05-23 富士通株式会社 半導体装置の製造方法および半導体装置
US7332625B2 (en) * 2002-09-10 2008-02-19 Arkema Process for the production of acrylic acid from propane
JP2004128042A (ja) * 2002-09-30 2004-04-22 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
JP4248928B2 (ja) * 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
JP2004363573A (ja) 2003-05-15 2004-12-24 Kumamoto Technology & Industry Foundation 半導体チップ実装体およびその製造方法
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP2005101186A (ja) * 2003-09-24 2005-04-14 Seiko Epson Corp 積層型半導体集積回路
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
JP4379307B2 (ja) * 2004-01-09 2009-12-09 セイコーエプソン株式会社 電子部品及び電子機器
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
KR100570514B1 (ko) * 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
JP2006278906A (ja) * 2005-03-30 2006-10-12 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
KR20060133800A (ko) 2005-06-21 2006-12-27 주식회사 하이닉스반도체 칩 스택 패키지
JP2007049115A (ja) * 2005-07-13 2007-02-22 Seiko Epson Corp 半導体装置
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
KR100832845B1 (ko) * 2006-10-03 2008-05-28 삼성전자주식회사 반도체 패키지 구조체 및 그 제조 방법
KR100817073B1 (ko) * 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542701B (zh) * 2008-06-05 2011-05-25 香港应用科技研究院有限公司 基于硅通孔的三维晶圆叠层的键合方法
CN102479770A (zh) * 2010-11-25 2012-05-30 财团法人工业技术研究院 半导体结构及其制作工艺

Also Published As

Publication number Publication date
US7598617B2 (en) 2009-10-06
US20070222050A1 (en) 2007-09-27
JP2007251145A (ja) 2007-09-27
TW200737482A (en) 2007-10-01
CN101038908A (zh) 2007-09-19
KR100753415B1 (ko) 2007-08-30
TWI351092B (en) 2011-10-21

Similar Documents

Publication Publication Date Title
CN100541789C (zh) 使用通路和重配线的层叠封装
US7321164B2 (en) Stack structure with semiconductor chip embedded in carrier
CN101355067B (zh) 多芯片模块的改进的电连接
US7446420B1 (en) Through silicon via chip stack package capable of facilitating chip selection during device operation
CN100470793C (zh) 半导体器件和制造半导体器件的方法
KR100833589B1 (ko) 스택 패키지
US7429792B2 (en) Stack package with vertically formed heat sink
US20110317381A1 (en) Embedded chip-on-chip package and package-on-package comprising same
CN1893053A (zh) 插件结构及其制造方法、晶片级堆叠结构和封装结构
US7615858B2 (en) Stacked-type semiconductor device package
CN101192544B (zh) 半导体元件埋入承载板的叠接结构及其制法
US20200035649A1 (en) Semiconductor package
KR101227078B1 (ko) 반도체 패키지 및 그 형성방법
KR20200127535A (ko) 팬 아웃 서브 패키지를 포함한 스택 패키지
US6803666B2 (en) Semiconductor chip mounting substrate and semiconductor device using the same
KR20160047841A (ko) 반도체 패키지
CN1619812B (zh) 层叠型半导体器件
JP5022042B2 (ja) 半導体素子埋め込み支持基板の積層構造とその製造方法
KR100988511B1 (ko) 반도체 소자가 매립된 지지 기판 적층 구조체 및 그제조방법
CN101465341B (zh) 堆叠式芯片封装结构
JP4083376B2 (ja) 半導体モジュール
KR101099579B1 (ko) 적층 칩 반도체 패키지
JP2005101186A (ja) 積層型半導体集積回路
KR20080029273A (ko) 스택 패키지 및 이를 이용한 고밀도 멀티 패키지
KR950014124B1 (ko) 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant