TWI449152B - 半導體元件堆疊結構 - Google Patents

半導體元件堆疊結構 Download PDF

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TWI449152B
TWI449152B TW100147767A TW100147767A TWI449152B TW I449152 B TWI449152 B TW I449152B TW 100147767 A TW100147767 A TW 100147767A TW 100147767 A TW100147767 A TW 100147767A TW I449152 B TWI449152 B TW I449152B
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reinforcing
semiconductor device
stack structure
semiconductor
device stack
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TW100147767A
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TW201327768A (zh
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Ding Ming Kwai
Yung Fa Chou
Chiao Ling Lung
Jui Hung Chien
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Ind Tech Res Inst
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Priority to CN201210111141.1A priority patent/CN103178051B/zh
Priority to US13/450,482 priority patent/US9048342B2/en
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Description

半導體元件堆疊結構
本揭露是有關於一種堆疊結構，且特別是有關於一種半導體元件堆疊結構。
在現今的資訊社會中，電子產品的設計是朝向輕、薄、短、小的趨勢邁進，因此發展出諸如堆疊式半導體元件封裝等有利於微型化的封裝技術。
堆疊式半導體元件封裝是利用垂直堆疊的方式將多個半導體元件封裝於同一封裝結構中，如此可提升封裝密度以使封裝體小型化，且可利用立體堆疊的方式縮短半導體元件之間的訊號傳輸的路徑長度，以提升半導體元件之間訊號傳輸的速度，並可將不同功能的半導體元件組合於同一封裝體中。
現行的堆疊式半導體元件封裝通常會在半導體元件內製作多個穿矽孔(through silicon via，TSV)，以藉由穿矽孔提供垂直方向的電性連接路徑。穿矽孔需具備良好的熱機械可靠性(Thermo-Mechanical reliability)，以便於批量生產，但由於穿矽孔內填材料與矽晶之間熱膨脹係數(coefficient of thermal expansion，CTE)的差異，使穿矽孔內產生熱應力，進而導致塑料變形(plastic deformation)、應力誘發孔洞(stress induced voiding)和應力遷移(stress migration)，界面處的應力能導致剝離和 填孔彈出(pop up)甚至導致晶片斷裂等不可挽救的情形。
本揭露一實施範例提供一種半導體元件堆疊結構，其能有效減少穿矽孔之熱應力所造成之半導體元件的翹曲變形。
本揭露一實施範例提出一種半導體元件堆疊結構，包括多個半導體元件及至少一加固結構。半導體元件相互堆疊，其中至少一半導體元件具有至少一穿矽孔。各至少一加固結構圍繞相應的至少一穿矽孔，並且電性隔絕於半導體元件。至少一加固結構包括多個加固件及至少一連結件。加固件位於半導體元件之間，其中加固件在一平面上的垂直投影圍出一封閉區域，且至少一穿矽孔在平面上的投影位於封閉區域內。連結件位於加固件在平面上的垂直投影的重疊區域內，用以連接加固件，而構成至少一加固結構。
為讓本揭露之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本揭露一實施例之半導體元件堆疊結構之局部分解示意圖。圖2為本揭露一實施例之加固結構及穿矽孔於平面上垂直投影之示意圖。其中，圖1將上方之半導體元件110與加固結構120分離，以更清楚地繪示加固結構 120。請同時參考圖1及圖2，本揭露一實施例提出一種半導體元件堆疊結構100，其包括多個半導體元件110(繪示為兩個)及一加固結構120。半導體元件110彼此相互堆疊，且其中一半導體元件110具有一穿矽孔112。在本實施例中，半導體元件110包括相互堆疊的一第一半導體元件110a以及一第二半導體元件110b，而穿矽孔112可以位於第一半導體元件110a中，或是配置於第一半導體元件110a與第二半導體元件110b之間，或是穿過第一半導體元件110a以及第二半導體元件110b。換言之，穿矽孔112可由第一半導體元件110a以及第二半導體元件110b的實際線路佈局來決定。當然，本揭露並不限制半導體元件及其上之穿矽孔的數量或是穿矽孔112在所述半導體元件110之間的位置。
加固結構120圍繞相應的穿矽孔112，並且電性隔絕於半導體元件110，意即，加固結構120不與穿矽孔112及半導體元件110中之其他主動元件形成電性連接。對應於半導體元件110上的穿矽孔112，本實施例繪示一個加固結構120。實際上，加固結構120的數量與位置可以隨半導體元件110上的穿矽孔112數量以及位置來進行調整。
本實施例的加固結構120包括多個加固件122及至少一連結件124，加固件122位於半導體元件110之間，其中加固件122在一平面上的垂直投影P1圍出一封閉區域CR(Close Region)，且穿矽孔112在平面上的投影P2位於封閉區域CR內。連結件124位於加固件122在平面上 的垂直投影P1的重疊區域OR內，用以連接加固件122，而構成加固結構120。換言之，加固結構120藉由位在重疊區域OR內之連結件124，連結位於不同平面之多個加固件122。
在本實施例中，第一半導體元件110a具有一第一表面114，第一表面114面向第二半導體元件110b的一第二表面116。加固件122包括至少一第一加固件122a及至少一第二加固件122b，而第一加固件122a即位於第一表面114上，第二加固件122b則位於第二表面116上。連結件124的數量為多個，分別位於第一表面114與第二表面116之間，用以連接第一加固件122a與第二加固件122b。在本揭露之其他實施例中，第一加固件及第二加固件亦可分別設置於不相鄰之半導體元件之表面上，且第一加固件及第二加固件於一平面上的垂直投影圍出一封閉區域。
詳細而言，半導體元件堆疊結構100更包括一緩衝層130，位於第一加固件122a與第二加固件122b之間，用以吸收穿矽孔112周圍之熱應力所導致之半導體元件110的變形，更可增加第一加固件122a及第二加固件122b的剛性(rigidity)，使半導體元件堆疊結構100的應力分布更為均勻。在本實施例中，第一半導體元件110a及第二半導體元件110b可為晶片、中介片(interposer)、晶圓(wafer)或封裝件，而第一加固件122a可為第一半導體元件110a之一第一表層金屬圖案，第二加固件122b可為第二半導體元件110b之一第二表層金屬圖案。連結件124的材料包括 銅、錫、鐵、金、鎢、鋼、上開金屬之複合物、化合物及合金等熱膨脹係數相近之金屬，且其形狀可為圓形、方形或三角形等，在本實施例中，連結件124為銲球。如上述之配置，半導體元件110可利用其本身之結構形成圍繞穿矽孔112之加固結構120，原則上可減少半導體元件110的翹曲變形，並降低穿矽孔112周圍之應力。
圖3為本揭露一實施例之加固結構之俯視示意圖。請參考圖3，加固結構120與穿矽孔112應符合一定的尺寸比例，以達到較佳之降低熱應力的效果。本實施例，連結件124的外徑D與加固件122的寬度W的比值大於或等於0.5，且小於或等於1.5。穿矽孔112的外徑d與連結件124的外徑D的比值應小於或等於2。穿矽孔112之中心至各連結件124之中心的距離為L，而L≦2(d+D)。並且，其中各連結件124與穿矽孔112之材料的熱膨脹係數比值介於0.75至1.25之間。
圖4為設置加固結構與未設置加固結構之半導體元件之應力比較圖。圖4之橫軸座標為穿矽孔之外徑，縱軸座標為穿矽孔周圍之應力，具斜線之長條圖則代表實施例之半導體元件堆疊結構於不同之穿矽孔外徑下，其穿矽孔周圍之應力。由圖4可知，依穿矽孔之外徑設置如前述之尺寸比例的加固結構於半導體元件上，其穿矽孔周圍之應力與未設置加固結構之半導體元件相比，原則上將降低，並可改善習知半導體元件因應力過大而產生斷裂的情形。
圖5A至圖5E為本揭露五種不同實施例之加固結構之 部分構件俯視圖。圖5A至圖5E之加固結構並未繪示第二加固件，以方便呈現其下方之結構。請先參考圖5A，第一加固件122a包括串連連結件124的多個加固區段140。半導體元件堆疊結構更包括一線路150，位於第一表面114上，線路150的一端連接穿矽孔112，而線路150的另一端朝向其中之一加固區段140a延伸，且所述之加固區段140a具有一開口142，以供線路150通過。在本揭露之另一實施例中，如圖5B所示，線路150的兩端分別朝向相鄰的兩個加固區段140b延伸，所述兩個加固區段140b分別具有一開口142，以供線路150的兩端通過，且線路150在連接穿矽孔112的位置上形成接近90度的轉折。在本揭露之另一實施例中，如圖5C所示，線路150的兩端分別朝向相對的兩個加固區段140c延伸，所述兩個加固區段140c分別具有一開口142，以供線路150的兩端通過。如上述之配置，穿矽孔112即可透過線路150與半導體元件110上之其他元件電性連接。
承上述，加固區段140的寬度及形狀更可因應半導體元件110上不同之線路及元件佈局，或依熱應力分布的大小，而做不同的改變。例如，如圖5D及圖5E所示，加固區段140中的至少一個可具有一第一部分144以及一第二部分146，且第一部分144的寬度W1大於第二部分146的寬度W2，或是，加固件122的邊緣可具有至少一凸出部148a或至少一缺口148b。如此，加固區段140可依半導體元件110上之佈局，改變其寬度或設置缺口148b以繞 過半導體元件110上之線路及元件，更可依半導體元件110上之應力分布大小，於應力較大的部份增加加固區段140之寬度或設置凸出部148a以加強其結構強度。
下表1為本揭露五種不同實施例與習知之半導體元件堆疊結構所承受之最大應力比較表。其中，習知之半導體元件堆疊結構即為未設置加固結構之半導體元件。由下表1可推論，本揭露相較習知原則上可減少之半導體元件堆疊結構之內應力。
綜上所述，本揭露於半導體元件間設置一圍繞其穿矽孔之加固結構，本揭露實施例之加固結構更可依半導體元件上線路及元件的佈局，或應力分布的大小，改變其加固結構之加固區段的寬度，以增加加固結構之應用性及彈性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體元件堆疊結構
110‧‧‧半導體元件
110a‧‧‧第一半導體元件
110b‧‧‧第二半導體元件
112‧‧‧穿矽孔
114‧‧‧第一表面
116‧‧‧第二表面
120‧‧‧加固結構
122‧‧‧加固件
122a‧‧‧第一加固件
122b‧‧‧第二加固件
124‧‧‧連結件
130‧‧‧緩衝層
140、140a、140b、140c‧‧‧加固區段
142‧‧‧開口
144‧‧‧第一部份
146‧‧‧第二部份
148a‧‧‧凸出部
148b‧‧‧缺口
150‧‧‧線路
CR‧‧‧封閉區域
D‧‧‧連結件外徑
d‧‧‧穿矽孔外徑
L‧‧‧距離
OR‧‧‧重疊區域
P1‧‧‧加固件投影
P2‧‧‧穿矽孔投影
W‧‧‧加固件寬度
W1‧‧‧第一部分寬度
W2‧‧‧第二部分寬度
圖1為本揭露一實施例之半導體元件堆疊結構之局部分解示意圖。
圖2為本揭露一實施例之加固結構及矽穿孔於平面上垂直投影之示意圖。
圖3為本揭露一實施例之加固結構之俯視示意圖。
圖4為設置加固結構與未設置加固結構之半導體元件之應力比較圖。
圖5A至圖5E為本揭露五種不同實施例之加固結構之部分構件俯視圖。
100‧‧‧半導體元件堆疊結構
110‧‧‧半導體元件
110a‧‧‧第一半導體元件
110b‧‧‧第二半導體元件
112‧‧‧穿矽孔
114‧‧‧第一表面
116‧‧‧第二表面
120‧‧‧加固結構
122‧‧‧加固件
124‧‧‧連結件

Claims (21)

  1. 一種半導體元件堆疊結構，包括：多個半導體元件，相互堆疊，其中至少一半導體元件具有至少一穿矽孔；以及至少一加固結構，各該至少一加固結構圍繞相應的該至少一穿矽孔，並且電性隔絕於該些半導體元件，該至少一加固結構包括：多個加固件，位於該些半導體元件之間，其中該些加固件在一平面上的垂直投影圍出一封閉區域，且該至少一穿矽孔在該平面上的投影位於該封閉區域內；以及至少一連結件，位於該些加固件在該平面上的垂直投影的重疊區域內，用以連接該些加固件，而構成該至少一加固結構。
  2. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件的外徑與各該加固件的寬度的比值大於或等於0.5，且小於或等於1.5。
  3. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中該至少一穿矽孔之外徑與各該連結件之外徑的比值小於或等於2。
  4. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中該至少一穿矽孔之中心至各該連結件之中心的距離為L，該至少一穿矽孔之外徑為d，各該連結件之外徑為D，且L≦2(d+D)。
  5. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該半導體元件包括一晶片、一中介片、一晶圓或一封裝件。
  6. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件的形狀包括圓形、方形或三角形。
  7. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件與該至少一穿矽孔之材料的熱膨脹係數比值介於0.75至1.25之間。
  8. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件的材料是與該至少一穿矽孔熱膨脹係數相近之金屬。
  9. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中該些半導體元件包括相互堆疊的一第一半導體元件以及一第二半導體元件，該第一半導體元件具有一第一表面，該第一表面面向該第二半導體元件的一第二表面，該至少一穿矽孔位於該第一半導體元件中，該些加固件包括位於該第一表面上的至少一第一加固件以及位於該第二表面上的至少一第二加固件，該至少一連結件位於該第一表面與該第二表面之間，用以連接該至少一第一加固件與該至少一第二加固件。
  10. 如申請專利範圍第9項所述之半導體元件堆疊結構，其中該第一加固件包括該第一半導體元件之一第一表層金屬圖案。
  11. 如申請專利範圍第9項所述之半導體元件堆疊結 構，其中該第二加固件包括該第二半導體元件之一第二表層金屬圖案。
  12. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件包括一銲球。
  13. 如申請專利範圍第9項所述之半導體元件堆疊結構，更包括一緩衝層，位於該第一加固件與該第二加固件之間。
  14. 如申請專利範圍第9項所述之半導體元件堆疊結構，其中該至少一連結件的數量為多個，且該第一加固件包括串連該些連結件的至少一加固區段。
  15. 如申請專利範圍第14項所述之半導體元件堆疊結構，更包括一線路，位於該第一表面上，該線路的一端連接該至少一穿矽孔，且該些加固區段中的一個具有一開口，以供該線路通過。
  16. 如申請專利範圍第14項所述之半導體元件堆疊結構，更包括一線路，位於該第一表面上，該線路連接該至少一穿矽孔，且該線路的兩端分別朝向相鄰的兩個加固區段延伸，所述兩個加固區段分別具有一開口，以供該線路的兩端通過。
  17. 如申請專利範圍第16項所述之半導體元件堆疊結構，其中該線路在連接該至少一穿矽孔的位置上形成接近90度的轉折。
  18. 如申請專利範圍第14項所述之半導體元件堆疊結構，更包括一線路，位於該第一表面上，該線路連接該 至少一穿矽孔，且該線路的兩端分別朝向相對的兩個加固區段延伸，所述兩個加固區段分別具有一開口，以供該線路的兩端通過。
  19. 如申請專利範圍第14項所述之半導體元件堆疊結構，其中該些加固區段中的至少一個具有一第一部分以及一第二部分，其中該第一部分的寬度大於該第二部分的寬度。
  20. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該加固件的邊緣具有至少一凸出部或至少一缺口。
  21. 如申請專利範圍第1項所述之半導體元件堆疊結構，其中各該連結件的材料包括金、鎢、銅、錫、鋼、鐵、上開金屬之複合物、化合物及合金。
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US9048342B2 (en) 2015-06-02

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