CN1505146A - 多芯片模块 - Google Patents

多芯片模块 Download PDF

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Publication number
CN1505146A
CN1505146A CNA200310118688A CN200310118688A CN1505146A CN 1505146 A CN1505146 A CN 1505146A CN A200310118688 A CNA200310118688 A CN A200310118688A CN 200310118688 A CN200310118688 A CN 200310118688A CN 1505146 A CN1505146 A CN 1505146A
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semiconductor chip
chip
base plate
installation base
microcomputer
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|
大脇政典
石川智和
内藤孝洋
铃木诚
ʷ
菊池隆文
小泽隆史
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Renesas Technology Corp
Shinko Electric Co Ltd
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Renesas Technology Corp
Shinko Electric Co Ltd
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Publication of CN1505146A publication Critical patent/CN1505146A/zh
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Abstract

提供了一种具有高性能的紧凑多芯片模块。多个第一种半导体芯片，贴片式安装在一片安装基板的表面上，以便交换信号。一个第二种半导体芯片，其大部分焊接点沿着其一侧排列，与安装基板上的至少一个第一种半导体芯片背靠背地安装。由丝焊连接第二种半导体芯片的焊接点和安装基板上形成的对应电极。利用一种密封材料，封装安装基板上的第一种和第二种半导体芯片以及焊线。

Description

多芯片模块
技术领域
本发明涉及一种多芯片模块(MCM)，尤其是涉及可有效地应用于多芯片模块的一种技术，在该模块中，具有几种不同功能的多个半导体芯片整合地安装在单一的基板上，从而使这多个半导体芯片形成一个本质上单一的半导体集成电路器件。
背景技术
在所谓的多芯片模块技术中，多个半导体芯片安装在一个基板上，它具有多条内部配线和多个外部端子，并且这多个半导体芯片与安装基板整合为一个电路器件。JP-A-2001-320014和JP-A-2000-299431公开了一种双芯片堆叠结构的若干实例，其中上部芯片大于下部芯片。另一方面，JP-A-11-219989公开了一种双芯片堆叠结构的一个实例，其中一个闪存和一个SRAM相互组合。
发明内容
在以下方向，半导体技术正在取得进展：多个半导体芯片，比如构成一个电子系统的一个微计算机芯片、一个DRAM芯片和一个闪存芯片，配置为单一的组件，作为一个半导体器件。确切地说，如果对于其中每一个都包括单一的半导体芯片，而不是多个半导体芯片的多个半导体器件，用通常的封装技术，比如QFP(四方扁平封装)、CSP(芯片尺寸封装或者芯片规模封装)或者BGA(球栅阵列)进行封装，并且安装在一个安装基板上，比如一片印刷电路板，那么半导体芯片之间的距离和配线长度就不容易缩短，结果，提高器件操作速度和减小器件尺寸都会受制于配线导致的较大信号延迟。
相反，按照多芯片模块技术，在单独封装的半导体器件中，制造了多个非常小的半导体芯片，其形式称为裸芯片。所以，能够缩短芯片之间的配线长度，并且能够改善半导体器件的特征。同时，由于在单独的封装中形成了多个半导体芯片，封装的面积减小了，因而能够减小半导体器件的尺寸。
优选情况下，一个多芯片模块选定的半导体芯片包括密切相关的芯片，  比如一个微计算机芯片、与微计算机芯片相连的一个DRAM或一个闪存芯片。通过选择如上所述的多个密切相关的半导体芯片，组合后就能够充分展示多芯片模块的特性。不过，JP-A-2001-320014、JP-A-2000-299431和JP-A-11-219989既没有考虑包括多芯片模块之特性的整体功能，也没有考虑减小器件尺寸，而是仅仅采用了各个芯片的一种堆叠结构。
本发明的目的是提供一种多芯片模块，在减小尺寸的同时改善性能。连同附图阅读了详细说明之后，以上的和其它的目的、特性和优点将会显而易见。
下面将简要介绍本文公开的本发明的典型方面。适于相互交换信号的多个第一种半导体芯片，贴片式安装在一片安装基板的表面上，大部分焊接点沿着一侧排列的一个第二种半导体芯片，与至少一个第一种半导体芯片背靠背地安装，这些焊接点和安装基板上形成的对应电极由丝焊相互连接。在安装基板上的第一种和第二种半导体芯片以及焊线，以一种密封材料封装。
附图简要说明
图1是一幅俯视图，显示了依据本发明的一个实施例的多芯片模块；
图2显示了图1中多芯片模块的安装基板表面上的芯片布局；
图3A和图3B是剖面图，示意性地显示了图1的多芯片模块；
图4是一幅示意图，用于讲解依据本发明之多芯片模块的装配步骤；
图5是一幅框图，显示了依据本发明的一个实施例的多芯片模块；
图6显示了依据本发明的一个实施例中多芯片模块所用的安装基板图案；
图7显示了依据本发明的一个实施例中一个闪存的焊接点布局；
图8显示了依据本发明的一个实施例中多芯片模块的一般外形；
图9是一幅示意图，显示了在本发明之前研究的一种多芯片模块之一般布局的一个实例；
图10是基本部件的一幅剖面图，显示了依据本发明的多芯片模块中的一种修改；
图11是基本部件的一幅剖面图，显示了图10中多芯片模块的制造方法；
图12是基本部件的一幅剖面图，显示了图10中多芯片模块的制造方法；
图13是基本部件的一幅剖面图，显示了图10中多芯片模块的制造方法。
具体实施方式
图1显示了依据本发明的一个实施例之多芯片模块的俯视图。在组件基板上安装着一个闪速EEPROM(闪速可电擦除可编程只读存储器，后文中简称为“闪存”)FLASH，以及一个数字信号装置ASIC。在上述闪存FLASH之下，安装着一个微计算机SH和一个同步动态随机访问存储器SDRAM。
确切地说，安装基板的表面上，如图2所示，已经贴片式安装着微计算机SH、同步动态随机访问存储器SDRAM和数字信号器件ASIC。如图2中的虚线所示，闪存FLASH(以芯片背面相互面对的方式)背靠背地安装在两个半导体芯片SH和SDRAM之上。
图2所示的半导体芯片SH、SDRAM和ASIC安装在安装基板的一个主表面上，其方式为半导体芯片表面形成的电路是相互面对的关系。多芯片模块的多个外部端子排列在安装基板的另一个主表面上。无论多个半导体芯片占据的面积以及排列多个外部端子所需的面积如何，这种结构都有可能制造出紧凑的多芯片模块。
半导体芯片SH、SDRAM和ASIC的结构是所谓的裸芯片，并且具有多个突起的电极，适于通过加压而安装在安装基板上。每个半导体芯片都通过一种面积阵列焊点的技术进行配置，其中使焊点电极(焊接点)能够通过聚酰亚胺树脂等材料的绝缘膜而重新排列的一种配线，形成在器件和配线完成后的半导体芯片的电路形成表面上，而且焊点电极(突起连接平面电极)在配线上形成。
利用上述的面积阵列焊点技术，由于半导体芯片SH、SDRAM和ASIC的外部端子具有0.1mm至0.2mm的直径，以相对较小的间距比如几十μm或100μm排列的焊点电极，转换为具有400μm至600μm的相对较大间距的突起电极的排列。面积阵列焊点技术有效地用于为半导体芯片比如SDRAM安置输入/输出电路，其焊点电极适于排列在半导体芯片的中心。
安装基板具有一种玻璃钢或玻璃的绝缘基底，一种相对较薄的内部配线——配置为在绝缘基底上形成的多层配线结构，与半导体芯片的突起电极导电连接的多个条带，以及多个外部端子。在安装基板要形成半导体芯片的主表面上，通过对闪存FLASH上排列的焊点以及上述条带进行配线，就形成了用于连接的电极。
按照这个实施例的闪存是所谓的AND类型，没有独立的地址端子。地址信号是使用—个数据端子，通过分时串行输入。确切地说，在按照这个实施例的闪存中，如图5所示，通过数据端子I/O(7∶0)取回用于指定操作模式的一个命令、一个地址和数据。通过输入/输出缓冲区输入的信号，通过一条内部信号线，传送到命令解码器和地址计数器。为了这个目的，若干焊点(每一个都是由一个方块表示)沿着半导体芯片的一侧(在这个实施例中是较长的一侧)排列，并且由焊线连接到安装基板上对应的电极。
图1和图2直观地显示了安装基板以及半导体芯片SH、SDRAM、ASIC和FLASH的(纵横向以mm表示的)尺寸。安装基板的尺寸为19和13，SH的尺寸为5.05和5.05，SDRAM的尺寸为8.70和5.99，ASIC的尺寸为6.25和6.15，FLASH的尺寸为7.32和10.46。不过，对于较长方向垂直安置的闪存FLASH，尺寸表示为水平长度和垂直长度。
为了在安装基板上高效地安装四个半导体芯片，矩形芯片SDRAM以其较长方向横向安置，正方形的芯片SH如图2所示垂直安置，从而符合矩形芯片FLASH的长度。以这种方式，芯片FLASH与芯片SDRAM和SH背靠背地安置，以形成一个堆叠结构。确切地说，从安装基板方向看，芯片FLASH可以整体安装在芯片SDRAM和SH占据的安装表面区域中。因此，包括芯片FLASH在内的四个半导体芯片可以安装在安装基板上，而原来它只能容纳包括芯片ASIC在内的三个半导体芯片。
图3A和图3B是剖面图，示意性地显示了依据本发明的多芯片模块。图3A是沿着图1中箭头A观察的剖面图，而图3B是沿着图1中箭头B观察的剖面图。因此，图3A和图3B的图形横向上相互反转。如上所述，半导体芯片SH、SDRAM和ASIC是贴片式安装在安装基板的主表面上，而闪存FLASH则是通过热固胶等与半导体芯片SH和SDRAM背靠背地安装。半导体芯片的电极通过焊线(连接线)，连接到安装基板的对应电极。安装着半导体芯片SH、SDRAM、ASIC和FLASH的安装基板主表面，以一种密封材料封装，其中包含着焊线。
在图3A和图3B中，多芯片模块的外部端子虽然没有显示，却是外形为突起的电极，适于通过安装基板中形成的孔，导电连接到内部配线，并且排列在安装基板的另一个主表面(反面)。半导体芯片SH、SDRAM和ASIC的突起电极可以被称为微突起，其尺寸和间距相对较小，而为安装基板提供外部端子的突起电极，其尺寸和间距相对较大。
图4是一幅示意图，用于讲解依据本发明之多芯片模块的装配步骤。图4显示了装配步骤和对应的热滞现象以及一般的垂直结构。在裸芯片1的焊点上形成了一个金的突起。在MCM的基底电极上，附着一层各向异性的导电薄膜ACF，裸芯片的焊点上形成了金的突起之后，把它安装在MCM的基底上，以便进行热压焊接。裸芯片2通过一种热固胶背靠背地固定在裸芯片1上，并且通过丝焊连接到MCM基底的对应电极。虽然没有显示，装配结果却是如此以树脂封装。在最后的步骤中，通过回流处理，形成焊球作为外部端子，MCM就完成了。
图5是一幅框图，显示了依据本发明一个实施例的多芯片模块。在图5中，图1中微计算机SH、存储器SDRAM和闪存FLASH的电接点，与信号端子名称直观地显示在一起。
为了对图1所示的微计算机SH、存储器SDRAM(及数字信号器件ASIC)和闪存FLASH进行组合，以利用获得的特性来改善性能、减小多芯片模块的尺寸，相互交换信号的微计算机SH和存储器SDRAM(及数字信号器件ASIC)，由安装基板上形成的地址总线(13位)、数据总线(32位)和控制总线互相连接。
例如，十三(13)条地址总线对应于SDRAM的地址端子A0至A12，32条数据总线对应于SDRAM的数据端子DQ0至DQ31。微计算机SH使地址总线连接到地址端子A2至A14，使数据总线连接到端子D0至D31。
微计算机SH具有对应于存储器SDRAM的控制输出端子CKIO、CKE、CS3B、RASLB、CASLB、RD/WRB、WE3B/DQMUU、WE2B/DQMUL、WE1B/DQMLU和WE0B/DQMLL，连接到CLK、CKE、CSB、RASB、CASB、WEB和DQM7、DQM5、DQM2、DQM0。附带有B的端子名称对应的逻辑信号，用于使附图中带有一条上覆线的低活化电平上升到活化电平。端子WE3B/DQMUU、WE2B/DQMUL、WE1B/DQMLU和WE0B/DQMLL是屏蔽信号。具有32位的数据总线划分为四个8位的组，所以WE3B/DQMUU、WE2B/DQMUL、WE1B/DQMLU和WE0B/DQMLL用于选择性地屏蔽读写操作。
同时，数字信号器件ASIC基本上与地址总线和数据总线连接，并且具有一条信号线，用于按需发送控制信号。这个数字信号器件用于多芯片模块中特殊应用的数字信号处理，并且与微计算机SH协作，负责专门指定的信号处理。这些半导体芯片需要较高的信号传输率。如果半导体芯片是贴片式安装在配线上，比如在安装基板上形成的总线上，就形成了长度最短的信号传输路径，因而能够进行高速信号交换。因此实现了高性能。
在这个实施例中，微计算机SH包括一个接口，对应于闪存FLASH。确切地说，闪存FLASH包括一个数据端子I/O(7∶0)以及控制信号WEB、SC、OEB、RDY/BusyB和CEB。与此保持一致，微计算机SH也包括NA_IO(7∶0)以及控制信号NA_WEB、NA_SC、NA_OEB、NA_RYBY和NA_CEB。微计算机SH和闪存FLASH之间的读写操作，比与SDRAM的操作速度慢。所以，即使在焊线形成信号传输路径的情况下，对传输率也没有不利的影响。因此，MCM作为一个整体能够减小尺寸，同时改善其性能。
图6显示了依据本发明的一个实施例中多芯片模块所用安装基板上的配线图案。安装基板的结构是多层配线基底，比如说八层。在图6中，直观地显示了安装基板主表面的一部分，该处安装着半导体芯片，包括微计算机SH和存储器SDRAM。
在图6中，直线和折表示配线，黑色矩形表示焊点，用于连接闪存FLASH。符号*表示基板电极，用于贴片式安装半导体芯片，包括微计算机SH和存储器SDRAM。在图6的上部，如图2所示，排列着基板电极，对应于近似正方形的微计算机SH，而图6的下部排列的基板电极对应于横向较长的存储器SDRAM。在图6的左侧以垂直方向排列着焊接点。
在上述结构中，闪存FLASH背靠背地安装在微计算机SH和存储器SDRAM之上，但是并不限于整个闪存FLASH安装在SH和SDRAM的安装表面上。考虑到闪存FLASH的焊点沿着一侧长边排列的事实，安装基板的焊点也可以如图6所示排列。结果，也能够减小安装基板上形成的焊点占据的面积。
图9是一幅示意图，显示了在应用本发明之前研究的一个实施例中多芯片模块的布局。在这种情况下，微处理器CPU背靠背地安装在闪存FLASH和存储器SDRAM上。微处理器CPU具有多个外部端子，沿着芯片的外围排列。所以，对应于CPU之焊点的多个焊点，需要分布地排列在安装基板上闪存FLASH和存储器SDRAM之外。因此，不必要地增加了安装基板上焊点占据的面积。
另一方面，从电路操作性能的观点，微处理器CPU需要高速传送信号的信号传输路径，包括了相对较长的焊线。这就产生了以下问题：焊线的电感分量相对较大，对高频时钟和与时钟同步之信号的传输率产生了不利的影响。相反，在依据本发明的多芯片模块中，一方面能够减小安装基板的尺寸，另一方面能够提高电路操作的性能。不过，申请人并不倾向于承认图9中的实例作为规章中的现有技术。
图7显示了依据本发明的一个实施例中一个闪存的焊接点布局。焊点PAD1至PAD34排列在矩形基板的较长一侧(底边)。除了图5所示的信号焊点之外，也包括电源电压VCC、VSS和操作电压的焊点。
图8显示了依据本发明的一个实施例中多芯片模块的一般外形。例如，多芯片模块薄至1.65mm，最厚为1.70mm，并且在反面具有焊球，组成总数为395的外部端子(针脚)。每个焊球触点(平面)的直径φ为0.33mm，排列间距为0.65mm。
下面将要讲解一个基板栅格阵列(LGA)型多芯片模块的实例，其中在安装基板的反面，使用金(Au)/焊料(Sn等)，使半导体芯片和安装基板相互连接，而不使用任何球形的突起电极。
如图10所示，与以上参考图1至图8介绍的MCM相比，按照这个实施例的MCM，除了以下介绍的差异之外，具有基本上类似的结构。确切地说，每个金钉突起1都通过连接材料，连接到触点4，既可导电，又可受力。在半导体芯片5和安装基板3之间，填充了一种下充树脂6，以便降低对半导体芯片5的损害，否则由于安装基板3和半导体芯片5之间的热传导系数差异，它会受到热应力集中造成的损害。另外，在安装基板的反面形成了平面电极7，作为外部端子，用于导电连接例如一片印刷电路板(PCB)。
按照这个实施例，没有形成图1至图8所示的球形突起电极，所以本模块能够有利地减小尺寸和厚度。虽然没有显示，但是在平面电极7的表面上可以形成Cr/Cu/Au等材料的屏障层。在这个实施例中，显示了单一的半导体芯片5作为代表情况，并且通过倒装芯片连接把SH、SDRAM和ASIC中的每一个都安装在安装基板3上。
安装基板3的结构主要有一片刚性的基底(核心基底)8，在刚性基底8的两个相对表面上通过堆积方法形成的柔软层9、10，以及以覆盖柔软层9、10的方式形成的保护膜11、12。虽然没有详细显示，但是刚性基底8和柔软层9、10具有例如一种多层配线结构。例如，使聚酰亚胺树脂或环氧树脂注入玻璃纤维产生的高弹性树脂基底，形成了刚性基底8的每一个绝缘层，而低弹性的环氧树脂形成了柔软层9、10的每一个绝缘层。
以上介绍的刚性基底8和柔软层9、10多层结构中的每一层配线，都是由例如铜(Cu)金属膜形成的。保护膜11、12是由例如聚酰亚胺树脂形成的，其主要的目的是保护柔软层9最上面配线层中形成的配线，并且意在一方面在封装时确保粘性树脂与半导体芯片粘结，另一方面在封装中控制湿焊料的膨胀。形成保护膜12主要是为了保护柔软层10最上面配线层中形成的配线，并且在平面电极7与焊料封装时控制湿焊料的膨胀。
虽然没有限制，但是半导体芯片5的结构主要有一片半导体基底，在半导体基底的一个主表面上形成的多个半导体器件，多重配线层(包括在半导体基底的一个主表面上在多个阶段中堆积的多个绝缘层和配线层)，以及以覆盖多重配线层的方式形成的一层表面保护膜(最终保护膜)。半导体基底是由例如单晶硅形成的，绝缘层是由例如氧化硅膜形成的，而配线层是由例如铝(Al)或铝合金的金属膜形成的。表面保护膜是由例如氧化硅或氮化硅的绝缘膜或者一种有机绝缘膜形成的。
与半导体芯片5的一个主表面(反面)呈相对关系的另一个主表面上，形成了多个电极焊点13。这多个电极焊点13是在半导体芯片5之多重配线层的最上配线层上形成的，并且暴露在半导体芯片5的表面保护膜上形成的焊接开口中。多个电极焊点13沿着半导体芯片5的每一侧排列。多个电极焊点13中的每一个，都形成一个比如说边长70μm的正方形平面。同时，这多个电极焊点13的排列间距大约为85μm。
例如，金(Au)钉突起1排列为半导体芯片5的一个主表面上的突起电极。多个钉突起1分别排列在多个电极焊点13上，后者排列在半导体芯片5的一个主表面上，所以这些钉突起1与电极焊点13相互连接，既可导电，又可受力。金线钉突起1是由球焊方法形成的，例如同时使用热焊和超声波振动。在球焊方法中，在每条金线的前端形成一个球，然后这个球在超声波振动下加热焊接在芯片的电极焊点上，再从球处把金线切断，从而形成一个突起。所以，在电极焊点上形成的钉突起就牢固地连接到电极焊点上。
下面将参考图11至图13，讲解以上介绍的MCM的制造过程。图11至图13是显示了基本部件的剖面图，用于讲解MCM的制造过程。如图11所示，在安装基板3的一个主表面上芯片安装区域中排列的每个触点4上，由分配方法供应例如一种糊状的连接材料2。一种焊料糊状材料用作连接材料2。制造这种焊料糊状材料，是通过对至少精细的焊料微粒和溶剂进行混合与揉捏。这个实施例使用的焊料糊状材料，是通过混合与揉捏焊料微粒制成的，它含有98％重量的铅(Pb)和2％重量的锡(Sn)，熔点大约300℃。分配方法是从一个细喷嘴中射出焊料糊状材料，用于涂布。
下一步，如图12所示，安装基板3安放在一个加热台14上，然后一个夹头15把半导体芯片5搬运到芯片安装区域，并且使钉突起1对准对应的触点4。接着，由加热台14加热安装基板3，同时由夹头15加热半导体芯片5。以这种方式，如图13所示，连接材料2熔化，然后熔化的连接材料2固结。结果，半导体芯片5就封装在安装基板3一个主表面上的芯片安装区域中。
如图10所示，一种下充树脂6填充在安装基板3一个主表面上的芯片安装区域和半导体芯片5之间。然后，如同图1至图8所示的MCM，闪存FLASH背靠背地堆叠在半导体芯片5上。然后，闪存FLASH的电极焊点通过丝焊连接到安装基板3的触点4上。在最后一步中，利用树脂对四个半导体芯片SH、SDRAM、ASIC和FLASH以及焊线进行封装，从而基本上完成了MCM。
把LGA型MCM安装到印刷电路板(PCB)时，在PCB一面的连接电极上，通过印刷等工艺形成一层焊料，而且在LGA型MCM的反面形成的平面电极对准PCB一面的连接电极。然后，通过焊料回流，由焊料使这些连接电极相互连接。另外，也可以通过印刷等工艺，在LGA型MCM的平面电极上事先形成一个焊料薄层。
虽然图1和图2仅仅显示了四个芯片，包括SH、SDRAM、ASIC和FLASH，但是也可以另外安装一个用于外围电路的芯片。在这样一种情况下，用于外围电路的芯片是面向下，通过突起的电极比如金钉突起1安装在安装基板上，与SH、SDRAM或ASIC的方式相同，使得外围电路连接到图5所示SH和ASIC共享的地址总线和数据总线。
确切地说，面向下由突起连接的芯片SH、SDRAM、ASIC和外围电路，由公共总线相互连接，从而改善了模块的操作速度。相反，堆叠在至少一个芯片上的闪存FLASH，是通过焊线连接到安装基板的电极焊点上，并且通过仅仅与SH独立连接的专用总线接口连接到SH，以减小模块尺寸。
以上具体地参考若干实施例，介绍了本发明人实现的发明。不过，本发明不限于以上介绍的实施例，并且在不脱离本发明的实质和范围的情况下，可以减小多种修改。例如，多芯片模块上可以安装一个与CPU协同操作的数字信号处理器(DSP)等协处理器，以取代ASIC。在这种情况下，CPU和数字信号处理器通过一个控制信号，以密切关系操作。经过以上介绍的加压，通过基板配线使CPU和数字信号处理器互连，所以能够实现高性能。对于构成多芯片模块的半导体器件，本发明具有广泛的应用。
下面将简要介绍本文公开的本发明的典型方面获得的效果。用于交换信号的多个第一种半导体芯片，贴片式安装在安装基板的表面上，大部分焊接点沿着一侧排列的一个第二种半导体芯片，与至少一个第一种半导体芯片以背靠背关系安装，使得这些焊接点和安装基板上形成的对应电极由丝焊相互连接。在安装基板上的第一种和第二种半导体芯片以及焊线，以一种密封材料封装，从而使多芯片模块实现性能高和尺寸小。

Claims (5)

1.一种多芯片模块，包括：
多个第一种半导体芯片，贴片式安装在一片安装基板的表面上，以便相互交换信号；
一个第二种半导体芯片，与所述多个第一种半导体芯片中的至少一个背靠背安装，所述第二种半导体芯片的大部分焊接点沿着其一侧排列；
若干焊线，用于连接所述第二种半导体芯片的焊接点和在所述安装基板上形成的对应电极；以及
一种密封组件，用于封装所述安装基板上的所述多个第一种半导体芯片、所述第二种半导体芯片和所述焊线。
2.根据权利要求1的多芯片模块，
其特征在于，所述多个第一种半导体芯片分别包括一台微计算机、一个随机访问存储器和用于为特定应用处理信号的一个信号处理器件，以及
其中，所述第二种半导体芯片是一个非易失性存储器。
3.根据权利要求2的多芯片模块，
其特征在于，所述微计算机与连接到所述微计算机的所述随机访问存储器或所述用于为特定应用处理信号的信号处理器件，由安装基板上经过加压而形成的配线互连；以及
其中，所述微计算机包括一个专用接口，对应于所述非易失性存储器，所述微计算机与所述非易失性存储器通过所述焊线互连。
4.根据权利要求3的多芯片模块，
其特征在于，所述非易失性存储器与包括所述微计算机的所述第一种半导体芯片背靠背地安装。
5.根据权利要求4的多芯片模块，
其特征在于，与所述非易失性存储器背靠背地安装的所述第一种半导体芯片包括所述微计算机和所述随机访问存储器；以及
其中，组成所述随机访问存储器的半导体芯片的较长边与组成所述非易失性存储器的半导体芯片的较长边相互正交地安置。
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