CN102439718B - 数据存储装置 - Google Patents
数据存储装置 Download PDFInfo
- Publication number
- CN102439718B CN102439718B CN201080013913.7A CN201080013913A CN102439718B CN 102439718 B CN102439718 B CN 102439718B CN 201080013913 A CN201080013913 A CN 201080013913A CN 102439718 B CN102439718 B CN 102439718B
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- Prior art keywords
- flash memory
- memory component
- data storage
- storage device
- stacking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000013500 data storage Methods 0.000 title claims abstract description 48
- 230000015654 memory Effects 0.000 claims abstract description 113
- 238000010276 construction Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 8
- 238000009826 distribution Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 208000005168 Intussusception Diseases 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 238000012546 transfer Methods 0.000 abstract description 2
- 238000003860 storage Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000000712 assembly Effects 0.000 description 4
- 238000000429 assembly Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- RPPNJBZNXQNKNM-UHFFFAOYSA-N 1,2,4-trichloro-3-(2,4,6-trichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC(Cl)=C1C1=C(Cl)C=CC(Cl)=C1Cl RPPNJBZNXQNKNM-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004193 electrokinetic chromatography Methods 0.000 description 1
- 108010025899 gelatin film Proteins 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201080013913.7A CN102439718B (zh) | 2010-06-25 | 2010-07-30 | 数据存储装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2010/074540 WO2011160311A1 (en) | 2010-06-25 | 2010-06-25 | Memory device |
CNPCT/CN2010/074540 | 2010-06-25 | ||
CN201080013913.7A CN102439718B (zh) | 2010-06-25 | 2010-07-30 | 数据存储装置 |
PCT/CN2010/075602 WO2011160321A1 (en) | 2010-06-25 | 2010-07-30 | Data storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102439718A CN102439718A (zh) | 2012-05-02 |
CN102439718B true CN102439718B (zh) | 2015-07-01 |
Family
ID=45986246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201080013913.7A Active CN102439718B (zh) | 2010-06-25 | 2010-07-30 | 数据存储装置 |
Country Status (1)
Country | Link |
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CN (1) | CN102439718B (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453841A (zh) * | 2002-03-28 | 2003-11-05 | 三因迪斯克公司 | 改进的存储器封装 |
CN1967709A (zh) * | 2005-11-18 | 2007-05-23 | 尔必达存储器株式会社 | 堆叠存储器 |
CN101088311A (zh) * | 2004-12-23 | 2007-12-12 | 英特尔公司 | 存储模块布线 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002176135A (ja) * | 2000-12-07 | 2002-06-21 | Toshiba Corp | 積層型の半導体装置とその製造方法 |
TW498470B (en) * | 2001-05-25 | 2002-08-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaging with stacked chips |
JP2004179442A (ja) * | 2002-11-28 | 2004-06-24 | Renesas Technology Corp | マルチチップモジュール |
KR100688514B1 (ko) * | 2005-01-05 | 2007-03-02 | 삼성전자주식회사 | 다른 종류의 mcp를 탑재한 메모리 모듈 |
US7826243B2 (en) * | 2005-12-29 | 2010-11-02 | Bitmicro Networks, Inc. | Multiple chip module and package stacking for storage devices |
US8472199B2 (en) * | 2008-11-13 | 2013-06-25 | Mosaid Technologies Incorporated | System including a plurality of encapsulated semiconductor chips |
-
2010
- 2010-07-30 CN CN201080013913.7A patent/CN102439718B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453841A (zh) * | 2002-03-28 | 2003-11-05 | 三因迪斯克公司 | 改进的存储器封装 |
CN101088311A (zh) * | 2004-12-23 | 2007-12-12 | 英特尔公司 | 存储模块布线 |
CN1967709A (zh) * | 2005-11-18 | 2007-05-23 | 尔必达存储器株式会社 | 堆叠存储器 |
Also Published As
Publication number | Publication date |
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CN102439718A (zh) | 2012-05-02 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: SIMPLO TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: BIWIN TECHNOLOGY LTD. Effective date: 20130708 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20130708 Address after: The British Virgin Islands of Tortola Rodez P.O. Box 4389 Applicant after: Simplo Technology Co., Ltd. Address before: Hongkong, China Applicant before: Biwin Technology Ltd. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151109 Address after: 518000, Guangdong, Nanshan District, Taoyuan Shenzhen street, with the rich industrial city, No. 4 factory building, 1 floor, 2 floor, 4 floor, 5 floor Patentee after: Biwin Storage Technology Limited Address before: The British Virgin Islands of Tortola Rodez P.O. Box 4389 Patentee before: Simplo Technology Co., Ltd. |
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C56 | Change in the name or address of the patentee | ||
CP03 | Change of name, title or address |
Address after: 518055, Guangdong, Nanshan District, Taoyuan Shenzhen street, with the rich industrial city, No. 4 factory building, 1 floor, 2 floor, 4 floor, 5 floor Patentee after: Shenzhen Bai dimensional storage Polytron Technologies Inc Address before: 518000, Guangdong, Nanshan District, Taoyuan Shenzhen street, with the rich industrial city, No. 4 factory building, 1 floor, 2 floor, 4 floor, 5 floor Patentee before: Biwin Storage Technology Limited |
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CP02 | Change in the address of a patent holder |
Address after: 518000 floors 1-3 and 4 of buildings 4 and 8, zone 2, Zhongguan honghualing Industrial South Zone, No. 1213 Liuxian Avenue, Pingshan community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee after: BIWIN STORAGE TECHNOLOGY Co.,Ltd. Address before: 518055 1st floor, 2nd floor, 4th floor, 5th floor, No.4 factory building, tongfuyu industrial city, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: BIWIN STORAGE TECHNOLOGY Co.,Ltd. |
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CP02 | Change in the address of a patent holder |