CN102891139A - 双侧倒装芯片封装 - Google Patents

双侧倒装芯片封装 Download PDF

Info

Publication number
CN102891139A
CN102891139A CN201210252290XA CN201210252290A CN102891139A CN 102891139 A CN102891139 A CN 102891139A CN 201210252290X A CN201210252290X A CN 201210252290XA CN 201210252290 A CN201210252290 A CN 201210252290A CN 102891139 A CN102891139 A CN 102891139A
Authority
CN
China
Prior art keywords
module
electronic
electrically connected
group
electric conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201210252290XA
Other languages
English (en)
Inventor
翟军
V·R·万卡纳尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of CN102891139A publication Critical patent/CN102891139A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1713—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及双侧倒装芯片封装。具有安装在衬底的相对两侧的两个或更多集成电路管芯的半导体器件模块。集成电路管芯通过使用诸如使用导电突起来实现的倒装芯片连接之类的表面安装连接来安装。系统可包括当前半导体器件模块中的一个或多个，并且在某些情况下，还可包括诸如系统模块之类的其他模块。

Description

双侧倒装芯片封装
技术领域
本公开一般涉及半导体器件，更具体而言，涉及多管芯（multi-die）模块。
背景技术
诸如，例如DDR存储器封装之类的器件封装的容量可以通过增加每个封装的集成电路管芯（integrated circuit die）的数量而改善。例如，一对或多对层叠的管芯可以在存储器封装内实现，以与具有未层叠的管芯的存储器封装相比增加存储器容量，而不会显著增加封装的占用空间。这样的层叠的存储器封装通常使用用于将管芯连接到模块衬底的丝焊（wire bonding）。
集成电路（IC）器件的倒装芯片连接可以提供理想的电感特性（例如，较低的信号和/或功率电感（power inductance））。此外，连接密度可以比丝焊集成电路器件所提供的连接密度大得多。倒装芯片连接可以使用设置在管芯的一个表面上的导电突起来便于到衬底的连接。如此，倒装芯片连接可能不很适合于典型的层叠的管芯配置。
发明内容
公开了提供具有安装在衬底的相对两侧的两个或更多集成电路管芯的半导体器件封装的各种结构和技术。这些集成电路管芯通过使用诸如使用导电突起来实现的倒装芯片连接之类的表面安装连接来安装。在某些实施例中，所公开的结构和技术可以促进封装内的较高的器件密度，而同时提供降低的电感值和改善的连接器密度。
电子器件模块的一个实施例可包括通过倒装芯片连接而电连接到模块衬底的第一表面的第一管芯，以及也通过倒装芯片连接而电连接到模块衬底的基本上相对的第二表面的第二管芯。特定实施例还可以在模块衬底的第一侧上包括导体，以便于电子器件模块到外部组件的连接。其他实施例可包括设置在模块衬底的除第一表面以外的一个或多个表面上的导体，用于进行外部连接。一些实施例可以被配置成通过设置在模块衬底的一个以上的表面上的导体来进行外部连接。例如，一个这样的实施例可以是包括安装在模块衬底的相对表面上的两个或更多DDR管芯倒装芯片的存储器模块，其中，存储器模块被配置成连接到包括片上系统（SOC）的系统模块。在某些情况下，特定存储器模块可以被进一步配置成连接到诸如另一个存储器模块之类的第三模块，从而便于包括SOC以及两个存储器模块的系统。
在特定实施例中，电子器件模块可包括电连接到模块衬底的第一组导体的第一集成电路，以及电连接到模块衬底的第二组导体的第二集成电路。第一和第二组导体可以是设置在模块衬底的基本上相对的表面上，并可以使用诸如焊料突起（solder bump）之类的导电突起（conductive bump）电连接到第一和第二集成电路。一些实施例可包括电连接到模块衬底的额外的集成电路。在某些实施例中，模块衬底还包括一组或多组被配置成进行外部连接的电导体（例如，被配置成到SOC模块、存储器模块、或其他模块的连接）。在某些情况下，一组或多组电导体可以被配置成使用一个或多个球栅阵列来进行连接。
在本公开的某些实施例中，系统可包括电连接到第二模块的第一模块。模块可以通过设置在第一模块衬底上的一组电导体进行连接。除第一模块衬底之外，第一模块可包括第一管芯和第二管芯。第一和第二管芯可以分别通过倒装芯片连接而电连接到第一模块衬底的相对表面。在某些实施例中，第二模块可包括SOC。在各实施例中，第一模块可以是存储器模块。
附图说明
下面的详细描述将参考现在被简短地描述的各个附图。
图1描绘了根据本公开的一个实施例的系统。所描绘的系统包括具有相对地安装到模块衬底的两个集成电路的第一模块、以及耦合到所述第一模块的第二模块。
图2描绘了包括安装到模块衬底的三个管芯的模块。三个安装的管芯包括使用导电突起安装到模块衬底的第一侧的两个管芯、以及使用导电突起安装到模块衬底的第二侧的第三管芯。模块衬底还包括用于将电连接提供到模块外部的组件的导体。
图3是从图2的线3-3查看的图2中所描绘的实施例的各种组件的底视图。描绘了设置在模块衬底的表面上的电导体。电导体包括一组用于连接到模块外部的组件的导体、一组用于连接到第一管芯的导体、以及一组用于连接到第二管芯的导体。
图4描绘了包括安装到模块衬底的两个集成电路的模块。两个集成电路包括使用导电突起安装到模块衬底的第一侧的IC、以及使用导电突起安装到模块衬底的第二侧的第二IC。模块衬底还包括位于偏移并平行于模块衬底的第一侧的用于提供到模块的外部的组件的电连接的导体。
图5是从图4的线5-5查看的图4中所描绘的实施例的底视图。用于连接到外部组件的电导体被描绘成被设置在模块衬底的相对于所描绘的IC被安装到的表面而偏移的表面上。电导体包括一组用于连接到模块外部的组件的导体、一组用于连接到第一管芯的导体、以及一组用于连接到第二管芯的导体。
图5是从图4的线5-5查看的图4中所描绘的实施例的底视图。用于连接到外部组件的一组电导体被描绘成被设置在模块衬底的相对于所描绘的IC被安装到的表面而偏移的表面上。所述模块还包括一组用于连接到第一管芯的导体、以及一组用于连接到第二管芯的导体。
图6描绘了根据本公开的一个实施例的具有三个模块的系统。所描绘的系统包括具有六个管芯的第一模块，三个管芯被安装在模块衬底的两个相对的一侧中的每一侧。具有一个管芯的第二模块被描绘成耦合到第一模块。第一模块还耦合到第三模块，该第三模块包括安装到第三模块的衬底的相对的两侧的两个管芯。第一模块包括充当用于便于到第二和第三模块的连接的隔离（stand off）的偏移表面。球栅阵列连接用于所描绘的实施例中的第一模块和第二和第三模块之间的连接中。
在附图中作为示例示出了特定实施例，并在此处详细地进行描述。然而，应了解附图和详细描述不旨在将权利要求限制到所公开的特定实施例，尽管参考特定特征只描述单一实施例。相反，可以覆盖对受益于本公开优点的所属技术领域的专业人员显而易见的所有修改、等效内容和替代方案。本公开中所提供的特征的示例只是说明性的，而并非限制性的，除非特别声明。
此处所使用的标题只用于组织目的，不用于限制描述的范围。如在本申请全篇中所使用的，词语“可以”用于许可的意义（即，表示具有可能性做某事），而不是强制性的意义（即，表示必须）。词语“包括”表示开放的关系，因此意味着包括但不仅限于。类似地，词语“具有”也表示开放的关系，如此意味着具有但不仅限于。如此处所使用的术语“第一”、“第二”、“第三”等等被用作它们后面的名词的标记，并不暗示任何类型的排序（例如，空间、时间、逻辑等等），除非这样的排序以别的方式明确地表示。例如，“电连接到模块衬底的第三管芯”不排除其中“电连接到模块衬底的第四管芯”在第三管芯之前被连接的情形，除非另作说明。类似地，“第二”特征也不要求“第一”特征在“第二”特征之前实现，除非另作说明。
各种组件可以被描述为“被配置成”执行一个或多个任务。在这样的上下文中，“被配置成”是一般意味着“具有在操作期间执行任务的结构”的广泛的列举。如此，组件可以被配置成执行任务，甚至在该组件当前不正在执行该任务的情况下（例如，一组电导体可以被配置成将一个模块电连接到另一个模块，甚至在两个模块不连接的情况下）。在一些上下文中，“被配置成”可以是一般意味着“具有在操作期间执行任务的电路”的结构的广泛的列举。如此，组件可以被配置成执行任务，甚至在组件当前没有被接通的情况下。一般而言，构成对应于“被配置成”的结构的电路可包括硬件电路。
在描述中，为了方便起见，各种组件可以被描述为执行一个或多个任务。这样的描述应该被解释为包括短语“被配置成”。列举被配置成执行一个或多个任务的组件明确地不打算援引35U.S.C,§112，段落6，对于该组件的解释。
本公开的范围包括此处所公开的任何特征或特征组合（显式地或者隐式地），或其任何概括，不管它是否减轻此处所解决的任何或者全部问题。相应地，可以在本申请（或对其要求优先权的申请）的审查过程期间形成新权利要求。具体而言，参考所附权利要求，来自从属权利要求的特征可以与独立的权利要求的特征相结合，以及来自相应的独立权利要求的特征可以以任何适当的方式组合，而并非只是以在所附权利要求中所枚举的特定的组合。
具体实施方式
本说明书包括对“一个实施例”或“实施例”的引用。短语“在一个实施例中”或“在实施例中”的出现不一定必须都是指同一个实施例。此外，根据本公开，特定功能、结构或特征可以以任何合适的方式组合起来。
转向图1，示出了系统1的实施例的图示。如所描绘的，多模块系统1包括通过使用模块导体130的连接电耦合到模块20的电子器件模块10。作为一个示例，模块20可以是包括集成电路管芯22（例如，处理器）的系统模块，而电子器件模块10可以是具有多个集成电路管芯200（例如，存储器IC）的模块（例如，存储器模块）。在某些实施例中，模块20可包括集成电路管芯22，它是片上系统。各实施例可包括电子器件模块10和/或提供诸如，例如，图形控制、数字信号处理，以及通信协议功能之类的其他功能的模块20。
电子器件模块10可以向系统1提供可配置性。例如，考虑其中处理器和存储器被设置在共同封装共同衬底上的以前的系统。在这样的系统中，可能需要包括处理器和存储器的固定配置的共同封装的库存（inventory），以在可以接受的前置时间（lead time）内满足产品需求。可能要求表示处理器和存储器的不同组合的许多固定配置。固定配置的存储的库存可以表示由于可能的组件价格变化、组件产品演进、以及组件退化所造成的库存风险。例如，包括特定的存储器集成电路的存储的共同封装可以由于发行性能更好的存储器或价格变化而变得不合乎需要。
使用存储器模块和处理器模块的当前示例性系统可以通过允许由与从各种模块组装系统相关联的较短的前置时间所产生的降低的库存的存储来降低库存风险。此外，随着特定模块的组件变得过时，当前示例性系统的其他模块不受影响。例如，特定存储器产品的退化只导致相对应的存储器模块的退化，而不导致处理器模块或其他存储器模块的退化。
相比之下，上文所讨论的以前的共同封装的库存可能由于过时的存储器集成到共同封装中而变得过时。由于处理器也被集成到共同封装中，存储器的可能的退化也导致与集成的处理器有关的库存风险。
此外，本实施例的模块可以提供用于测试和采购的优选的单元。例如，由存储器供应商所提供的根据本公开的存储器模块为该存储器供应商提供了在模块级别而不是只在管芯级别进行质量保证的机会。相应地，可以通过在提供给客户之前由供应商执行的更高级别的测试来提高效率。因此，在组装期间与缺陷产生相关联的各种风险可以转移到模块供应商。
可以使用各种互连格式，通过模块导体130，来实现电子器件模块10和模块20之间的电连接。例如，系统1的各实施例可包括使用球栅阵列、针栅阵列、触点栅阵列、双列直插式封装、或其他合适的互连形状因子、电耦合的电子器件模块10和模块20。在某些情况下，系统1的各实施例可包括使用多个不同互连格式的多个模块导体130。模块导体130可以相对于模块衬底100的表面110对称地排列（参见图3），或者，在某些情况下，可以相对于表面110不对称地排列。系统导体24可以便于系统1与诸如系统板之类的外部组件的连接。在某些实施例中，系统导体24可以包括在模块导体130中所使用的相同互连格式。在其他实施例中，系统导体24可以使用与在模块导体130中所使用的互连格式不同的（或额外的）的互连格式。
转向图2，电子器件模块10的所描绘的实施例包括使用导电突起210安装到模块衬底100的三个集成电路管芯200。集成电路管芯200a和集成电路管芯200c使用导电突起210a和导电突起210b电连接到模块衬底100的表面110a。集成电路管芯200b使用导电突起210b电连接到与模块衬底100上的表面110a相对的表面110b。被配置成向诸如模块20之类的外部组件提供电耦合的模块导体130设置在表面110a上。
导电突起210可包括通过使用，例如回流焊接过程（reflow solderprocess）的超声波形成的倒装芯片连接，在集成电路管芯200和模块衬底100之间提供电连接。在某些实施例中，倒装芯片连接可以使用其他突起（例如，金球突起）及其他工艺（例如，导电膜或导电带）来形成。
倒装芯片连接的使用与替换的连接方法相比提供了多个优点。例如，倒装芯片连接可以比丝焊连接短得多。相应地，可以实现提供较低的电感值（例如，功率电感和信号电感）的设计。此外，在倒装芯片实现中管芯的整个一侧用于放置导电突起提供了比丝焊通常可用的导体密度更高的导体密度（例如，更大数量的输入/输出信号和电源/接地信号）的机会。
集成电路管芯200在模块衬底100的相对的两侧的安装可以允许集成电路管芯200在电子器件模块10和系统1的特定占用空间内的密度增大。可以通过集成电路管芯200的这样的双侧安装来促进的密集配置可以适应在诸如移动设备之类的形状因子敏感的实现中所施加的紧凑设计约束。在电子器件模块10的特定实施例中，可以使用各种集成电路管芯200安装配置，包括不同数量的管芯的对称或不对称配置。例如，图1、4、以及6各自都描绘了具有安装在模块衬底的两个相对的表面中的每一个表面上的一个管芯的模块。参见图1，元件10；图4，元件10；图6，元件30。图2描绘了其中在模块衬底的第一表面上安装了一个管芯，以及在相对表面上安装了两个管芯的实施例。图6的元件10包括安装在模块衬底的相对的两侧中的每一侧上的三个管芯。
在某些实施例中，电子器件模块10可包括安装在模块衬底100上的多个相同的集成电路管芯200。一个这样的实施例是其中相同的存储器集成电路可以被用来提供供片上系统使用的存储装置的存储器模块。电子器件模块10的其他实施例可包括安装在模块衬底100上的各种集成电路管芯200。例如，特定存储器模块可以被配置成向耦合的系统提供分开的系统存储器和图形存储器。在此特定示例性存储器模块中，可以使用一个或多个特定集成电路来提供系统存储器，以及可以使用一个或多个不同的集成电路来提供图形存储器。电子器件模块10的其他实施例可包括提供除存储器以外的功能，诸如，例如，图形控制、数字信号处理以及通信协议功能的集成电路管芯200。
图3描绘了从图2的线3-3查看的模块衬底100的表面110a。示出了设置在模块衬底的表面上的电导体。电导体包括对应于用于电连接到集成电路管芯200a的导电突起210a的衬底导体120a。类似地，衬底导体120b对应于用于电连接到集成电路管芯200b的导电突起210b。虽然在图3中所描绘的实施例中，衬底导体120a和衬底导体120b是类似的阵列，但是其他实施例可包括具有不同于那些所描绘的、和/或彼此不同的图案的衬底导体120。虚线表示当安装到模块衬底100时集成电路管芯200a的略图，以及集成电路管芯200b轮廓。集成电路管芯200的安装可包括使用绝缘体的底层填充。
现在转向图4和5，描绘了电子器件模块10的替换实施例。与图2和3所示出的包括设置在模块衬底100的表面110处的模块导体130的实施例不同，图4和5的实施例包括设置在表面110c处的模块导体130。表面110c可以偏移表面110a，如此在集成电路管芯200a和电子器件模块10连接到的组件之间提供额外的间隙。例如，模块衬底100的配置可包括隔离（standoff）以适应集成电路管芯200a和电子器件模块10可以连接到的系统板或模块的组件之间的间隙。图3的实施例包括沿表面110的周边对称地排列的模块导体130，而图5的实施例包括在模块衬底100的两个边缘附近对称地排列的模块导体130。其他实施例可包括按其他配置，包括不对称配置，排列的模块导体130。各实施例还可包括诸如球栅阵列、针栅阵列、触点栅阵列、双列直插式封装或其他合适的互连形状因子之类的各种形状因子的模块导体130。
图6描绘了系统1的包括通过模块导体130a电耦合到模块20，以及通过模块导体130b耦合到器件模块30的电子器件模块10的实施例。电子器件模块10包括如此配置的模块衬底，以便在安装在电子器件模块10上的集成电路和安装在模块20和器件模块30上的集成电路之间提供间隙。在某些实施例中，模块20可包括片上系统封装，电子器件模块10和模块20是串联地层叠在系统封装之上的存储器封装。在其他实施例中，电子器件模块10可以是系统封装，模块20和器件模块30是层叠在系统封装的任一侧的存储器封装。一些实施例可包括层叠在器件模块30上方和/或模块20下方的额外的封装。特定实施例可包括具有执行不同的或附加功能，包括例如控制、信号处理，以及电源相关的功能的集成电路的封装。
虽然非常详细地描述了上文的实施例，但是一旦完全理解了以上公开，很多变化和修改方案对于那些本领域的技术人员将变得显而易见。下面的权利要求应被解释为包括所有这样的变化和修改方案。

Claims (20)

1.一种电子器件模块，包括：
包括第一表面、基本上与所述第一表面相对的第二表面、以及被配置成电连接所述电子器件模块的第一组电导体的模块衬底；
通过与所述模块衬底的所述第一表面的倒装芯片连接，电连接到所述模块衬底的第一管芯；以及
通过与所述模块衬底的所述第二表面的倒装芯片连接，电连接到所述模块衬底的第二管芯。
2.如权利要求1所述的电子器件模块，其中，所述第一组电导体被配置成将所述电子器件模块电连接到包括片上系统的模块。
3.如权利要求2所述的电子器件模块，还包括：
被配置成将所述电子器件模块电连接到另一个模块的第二组电导体，其中，所述第二组电导体被配置成从基本上与连接所述包括片上系统的模块的方向相反的方向电连接所述电子器件模块。
4.如权利要求1所述的电子器件模块，其中，所述第一组电导体被设置在所述模块衬底的所述第一表面上，以及其中，所述第一组导体被配置成使用球栅阵列电连接所述电子器件。
5.如权利要求1所述的电子器件模块，其中，所述第一组电导体至少部分地被设置在所述模块衬底的第三表面上，所述第三表面不同于所述第一表面并且基本上平行于所述第一表面。
6.如权利要求1所述的电子器件模块，其中，所述第一管芯包括存储器。
7.如权利要求1所述的电子器件模块，还包括：
通过与所述模块衬底的所述第一表面的倒装芯片连接，电连接到所述模块衬底的第三管芯；以及
通过与所述模块衬底的所述第二表面的倒装芯片连接，电连接到所述模块衬底的第四管芯；
其中，所述第一管芯、第二管芯、第三管芯、以及第四管芯各自都包括存储器。
8.一种电子器件模块，包括：
模块衬底，包括：
设置在所述模块衬底的第一表面上的第一组电导体；以及
设置在所述模块衬底的第二表面上的第二组电导体，所述第二表面基本上与所述第一表面相对；以及
第三组电导体；
使用第一组焊料突起，电连接到所述模块衬底的所述第一组电导体的第一集成电路；以及
使用第二组焊料突起，电连接到所述模块衬底的所述第二组电导体的第二集成电路；
其中，所述电子器件模块被配置成通过所述模块衬底的所述第三组电导体电连接。
9.如权利要求8所述的电子器件模块，其中，所述第三组电导体被配置成将所述电子器件模块电连接到包括片上系统的模块。
10.如权利要求9所述的电子器件模块，其中，还包括：
被配置成将所述电子器件模块电连接到另一个模块的第四组电导体，其中，所述第四组电导体被配置成从基本上与所述包括所述片上系统的模块被连接的所述方向相反的方向电连接所述电子器件模块。
11.如权利要求8所述的电子器件模块，其中，所述第三组电导体被设置在所述模块衬底的所述第一表面上。
12.如权利要求8所述的电子器件模块，其中，所述第三组电导体至少部分地被设置在所述模块衬底的第三表面上，所述第三表面不同于第一表面，并基本上平行于所述第一表面。
13.如权利要求8所述的电子器件模块，其中，所述第一集成电路包括存储器。
14.如权利要求8所述的电子器件模块，其中，还包括：
使用第三组焊料突起，电连接到设置在所述模块衬底的所述第一表面上的电导体的第三集成电路；以及
使用第四组焊料突起，电连接到设置在所述模块衬底的所述第二表面上的电导体的第四集成电路；
其中，所述第一集成电路、第二集成电路、第三集成电路、以及第四集成电路各自都包括存储器。
15.一种系统，包括：
第一模块，包括：
包括第一表面、基本上与所述第一表面相对的第二表面、以及第一组电导体的第一模块衬底；
通过与所述第一模块衬底的所述第一表面的倒装芯片连接，电连接到所述第一模块衬底的第一管芯；以及
通过与所述第一模块衬底的所述第二表面的倒装芯片连接，电连接到所述第一模块衬底的第二管芯；以及
通过所述第一模块衬底的所述第一组电导体，电连接到所述第一模块的第二模块，所述第二模块包括第二模块衬底。
16.如权利要求15所述的系统，其中，所述第二模块还包括：
片上系统。
17.如权利要求15所述的系统，其中，所述第二模块是封装中的系统。
18.如权利要求15所述的系统，其中，所述第二模块使用球栅阵列电连接到所述第一模块。
19.如权利要求15所述的系统，还包括：
通过设置在所述第一模块衬底上的第二组电导体电连接到所述第一模块的第三模块。
20.如权利要求19所述的系统，其中，所述第三模块使用球栅阵列电连接到所述第一模块。
CN201210252290XA 2011-07-21 2012-07-20 双侧倒装芯片封装 Pending CN102891139A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/188,287 US20130020702A1 (en) 2011-07-21 2011-07-21 Double-sided flip chip package
US13/188,287 2011-07-21

Publications (1)

Publication Number Publication Date
CN102891139A true CN102891139A (zh) 2013-01-23

Family

ID=46548277

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210252290XA Pending CN102891139A (zh) 2011-07-21 2012-07-20 双侧倒装芯片封装

Country Status (10)

Country Link
US (1) US20130020702A1 (zh)
EP (1) EP2549533A1 (zh)
JP (1) JP2013038425A (zh)
KR (1) KR20130011984A (zh)
CN (1) CN102891139A (zh)
AU (1) AU2012204142A1 (zh)
BR (1) BR102012018139A2 (zh)
MX (1) MX2012008351A (zh)
TW (1) TW201308530A (zh)
WO (1) WO2013012634A2 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11302617B2 (en) * 2008-09-06 2022-04-12 Broadpak Corporation Scalable semiconductor interposer integration
US10594355B2 (en) 2015-06-30 2020-03-17 Skyworks Solutions, Inc. Devices and methods related to radio-frequency filters on silicon-on-insulator substrate
US20170092618A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Package topside ball grid array for ultra low z-height
US9939477B2 (en) * 2016-06-24 2018-04-10 International Business Machines Corporation On-demand detection of electromagnetic disturbances using mobile devices
KR102400748B1 (ko) * 2017-09-12 2022-05-24 삼성전자 주식회사 인터포저를 포함하는 전자 장치
KR102149387B1 (ko) 2019-02-13 2020-08-28 삼성전기주식회사 전자 소자 모듈

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020074652A1 (en) * 2000-12-15 2002-06-20 Pierce John L. Method, apparatus and system for multiple chip assemblies
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package
US20020163786A1 (en) * 2001-04-19 2002-11-07 Mark Moshayedi Chip stacks and methods of making same
US20030042587A1 (en) * 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2541487B2 (ja) * 1993-11-29 1996-10-09 日本電気株式会社 半導体装置パッケ―ジ
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
JP3653452B2 (ja) * 2000-07-31 2005-05-25 株式会社ノース 配線回路基板とその製造方法と半導体集積回路装置とその製造方法
JP2002158326A (ja) * 2000-11-08 2002-05-31 Apack Technologies Inc 半導体装置、及び製造方法
US20020121707A1 (en) * 2001-02-27 2002-09-05 Chippac, Inc. Super-thin high speed flip chip package
US6542393B1 (en) * 2002-04-24 2003-04-01 Ma Laboratories, Inc. Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between
US6833628B2 (en) * 2002-12-17 2004-12-21 Delphi Technologies, Inc. Mutli-chip module
TWI313048B (en) * 2003-07-24 2009-08-01 Via Tech Inc Multi-chip package
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
US7151010B2 (en) * 2004-12-01 2006-12-19 Kyocera Wireless Corp. Methods for assembling a stack package for high density integrated circuits
JP2007036104A (ja) * 2005-07-29 2007-02-08 Nec Electronics Corp 半導体装置およびその製造方法
JP2007123457A (ja) * 2005-10-27 2007-05-17 Nec Electronics Corp 半導体モジュール
JP5005321B2 (ja) * 2006-11-08 2012-08-22 パナソニック株式会社 半導体装置
US7948064B2 (en) * 2008-09-30 2011-05-24 Infineon Technologies Ag System on a chip with on-chip RF shield

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020074652A1 (en) * 2000-12-15 2002-06-20 Pierce John L. Method, apparatus and system for multiple chip assemblies
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package
US20020163786A1 (en) * 2001-04-19 2002-11-07 Mark Moshayedi Chip stacks and methods of making same
US20030042587A1 (en) * 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods

Also Published As

Publication number Publication date
KR20130011984A (ko) 2013-01-30
BR102012018139A2 (pt) 2014-06-17
TW201308530A (zh) 2013-02-16
JP2013038425A (ja) 2013-02-21
MX2012008351A (es) 2013-01-24
EP2549533A1 (en) 2013-01-23
US20130020702A1 (en) 2013-01-24
WO2013012634A3 (en) 2014-05-08
WO2013012634A2 (en) 2013-01-24
AU2012204142A1 (en) 2013-02-07

Similar Documents

Publication Publication Date Title
US6346743B1 (en) Embedded capacitor assembly in a package
US6900529B2 (en) Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
US7309914B2 (en) Inverted CSP stacking system and method
US7227247B2 (en) IC package with signal land pads
US20060050592A1 (en) Compact module system and method
CN102891139A (zh) 双侧倒装芯片封装
US20030137808A1 (en) Electronic module having canopy-type carriers
US7265995B2 (en) Array capacitors with voids to enable a full-grid socket
CN101236940B (zh) 重配置线路层的线路结构
CN112885808B (zh) 封装基板以及封装结构
US6992387B2 (en) Capacitor-related systems for addressing package/motherboard resonance
US8493765B2 (en) Semiconductor device and electronic device
US6794760B1 (en) Integrated circuit interconnect
US20210167038A1 (en) Dual in-line memory module
US11991827B2 (en) Electronic device
CN213184274U (zh) Sdram存储器
CN212209482U (zh) Spi闪断存储器
US20240128193A1 (en) Electronic module and electronic apparatus
US20230061258A1 (en) Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods
CN101521184B (zh) 半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C05 Deemed withdrawal (patent law before 1993)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130123