CN1228839C - 一种多晶粒封装结构 - Google Patents

一种多晶粒封装结构 Download PDF

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CN1228839C
CN1228839C CNB031091172A CN03109117A CN1228839C CN 1228839 C CN1228839 C CN 1228839C CN B031091172 A CNB031091172 A CN B031091172A CN 03109117 A CN03109117 A CN 03109117A CN 1228839 C CN1228839 C CN 1228839C
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crystal grain
encapsulating structure
electrically connected
substrate
encapsulation
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CN1467829A (zh
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李宗翰
林锟吉
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United Microelectronics Corp
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Abstract

本发明是提供一种多晶粒(multi-die)封装结构。本发明的封装结构包含有一L型基板以及复数个晶粒设于该L型基板上。该L型基板包含有一晶粒封装区，复数个凸块焊垫(solder bump pad)设于该晶粒封装区中，复数个针脚用来电连接一印刷电路板，与一电路设于该L型基板的内部，用来电连接该复数个凸块焊垫与该相对应的复数个针脚。其中，该复数个晶粒是设于该L型基板的晶粒封装区中，且该晶粒的主动表面包含有复数个接合垫(bondingpad)，用来电连接该复数个相对应的凸块焊垫。

Description

一种多晶粒封装结构
技术领域
本发明提供一种半导体封装结构，尤指一种多晶粒封装(multi-die package)结构。
背景技术
近年来，随着笔记型电脑、个人资料助理(PDA)与数位相机等携带式机器的小型化与高功能化，使其半导体制程倾向于高积集度与高密度封装，而在提升封装积集度方面则取决于封装的承载器(carrier)的尺寸，以及晶片与承载器接合所占的空间。
对于单一晶片的半导体封装而言，晶片上有导脚(lead on chip，LOC)的封装结构是常见缩小晶片与承载器接合所占空间的方法，LOC架构是指承载器的导脚延伸至晶片中央的接合垫，导脚与晶片主动表面连接，亦同时提供晶片物理上的支撑，因此可以缩小整个封装的体积。其中，承载器包括习知的LOC型态的导线架，或是具有开口的积层板(laminate substrate)。
对于多晶粒集成电路的封装而言，多晶片封装模组(multi-chip module，MCM)为常见高积集度的封装结构。MCM根据不同的集成电路设计需求，将多个晶片同时封装于同一承载器上，不但能缩小封装体积，减少制程费用，且因为晶片间讯号传递路径缩短，故可增加其效能。目前MCM通常架构在一印刷电路板(printed circuit board)上，将多个晶片配置于印刷电路板的同一表面，而晶片与电路板连接方式包括打线(wire bonding)、软片自动接合(tapeautomatic bonding，TAB)或覆晶(flip chip)的方式。
请参照图1与图2，图1与图2为习知多晶粒(multi-die)封装结构20的示意图。如图1所示，将至少一晶粒12的主动表面朝上，以绝缘黏着剂14(insulation glue)涂抹于晶粒12的背面，并将晶粒12贴附于一基板10的一预定区域上，以温度150℃加热烘烤固化晶粒12。接着利用打线(wirebonding)方式，以铜线15电连接晶粒12的主动表面上的接合垫16与基板10上相对应的接点(未显示)，然后以一封装材料18完整覆盖晶粒12和铜线15，并加热烘烤使封装材料18固化。之后再进行一蚀刻制程以于基板10下侧形成复数个以球格阵列(ball grid array，BGA)方式排列的焊球垫(未显示)，并焊接复数个锡球19于复数个焊球垫上。其中，锡球19用来电连接整个封装结构20与一印刷电路板(未显示)，而基板10内部具有一电路(未显示)，用来电连接基板10的接点与锡球19，因此晶粒12可透过铜线15、基板10内部的电路与锡球19以电连接印刷电路板。此外，基板10为一积层板，黏着剂14为一高分子材料，封装材料18为陶瓷、玻璃环氧树脂或BT树脂(BT resin)。
习知利用打线方式所形成的封装结构所占面积较大，不符合小型化的需求，因此发展出一种锡球间距较小，封装外型接近晶粒大小，且厚度不必考虑到打线的线弧度高度，称为晶片型封装(chip scale package)，以裸晶片(bare chip)与覆晶(flip chip)方式以达成高密度封装。如图2所示，习知覆晶晶片型封装结构28中，将至少一晶粒12的主动表面朝下，以覆晶方式贴附于基板10的预定区域表面，其中基板10的表面具有复数个凸块焊垫(bump pad)22，用来植接复数个相对应的锡球(solder ball)24，而晶粒12主动表面上的接合垫16以电连接复数个相对应的凸块焊垫22，接着以一填充物质26，如树脂填充于各晶粒12与基板10之间，并与锡球24周围的外侧区域形成一底充区域(under fill region)，以减轻锡球24因为基板10与晶粒12的热膨胀系数不同所产生的应力集中。
习知多晶粒封装结构是将晶片配置于印刷电路板的同一面，因此当晶粒较多时，所占的印刷电路板面积会较大，不符合目前趋势。且晶粒之间的连接线路需透过印刷电路板中复杂的路径传输，不但增加讯号传递路径的长度及阻抗，亦同时降低整体效能，虽然可以利用覆晶方式来缩小封装体积，但是晶粒的接合垫间距会由于晶粒的小型化而过于狭窄，锡球的高度也降低，使得填充物质和晶粒之间的间隙狭窄，增加形成底充区域的难度，目前虽然已有使用known good die(KGD)方式，但是良率很低且增加成本。
发明内容
本发明的主要目的在于提供一种多晶粒(multi-die)封装结构，可以缩短晶粒间的讯号传递路径，以提高整体效能。
本发明的另一目的在于提供一种多晶粒封装结构，不但可以强化机械强度以保护晶粒免于外在环境如机械碰撞、化学物质或湿气的影响而失去功能，更可以缩小整体封装体积，提高封装的积集度。
一种多晶粒(multi-die)的封装结构，该封装结构包含有：
一L型基板，该L型基板包含有一晶粒封装区，复数个凸块焊垫(solder bumppad)设于该晶粒封装区中，复数个针脚(pin)用来电连接一印刷电路板，以及一电路设于该L型基板的内部，用来电连接该复数个凸块焊与该相对应的复数个外部接脚；以及
复数个晶粒，该复数个晶粒配置于该L型基板的晶粒封装区中，其中该晶粒的主动表面包含有复数个接合垫(bonding pad)，用来电连接该复数个相对应的凸块焊垫。
所述的的封装结构，其中是利用覆晶(flip chip)方式，以电连接该晶粒的接合垫与该L型基板的凸块焊垫。
所述的封装结构，其中另包含复数个焊料凸块(solder bump)设于该复数个晶粒的接合垫与该L型基板的凸块焊垫之间，用来固定并电连接该复数个晶粒。
所述的封装结构，其中是先将该晶粒贴设于该L型基板上，再以打线(wirebonding)方式电连接该晶粒的接合垫与该L型基板的凸块焊垫。
所述的封装结构，其中还包含一封胶(encapsulating)制程，以一封装材料(molding compound)完整包覆该L型基板与该复数个晶粒。
所述的封装结构，其中该封装材料是包含有硅胶、环氧树脂、聚醯胺类、聚苯二甲基类或硅聚醯胺类。
所述的封装结构，其中该复数个外部接脚的封装形状包含有筒状(can)封装、双列直插式封装(dual-inline package，DIP)、扁平封装(flat package，FP)、栅格阵列(pin grid array，PGA)、晶片座(chip carrier)或带状在座(tape carrier)封装。
所述的封装结构，其中该L型基板还包含一具有一控制电路的周边(periphery)区域。
所述的封装结构，其中该晶粒是包含有逻辑(logic)电路晶粒，静态随机存取记忆体(SRAM)晶粒，动态随机存取记忆体(DRAM)晶粒，中央处理单元(CPU)晶粒或快闪记忆体(flash memory)晶粒。
一种系统整合的封装结构，用以同时封装复数个晶粒(die)，该封装结构包含有：
一基板结构，该基板结构包含有至少一垂直基板连结于一水平基板上，该垂直基板包含有一晶片封装区，复数个凸块焊垫(solder bump pad)设于该晶片封装区中，复数个外部接脚，以及一电路设于该基板结构的内部，用以电连接该复数个凸块焊垫与相对应的该复数个针脚；以及
复数个晶粒，该复数个晶粒设于该垂直基板的晶片封装区中，且每一个晶粒的表面包含有复数个接合垫(bonding pad)，用来电连接该复数个相对应的凸块焊垫。
所述的封装结构，其中该复数个外部接脚是用来电连接一印刷电路板。
所述的封装结构，其中该复数个外部接脚是用来电连接每一个垂直基板。
所述的封装结构，其中该复数个外部接脚的封装形状包含有筒状(can)封装、双列直插式封装(dual-inline package，DIP)、扁平封装(flat package，FP)、栅格阵列(pin grid array，PGA)、晶片座(chip carrier)或带状在座封装(tape carrier)。
所述的封装结构，其中是利用覆晶(flip chip)方式，以电连接该晶粒的接合垫与该垂直基板的凸块焊垫。
所述的封装结构，其中还包含复数个焊料凸块(solder bump)设于该复数个晶粒的接合垫与该垂直基板的凸块焊垫之间，用来固定并电连接该复数个晶粒。
所述的封装结构，其中是先将该晶粒贴设于该垂直基板上，再以打线(wirebonding)方式打线电连接该晶粒的接合垫与该垂直基板的凸块焊垫。
所述的封装结构，其中还包含一封胶(encapsulating)制程，以一封装材料(molding compound)完整包覆该基板结构与该复数个晶粒。
所述的封装结构，其中该封装的封装材料是包含有硅胶、环氧树脂、聚醯胺类、聚苯二甲基类或硅聚醯胺类。
所述的封装结构，其中该垂直基板还包含一具有一控制电路的周边(periphery)区域。
所述的封装结构，其中该晶粒是包含有逻辑(logic)电路晶粒，静态随机存取记忆体(SRAM)晶粒，动态随机存取记忆体(DRAM)晶粒，中央处理单元(CPU)晶粒或快闪记忆体(flash memory)晶粒。
相较于习知晶粒直接配置于印刷电路板上，本发明的多晶粒封装结构先将晶粒配置于L型基板的晶粒封装区中，再将L型基板以电连接印刷电路板，除了同样可达到保护晶粒免于外界的伤害外，也具有尺寸规格化的功能。综上所述，本发明具有下列优点：
1.将复数个晶粒配置于L型基板上，可以缩短晶粒间讯号传递路径，减少电路阻抗，降低讯号延迟，提高讯号传输速度，并提高整体效能，
2.缩小封装体积，提高封装积集度，
3.基板结构可以无限延伸以同时配置多个晶粒，
4.利用针脚封装结构，方便使用者自行组装与拆卸。
附图说明
图1至图2为习知多晶粒封装结构的示意图；
图3为本发明L型基板结构的正面示意图；
图4为本发明多晶粒封装的侧面示意图；
图5为本发明多晶粒封装的局部放大示意图；
图6为本发明多晶粒封装的正面示意图；
图7为本发明多晶粒封装完成的侧面示意图；
图8为本发明第二实施例基板结构的正面示意图；
图9为本发明第二实施例基板结构的侧面示意图；
图10为本发明第二实施例多晶粒封装完成的侧面示意图。
符号说明
10基板             12晶粒
14绝缘黏着剂       15铜导线
16接合垫           18封装材料
19焊球             20多晶粒封装结构
22凸块焊垫         24锡球
26填充材料         28多晶粒封装结构
30L型基板          32垂直基板
34水平基板         36晶粒封装区
38周边区域         40凸块焊垫
42外部接脚         44--48晶粒
50接合垫           52焊料凸块
54填充材料         56晶粒封装区
58封装材料         60多晶粒封装结构
62基板结构         64垂直基板
66水平基板         68周边区域
70凸块焊垫         72接脚
74外部接脚         76孔洞
78接脚             80--88晶粒
90封装材料         92多晶粒封装结构
具体实施方式
请参照图3至图7，图3至图7为本发明的多晶粒封装结构60的示意图。如图3所示，一L型基板30为本发明的多晶粒封装结构60所使用的封装基板，L型基板30是为一垂直基板32与一水平基板34的组合。垂直基板32的表面具有一晶粒封装区36与一周边(periphery)区域38，晶粒封装区36中具有复数个阵列状的凸块焊垫40(bump pad)，水平基板34的下侧具有复数个针脚(pin)42，用来电连接一印刷电路板(未显示)，且L型基板30的内部具有一电路(未显示)，用来电连接复数个凸块焊垫40与其相对应的针脚42，周边区域38内部具有一控制电路(未显示)，用以控制L型基板30的内部的电路连接。其中，L型基板30为一般的积层板，其材质包括有玻璃环氧基树脂(FR-4、FR-5)或双顺丁烯二酸醯亚胺(Bismaleimide-Triazine，BT)，而针脚42的排列方式可为格状阵列(grid array)或特殊格状阵列(specialized gridarray)。
如图4所示，先将一晶粒44配置于晶粒封装区36的一预定区域中，再依照不同的集成电路的设计需求，配置所需的相同功能或不同功能的晶粒(die)，如晶粒46。其中，晶粒44与46可为逻辑(logic)电路晶粒、静态随机存取记忆体(SRAM)晶粒，动态随机存取记忆体(DRAM)晶粒，中央处理单元(CPU)晶粒或快闪记忆体(flash memory)晶粒等的晶粒。
接着如图5所示，图5为图4的晶粒封装区36的放大示意图。晶粒44与46的主动表面具有复数个接合垫50(bonding pad)，用来电连接晶粒封装区36的相对应的凸块焊垫(solder bump pad)40。首先将晶粒44与46以主动表面面向L型基板30的表面，以覆晶方式将晶粒44与46贴设于晶粒封装区36的预定区域中，且接合垫50与凸块焊垫40之间设有复数个焊料凸块52(solderbump)或导电聚合物凸块(conductive polymer bump)，用来固定并电连接晶粒44与46以及晶粒封装区36的凸块焊垫40。
为了避免后续操作时，焊料凸块52因受到热循环与热应力的影响，而产生疲劳断裂的情形，可分别于晶粒44、晶粒46与L型基板30的晶粒封装区36之间填入一填充材料54，并充满于焊料凸块52之间以形成一底部密封层(epoxyunderfill layer)。此外，为了改善本发明的多晶粒封装的散热效能，可于晶粒44与46的背面配置一散热片(未显示)，散热片与晶粒44与46以导热性连接(thermal coupling)。其中，焊料凸块52的材质为锡铅合金或金，填充材料54的材质包括液态封装材料、环氧树脂或异方性导电树脂(anisotropicconductive film，ACF)。
如图6所示，图6为图4的正面示意图。若是晶粒数量太多可另将晶粒配置于水平基板34的晶粒封装区56中，或垂直基板32的背面。同样地，水平基板34的晶粒封装区56或垂直基板32背面的晶粒封装区(未显示)表面亦具有复数个凸块焊垫40。
最后如图7所示，将配置完成的多晶粒封装结构60浸入一封装材料58(molding compound)中，进行一封胶(encapsulating)制程，以完整包覆L型基板30、晶粒44至48以及L型基板30与晶粒44至48相连接的部分，以保护其不受外界环境、人为因素或湿气所破坏，完成本发明的多晶粒封装结构60。其中，封装材料58的材质为硅胶、环氧树脂、聚醯胺类、聚苯二甲基类或硅聚醯胺类等。另外，如前所述，L型基板30的内部包含有一电路(未显示)，用来电连接复数个凸块焊垫40与其相对应的针脚42，以将多晶粒封装结构60透过针脚42而与一印刷电路板(如主机板等产品)上相对应的导电区域相电连接，组装于该印刷电路板上，以符合需求的完整的电气功能。
请参照图8至图10，图8至图10为本发明第二实施例多晶粒封装结构92的示意图。如图8与图9所示，基板结构62具有至少一垂直基板64与一水平基板66相连结。本实施例是以三个垂直基板64为例，每一个垂直基板64的表面具有一晶粒封装区65与一周边区域68，复数个凸块焊垫70设于晶粒封装区65中，复数个接脚72设于垂直基板64的下侧，用以插入并电连接水平基板66的相对应的孔洞76，而水平基板66下侧还具有复数个外部接脚74，用以插入一印刷电路板(未显示)，且垂直基板64与水平基板66的内部具有一电路(未显示)，用以电连接复数个凸块焊垫70与相对应的复数个外部接脚74，周边区域68具有一控制电路(未显示)，用以控制基板结构62内的电路连接。此外，垂直基板64的表面还可具有复数个相对应的孔洞(未显示)，而垂直基板64的背面则相对应地具有复数个接脚78，用以相互电连接每一个垂直基板64。其中，基板结构62为一般的积层板，其材质包括有玻璃环氧基树脂或双顺丁烯二酸醯亚胺，而接脚72、外部接脚74与接脚78均可为针脚或焊球，其排列方式为格状阵列或特殊格状阵列。
如图10所示，本实施例以五个晶粒80至88为例，依照集成电路设计需求，将晶粒80至88分别贴设于垂直基板64的晶粒封装区65中，最后利用一封装材料90，如环氧树脂，以完整包覆基板结构62以及晶粒80至88，完成本发明的多晶粒封装92。其中，如图5所示，晶粒80至88可以利用打线方式或覆晶方式，而装设于晶粒封装区65上。
另外，所述的封装结构，其中该复数个外部接脚的封装形状包含有筒状(can)封装、双列直插式封装(dual-inline package，DIP)、扁平封装(flatpackage，FP)、栅格阵列(pin grid array，PGA)、晶片座(chip carrier)或带状在座封装(tape carrier)。
本发明利用L型基板为封装架构，将复数个具有相同功能或不同功能的复数个晶粒配置于L型基板的晶粒封装区中，以形成一整合型封装结构，且若是所需封装的晶粒数量太多，则可以延伸L型基板使其具有复数个垂直基板与复数个晶粒封装区。而本发明中实施例的接脚均以针脚封装结构来说明，此乃因针脚封装为面积阵列式配置(area array)，具有较高的积集度，但本发明的封装架构亦可选用其他种类的电连接针脚。
本发明经过最后封胶制程之后所形成的整合型封装结构可以视为一插卡结构，以方便使用者自行组装，更换插卡，也不会损伤到晶粒及其内部电路。
相较于习知晶粒直接配置于印刷电路板上，本发明的多晶粒封装结构先将晶粒配置于L型基板的晶粒封装区中，再将L型基板以电连接印刷电路板，除了同样可达到保护晶粒免于外界的伤害外，也具有尺寸规格化的功能。综上所述，本发明具有下列优点：
1.将复数个晶粒配置于L型基板上，可以缩短晶粒间讯号传递路径，减少电路阻抗，降低讯号延迟，提高讯号传输速度，并提高整体效能，
2.缩小封装体积，提高封装积集度，
3.基板结构可以无限延伸以同时配置多个晶粒，
4.利用针脚封装结构，方便使用者自行组装与拆卸。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明专利的涵盖范围。

Claims (20)

1.一种多晶粒的封装结构，其特征在于该封装结构包含有：
一L型基板，该L型基板包含有一晶粒封装区设于一垂直基板上，复数个凸块焊垫设于该晶粒封装区中，复数个外部接脚设于一水平基板下方用来电连接一印刷电路板，以及一电路设于该L型基板的内部，用来电连接该复数个凸块焊垫与该相对应的复数个外部接脚；以及
复数个晶粒，该复数个晶粒配置于该L型基板的晶粒封装区中，其中该晶粒的主动表面包含有复数个接合垫，用来电连接该复数个相对应的凸块焊垫。
2.如权利要求1所述的封装结构，其特征在于其是利用覆晶方式，以电连接该晶粒的接合垫与该L型基板的凸块焊垫。
3.如权利要求2所述的封装结构，其特征在于：还包含复数个焊料凸块设于该复数个晶粒的接合垫与该L型基板的凸块焊垫之间，用来固定并电连接该复数个晶粒。
4.如权利要求1所述的封装结构，其特征在于：先将该晶粒贴设于该L型基板上，再以打线方式电连接该晶粒的接合垫与该L型基板的凸块焊垫。
5.如权利要求1所述的封装结构，其特征在于：还包含一封胶制程，以一封装材料完整包覆该L型基板与该复数个晶粒。
6.如权利要求4所述的封装结构，其特征在于：该封装材料是包含有硅胶、环氧树脂、聚醯胺、聚苯二甲基或硅聚醯胺。
7.如权利要求1所述的封装结构，其特征在于：该复数个外部接脚的封装形状包含有筒状封装、双列直插式封装、扁平封装、栅格阵列、晶片座或带状在座封装。
8.如权利要求1所述的封装结构，其特征在于：该L型基板还包含一具有一控制电路的周边区域。
9.如权利要求1所述的封装结构，其特征在于：该晶粒是包含有逻辑电路晶粒，静态随机存取记忆体晶粒，动态随机存取记忆体晶粒，中央处理单元晶粒或快闪记忆体晶粒。
10.一种系统整合的封装结构，用以同时封装复数个晶粒，其特征在于该封装结构包含有：
一基板结构，该基板结构包含有至少一垂直基板连结于一水平基板上，该垂直基板包含有一晶片封装区，复数个凸块焊垫设于该晶片封装区中，复数个外部接脚，以及一电路设于该基板结构的内部，用以电连接该复数个凸块焊垫与相对应的该复数个外部接脚；以及
复数个晶粒，该复数个晶粒设于该垂直基板的晶片封装区中，且每一个晶粒的表面包含有复数个接合垫，用来电连接该复数个相对应的凸块焊垫。
11.如权利要求10所述的封装结构，其特征在于：该复数个外部接脚是用来电连接一印刷电路板。
12.如权利要求10所述的封装结构，其特征在于：该复数个外部接脚是用来电连接每一个垂直基板。
13.如权利要求10所述的封装结构，其特征在于：该复数个外部接脚的封装形状包含有筒状封装、双列直插式封装、扁平封装、栅格阵列、晶片座或带状在座封装。
14.如权利要求10所述的封装结构，其特征在于：其是利用覆晶方式，以电连接该晶粒的接合垫与该垂直基板的凸块焊垫。
15.如权利要求14的封装结构，其特征在于：还包含复数个焊料凸块设于该复数个晶粒的接合垫与该垂直基板的凸块焊垫之间，用来固定并电连接该复数个晶粒。
16.如权利要求10所述的封装结构，其特征在于：先将该晶粒贴设于该垂直基板上，再以打线方式电连接该晶粒的接合垫与该垂直基板的凸块焊垫。
17.如权利要求10所述的封装结构，其特征在于：还包含一封胶制程，以一封装材料完整包覆该基板结构与该复数个晶粒。
18.如权利要求17所述的封装结构，其特征在于：该封装的封装材料是包含有硅胶、环氧树脂、聚醯胺、聚苯二甲基或硅聚醯胺。
19.如权利要求10所述的封装结构，其特征在于：该垂直基板还包含一具有一控制电路的周边区域。
20.如权利要求10所述的封装结构，其特征在于：该晶粒是包含有逻辑电路晶粒，静态随机存取记忆体晶粒，动态随机存取记忆体晶粒，中央处理单元晶粒或快闪记忆体晶粒。
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