CN1551351A - 半导体多芯片封装和制备方法 - Google Patents

半导体多芯片封装和制备方法 Download PDF

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Publication number
CN1551351A
CN1551351A CNA2004100477958A CN200410047795A CN1551351A CN 1551351 A CN1551351 A CN 1551351A CN A2004100477958 A CNA2004100477958 A CN A2004100477958A CN 200410047795 A CN200410047795 A CN 200410047795A CN 1551351 A CN1551351 A CN 1551351A
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China
Prior art keywords
chip
multicore sheet
sheet encapsulation
supporting structure
connection lead
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CNA2004100477958A
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English (en)
Inventor
金东局
李昌哲
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020030021922A external-priority patent/KR20040087501A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1551351A publication Critical patent/CN1551351A/zh
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Abstract

本发明公开了一种多芯片封装和制备方法。多芯片封装包括上面设有键合指的封装衬底。第一芯片具有大体形成在中心部分上的中心焊盘。在封装衬底上设置第一芯片。在位于焊盘外侧的第一芯片上形成绝缘支撑结构。在一个键合指和至少一个中心焊盘之间连有连接导线。第二芯片被设置在连接导线上并且覆盖绝缘支撑结构。

Description

半导体多芯片封装和制备方法
技术领域
本发明涉及半导体器件，具体地说，涉及一种半导体多芯片封装及其制备方法。
根据35 U.S.C.§119，该U.S.非临时申请请求享有申请日为2003年4月8日的韩国专利申请2003-21922号的优先权，在此将其全部内容引作参考。
背景技术
传统的半导体芯片具有或者在芯片中心区域上形成焊盘(bondingpads)12的中心焊盘(center pads)结构，或者在芯片周缘区域上形成焊盘14的周缘焊盘结构。图1A是具有中心焊盘结构的半导体芯片的平面图，图1B是具有周缘焊盘结构的半导体芯片的平面图。通常，中心焊盘结构更适于实现半导体器件的高速工作。
近来，为形成能满足用于高速、多功能半导体器件中的高封装密度要求的半导体多芯片封装，半导体行业投入了大量资源。其中的努力包括该行业推荐了包括具有周缘焊盘结构的叠层芯片的半导体多芯片封装。
图2示出了一种这类传统的多芯片封装。参见图2，半导体多芯片封装包括每个都具有周缘焊盘结构的叠层芯片20、40。将芯片20、40中的一个层叠在另一个上并在其间设置隔离件30。然而，遗憾的是，由于中心焊盘不能在其间提供用于放置隔离件的足够空间，因此图2的多芯片封装不能利用具有中心焊盘结构的下层芯片进行组装。
图3示出了一种传统的尝试，以提供具有最初被构成为具有中心焊盘结构即，在其中心区域(“中心焊盘布线图形”)上形成的焊盘布线图形(未示出)的下层芯片32的半导体多芯片封装32，。
图4和5表示用于将中心焊盘布线图形36重新分布为周缘焊盘38的工艺，在该工艺中进行实际的导线键合工艺(actual wire bonding process)。参见图3至5，根据该实例，传统的多芯片封装32包括最初构成为具有中心焊盘结构的叠层芯片32、34。使用重新分布图形39将半导体芯片32、34的中心焊盘布线图形36从中心区域重新分布到周缘区域。
换句话说，中心焊盘布线图形36通过重新分布图形39连接周围焊盘38。这使隔离件37可被设置在下层芯片32上的焊盘38之间，以形成包括具有中心焊盘布线图形36的叠层芯片32、34的多芯片封装300。
然而，遗憾的是，重新分布焊盘布线图形的成本相当高，并且工艺和封装的可靠性也没达到期望的水平。因此，仍需要一种可靠且低成本的方法来制备使用具有中心焊盘结构的芯片的半导体多芯片封装。
发明内容
根据本发明的原理，使用具有中心焊盘结构的芯片可形成高密度半导体多芯片封装。最好使用现有的组装设备完成，并且不使用昂贵的、不可靠的焊盘重新分布工艺。
例如，根据一实施方式，多芯片封装包括其上设置有键合指(bond fingers)的封装衬底。将第一芯片设置在封装衬底上，并优选包括在大体为该芯片的中心部上形成的第一焊盘。优选在第一芯片上的焊盘的外侧形成绝缘支撑结构。优选在一个键合指和至少一个第一焊盘之间连有连接导线。优选用支撑结构将部分连接导线与第一芯片分隔开。第二芯片设置在连接导线上并覆盖绝缘支撑结构。
附图说明
通过下面结合附图对优选实施方式所作出的详细描述可使本发明的目的、特征和优点更为清楚。在附图中，相同的附图标记表示相同或相似的部件，并且为清楚起见放大了层或区域的厚度。附图中：
图1A是现有的具有中心焊盘结构的半导体芯片平面图；
图1B是现有的具有周缘焊盘结构的半导体芯片平面图；
图2是具有周缘焊盘的芯片的传统的多芯片封装的横截面图；
图3是现有的具有将中心焊盘重新分布为周缘焊盘的芯片的多芯片封装的横截面图；
图4是具有从中心区域重新分布到周缘区域的焊盘的传统半导体芯片平面图；
图5是具有从中心区域重新分布到周缘区域的焊盘的传统半导体芯片的横截面图；
图6至12是横截面图，它示出了本发明一实施方式的制备半导体多芯片封装的方法；
图13是本发明另一实施方式的绝缘支撑结构的横截面图；
图14A是平面图，它示出了本发明一种情况的上面设置有绝缘支撑结构的半导体芯片；
图14B是平面图，它示出了根据本发明另一种情况的上面设置有绝缘支撑结构的半导体芯片；
图15是本发明另一实施方式的晶片层(wafer level)封装的平面图；
图16是在形成具有如图15所示结构的晶片层封装中使用的丝网掩模(screen mask)的平面图；
图17是本发明再一个实施方式的半导体多芯片封装的横截面图；
具体实施方式
现在参考附图详细描述本发明的各实施方式。然而，应强调的是，可在排列和细节上对在此描述的本发明的各实施方式进行改型，本发明的范围不限于所描述的实施方式。实际上，提供这些示例性的实施方式只是向本领域技术人员说明本发明的原理。
图12示出了根据本发明原理构造的多芯片封装的一优选实施方式。参见图12，优选多芯片封装400包括封装衬底200，在封装衬底上设置键合指220。优选第一芯片210具有中心焊盘结构，因此第一芯片包括在其大体为中心的部分上形成的第一焊盘215。优选在封装衬底200上设置第一芯片210。
优选在焊盘215外侧的第一芯片210上形成绝缘支撑结构260。例如，可沿第一芯片210的相对两侧彼此隔开地形成绝缘支撑结构260，并且在绝缘支撑结构之间具有焊盘215。例如，绝缘支撑结构260可沿第一芯片210的至少两个相对侧的周缘以线形延伸(参见图9)。
当然，支撑结构260决不限制为线形，其它形状也都包括在本发明的考虑之中。例如，支撑结构260可为沿第一芯片210的两个或多个周缘的长度方向设置的多个分离的堆形(mound-like)结构。也可如图14A至14B所示，在第一芯片210的拐角处形成支撑结构260。与线形支撑结构260相比，采用分离的堆形支撑结构，可通过减少形成绝缘支撑结构所需的材料量来降低制造成本和缩短处理时间。并且，支撑结构260不限于图9所示的直线形。其它形状如波浪线形也可用于实现本发明。另外，根据制造目的，可在第一芯片210的相对的周缘区域上形成多于单根线的绝缘支撑结构260。
优选在一个键合指220和至少一个第一焊盘215之间连接连接导线230。优选通过绝缘支撑结构260将连接导线230与第一芯片210分隔开。还需要确保连接导线环230(bonding wire loop)的顶部大体上不高于支撑结构260的顶部。优选使具有第二焊盘315的第二芯片310设置在连接导线230上方并覆盖绝缘支撑结构260。
图13示出了结合本发明原理的一可供选择的实施方式。参见图13，连接导线230可穿过支撑结构260，而不是位于支撑结构260上。在这种结构中，绝缘支撑结构260直接支撑第二芯片310。
然而，在另一实施方式中，根据制造目的，连接导线230不必直接接触支撑结构260，而是例如不接触地设置在其上方或者设置成与线状或分离的堆形支撑结构260并排。
图11是本发明的另一种情况。参见图11，优选多芯片封装400包括夹在第一芯片210和第二芯片310之间用于其间粘接的插入层270(interposer)。插入层270支撑第二芯片310并防止其接触连接第一芯片210的连接导线230。优选在分离的支撑结构260(参见图10)之间放置插入层材料170、例如其中没有如二氧化硅之类的填料的环氧树脂，以形成插入层270。当然，不使用插入层270，而使用绝缘支撑结构260和/或绝缘带340以支撑第二芯片3 10并使连接导线230绝缘，也可形成各种可供选择的实施方式。
再参见图12，多芯片封装400还可包括在第二芯片310和连接导线230之间设置的绝缘带340，例如用于提供其间的隔离。优选在第二芯片310的底面上形成绝缘带340。尽管未示出，绝缘带340可直接与连接导线230接触。而且，例如，如果连接导线230如结合图13或图14B所描述的那样分别穿过支撑结构260，那么绝缘带340可直接接触绝缘支撑结构260。也可选择使绝缘带340接触插入层270，而不接触连接导线230或绝缘支撑结构260。
多芯片封装400也可包括密封第一和第二芯片210、310的环氧树脂模塑料(EMC)(epoxy molding compound)350。尽管未示出，如果在第一芯片210上未形成插入层270，优选在第一芯片210和第二芯片310之间设置EMC350来代替插入层270。
制造方法
现在参考图6至12更详细地描述制备上述半导体多芯片封装400的优选方法。具体参考图6，通过在封装衬底200上安装下层(或第一)半导体芯片210来形成半导体多芯片封装400。这可使用常规技术完成。例如，可使用具有用于分配粘合剂240的分配器单元的常规粘片机(die-bonder)将粘合剂240施加在封装衬底200上。通常，粘合剂可为用于半导体封装的常规粘合材料。
封装衬底200可是印刷电路板(PCB)或如引线框或布线带(wiring tape)之类的其它封装衬底。优选衬底200具有用于在封装衬底200和第一芯片210之间电连接的键合指(或线连接接触)220。优选第一芯片210具有大体形成在芯片210中心部分上的第一焊盘(中心焊盘)215。优选使用粘合剂240将下层半导体芯片210结合于封装衬底200上。
再参见图7，通过在下层芯片210的周缘表面(即，周缘区域的表面)上施加液体类非导电环氧树脂、或任何其它合适的如混合型粘合剂、硅型粘合剂、薄膜型粘合剂之类的非导电绝缘材料形成绝缘支撑结构260。可使用例如包括分配技术之类的常规技术执行这种操作。可用将粘合剂240施加到封装衬底200上的粘片机分配单元将环氧树脂提供到下层芯片210的周缘表面。例如，可使绝缘支撑结构260沿下层芯片210(参见图9)的周缘区域线形排列，或排列为多个分隔的例如与中心焊盘215对准的堆形结构。
然后优选在约100℃或更高温度下对形成的结构进行热处理，固化支撑结构260的环氧树脂以及粘合剂240。因此，在下层芯片210周缘区域上形成绝缘支撑结构260。优选支撑结构260的宽度d1小于焊盘215的中心到第一芯片210最近周缘之间的距离d2的一半。另外，优选支撑结构260的高度h在大约25～200μm之间。
参见图8，优选键合指220的一部分通过由如金或铜之类的导电材料制造的第一连接导线230电连接到第一焊盘215。这种导线连接工艺可用包括但不限于楔焊技术或隆点回流球焊(bump rererse ball bonding)技术的常规技术实现。可直接在第一焊盘215上进行导线连接工艺，该第一焊盘215形成在芯片210的大体中心部分上。如参考区域A所示，第一导线230可直接接触支撑结构260的顶表面(即，直接覆盖设置)。连接导线230也可构造为穿过支撑结构260(参见图13)或者位于绝缘支撑结构260上方以使其不接触支撑结构260。使用绝缘支撑结构260，可减少常见问题如连接导线下垂问题。
参见图10，优选在下层芯片210的表面上设置插入层材料170。插入材料层170可是液体，也可为与形成支撑结构260相同的材料。可用常规分配技术施加插入层材料170。
参见图11，在第一芯片210上安装上面的(或第二)半导体芯片310。第二芯片310或者可具有中心焊盘结构，或者具有周缘焊盘结构。优选控制导线230的线环高度和形状，以使第一导线230不接触第二芯片310的底面。在这种情况中，连接导线230可具有低的线环高度和适于在第一芯片210上方层叠第二芯片310的大体平坦的部分。因此可减少封装厚度，并可防止由于布线230和第二芯片310之间不期望的接触而产生的器件失效。
可选择使第二芯片310具有设置在其底侧的绝缘带340。绝缘带340可防止第二芯片310的底面与第一导线230接触，并使第二芯片310更靠近第一芯片210，从而减少整个封装厚度。
当然，绝缘带340不是必须的，即使没有绝缘带340，通过使用在第一和第二芯片210、310之间的插入层270和/或绝缘结构260也可在导线230和第二芯片310之间获得足够的隔离。例如，如结合图13或图14B所述，如果连接导线230穿过支撑结构260，则在第一芯片210和第二芯片310之间的绝缘带340不是必须的。在这些实施方式的任一种中，优选使连接导线230与第二芯片310的底面分隔足够的距离，以提供其间的隔离。因此，根据本发明各实施方式，可显著降低第一连接导线230(线环)的高度，这反过来又显著减少了整个封装厚度。
在将第二芯片310安装或结合到第一芯片210期间，朝下推插入层材料170并使其沿下层芯片210的周缘区域散开。在此过程中，沿第一芯片210(参见图9)的长度延伸的绝缘支撑结构260用作挡拦结构(dam structure)，以有助于在第一芯片210的边界内包含插入层材料170并防止插入层材料渗出到封装衬底200上。尽管可在第一芯片210的两个以上的侧边上设置绝缘支撑结构260，但由于在下层芯片210上安装或结合上层芯片310时，在插入层材料170中可能产生孔隙，因此，优选使绝缘支撑结构260只沿第一芯片210的两个相对侧延伸。
通过有助于防止插入层材料170流到下层芯片210的侧壁，可保持插入层270的适当厚度。另外，通过防止插入层材料170在下层芯片210和外壳350之间流动，可防止它们之间的弱结合。例如，如果插入层材料170可从下层芯片210的周缘逸出，则在下层芯片210和密封第一和第二芯片210、310的环氧树脂模塑料之间插入具有弱结合特性的插入层材料170，由此可抑制在形成外壳350(图12)的模塑料和下层芯片210之间的直接的强结合。因此插入层材料的逸出可降低整个封装的可靠性。支撑结构260也有利于在结合期间保持第二芯片310和第一芯片210之间的平行关系。这也提高了产量并减少了整个封装厚度。
在第一芯片210上安装第二芯片310后，通过在约50℃到约200℃之间的温度下进行热处理固化插入层材料170，以形成插入层270。插入层270使下层和上层芯片210、310彼此结合，同时在固化的插入层270中进一步牢固连接导线230。由于插入层270可防止在转移模制工艺中第一导线230被流动的模塑料偏移或弯曲，从而可有效地防止常见的密封问题如由于密封材料导致的导线偏移和下垂。另外，插入层270也可提供第一芯片210和第二芯片310之间的隔离。
优选使键合指220的其它部分通过第二连接导线330直接电连接到形成在上层芯片310中的第二焊盘315。如上所讨论的那样，这也可用常规导线连接技术完成。上层芯片310也可以具有利用与前述类似的方法形成的绝缘支撑结构。
参见图12，然后对形成的结构进行模制工艺，以形成外壳350。这可为使用EMC的常规模制工艺。当然，本领域的技术人员可理解，外壳350可由除EMC以外的材料如陶瓷形成，也可使用除常规模制工艺以外的工艺形成。如前面所指出的那样，在转移模工艺中通过模塑料插入层270可防止第一导线230偏移和弯曲。因此与存在布线偏移和下垂问题的传统封装相比可显著提高连接导线的可靠性和封装的可靠性。可在封装衬底200的底面上形成如焊料球阵列之类的导电球阵列，以形成球栅阵列(BGA)封装并与外部系统连接。
可供选择的实施方式
图13示出了实现本发明原理的可供选择的实施方式。参见图13，除了在形成第一导线230之后形成支撑结构260外，该可供选择的实施方式与图6至13B中描述的实施方式相同。因此，在本实施方式中，第一导线230可穿过支撑结构260。在所示的本具体实施方式中，第一导线230穿过支撑结构260的中部，以在支撑结构260中固定或紧固第一导线230。本实施方式的一个优点是第一导线230的顶高低于支撑结构260的顶高。因此足以将上层芯片310的底面与第一芯片230隔离并且可防止布线偏移和下垂问题而不需要绝缘带340。上层芯片310可保持与下层芯片210平行。
根据本发明的另一实施方式，本发明的各原理有利于单个芯片封装。在此实施方式中，在形成支撑结构260之后，可对形成的结构进行模制工艺和形成焊料球阵列的工艺。在该单个芯片的实施方式中，支撑结构260有助于防止在模制工艺期间第一导线230的偏移和下垂。
晶片层制备技术
图15和16示出了根据本发明另一实施方式的晶片层制备技术。除了在晶片层上形成支撑结构260外，晶片层制备工艺与上述参考图6到13B描述的工艺相同。
参见图15，晶片包括多个芯片210，每个芯片具有在其上形成的绝缘支撑结构260。可使用与在前描述的分配技术相同的晶片层分配技术形成支撑结构260。支撑结构260也可使用丝网印刷技术形成。图16示出了用于形成线状支撑结构260的丝网掩模402。丝网掩模402也可用于形成多个分离的交替结构。丝网印刷技术可更好地控制支撑结构260的宽度和高度。在形成绝缘支撑结构260之后，晶片被切片(切割)为单独的多个芯片210。接下来，进行上述工艺或用相似的方法以形成根据本发明原理的多芯片封装。形成晶片层支撑结构260的方法也可用于具有只有单个芯片的封装。
具有三个或更多芯片的芯片封装
图17是实现本发明原理的又一实施方式，其中多芯片封装包括两个以上的叠层芯片。参见图17，该实施方式中的多芯片封装500包括三个或更多叠层芯片510、520、530、540。为简化描述，在此附图中的所有连接导线512都连接到单键合指514。然而，本领域技术人员可以理解，可根据需要将各连接导线512连接到对应的键合指514。每个叠层芯片510、520、530、540或者可具有中心焊盘结构，或者可具有周缘焊盘结构。并非所有的叠层芯片510、520、530、540都需要具有相同的焊盘结构。
总之，使用如本发明公开部分所披露的绝缘结构260，可设有或不设有插入层270，使用具有中心焊盘结构的下层芯片可形成多芯片封装。而且，与传统方法相比，此处所公开的方法成本更低，并可使用现有设备完成。因此，可避免如布线偏移或下垂等常见问题。
尽管上面已参照具体实施方式对本发明的原理作出了图示和描述，但本领域技术人员可以理解，在不超出本发明构思和保护范围的前提下，如所附权利要求书所覆盖的那样，可对形式和细节作出各种改变。

Claims (58)

1.一种多芯片封装，包括：
一上面设有键合指的封装衬底；
一第一芯片，该芯片具有大体在其中心部分的第一焊盘，所述第一芯片设置在所述封装衬底上；
形成在位于所述第一焊盘外侧的所述第一芯片上的绝缘支撑结构；
连接在一个所述键合指和至少一个所述第一焊盘之间的连接导线；以及
一第二芯片，其具有设置在所述连接导线上方的第二焊盘，该芯片覆盖所述绝缘支撑结构。
2.根据权利要求1所述的多芯片封装，其中，所述支撑结构沿所述第一芯片相对的两侧延伸。
3.根据权利要求2所述的多芯片封装，其中，所述支撑结构以线形延伸。
4.根据权利要求3所述的多芯片封装，其中，所述连接导线穿过所述支撑结构。
5.根据权利要求3所述的多芯片封装，其中，所述连接导线位于所述支撑结构上，并且所述连接导线与所述支撑结构不直接接触。
6.根据权利要求3所述的多芯片封装，其中，所述连接导线直接位于所述支撑结构上。
7.根据权利要求1所述的多芯片封装，其中，所述支撑结构包括多个分离的堆形结构。
8.根据权利要求7所述的多芯片封装，其中，在所述第一芯片的各个拐角处形成所述多个分离的堆形结构。
9.根据权利要求7所述的多芯片封装，其中，所述连接导线穿过所述支撑结构。
10.根据权利要求7所述的多芯片封装，其中，所述连接导线位于所述支撑结构上，并且所述连接导线与所述支撑结构不直接接触。
11.根据权利要求7所述的多芯片封装，其中，所述连接导线设置为直接位于所述支撑结构上。
12.根据权利要求1所述的多芯片封装，其中，还包括夹在所述第一芯片和所述第二芯片之间的一插入层。
13.根据权利要求12所述的多芯片封装，其中，使所述插入层的主要部分位于所述支撑结构之间且位于所述第一芯片上。
14.根据权利要求12所述的多芯片封装，其中，所述插入层支撑所述第二芯片，以防止所述第二芯片接触所述连接导线。
15.根据权利要求12所述的多芯片封装，其中，用与所述支撑结构相同的材料构成所述插入层。
16.根据权利要求12所述的多芯片封装，其中，所述插入层由不加填料的环氧树脂构成。
17.根据权利要求1所述的多芯片封装，其中，还包括设置在所述第二芯片和所述连接导线之间的一绝缘带。
18.根据权利要求17所述的多芯片封装，其中，所述绝缘带与所述连接导线直接接触。
19.根据权利要求17所述的多芯片封装，其中，所述绝缘带与所述绝缘支撑结构直接接触。
20.根据权利要求1所述的方法，其中，所述线环的顶部大体上不高于所述支撑结构的顶部。
21.根据权利要求1所述的多芯片封装，其中，还包括密封所述第一芯片和所述第二芯片的一外壳。
22.根据权利要求21所述的多芯片封装，其中，所述外壳包括一环氧模塑料。
23.根据权利要求21所述的多芯片封装，其中，所述环氧模塑料设置在所述第一芯片和所述第二芯片之间。
24.根据权利要求1所述的多芯片封装，其中，所述封装衬底是一导线框架或一布线带。
25.根据权利要求1所述的多芯片封装，其中，所述绝缘结构的宽度小于所述焊盘中心和所述第一芯片的最近周缘之间的距离的一半。
26.根据权利要求1所述的多芯片封装，其中，所述绝缘支撑结构具有约25～200μm的高度。
27.根据权利要求1所述的多芯片封装，其中，所述第二芯片具有形成在大体在其周缘区域的焊盘。
28.根据权利要求1所述的多芯片封装，其中，所述第二芯片具有形成在大体在其中心区域的焊盘。
29.根据权利要求1所述的多芯片封装，其中，还包括在所述第二芯片上附加层叠的一个或更多的芯片。
30.根据权利要求29所述的多芯片封装，其中，至少一个所述芯片具有位置与其它所述芯片的焊盘不同的焊盘。
31.根据权利要求1所述的多芯片封装，其中，还包括在所述封装衬底的一底面上形成的焊料球阵列，以形成球栅阵列封装。
32.根据权利要求1所述的多芯片封装，其中，利用所述第一焊盘使所述绝缘支撑结构之间彼此分隔。
33.根据权利要求1所述的多芯片封装，其中，所述连接线与所述支撑结构并排排列。
34.一种多芯片封装，包括：
一上面设有键合指的封装衬底；
一第一芯片，该芯片具有大体在其中心部分的第一焊盘，所述第一芯片设置在所述封装衬底上；
形成在位于所述第一焊盘外侧的所述第一芯片上的绝缘支撑结构；
连接在一个所述键合指和至少一个所述第一焊盘之间的连接导线，通过所述支撑结构将所述连接导线与所述第一芯片隔开；
层叠在所述连接导线上方并覆盖所述绝缘支撑结构的第二芯片；以及
夹在所述第一芯片和所述第二芯片之间的一绝缘插入层。
35.根据权利要求34所述的多芯片封装，其中，还包括；
形成在所述封装衬底的底面上的导电球阵列。
36.根据权利要求34所述的半导体封装，其中，所述连接导线具有设置在所述第二芯片下的大体平坦的部分。
37.一种多芯片封装，包括：
一封装衬底；
一安装在所述封装衬底上的第一芯片，该芯片具有大体在其中心部分上的中心焊盘；
一层叠在所述第一芯片上的第二芯片，该芯片与所述封装衬底电连接；以及
在所述封装衬底和所述中心焊盘之间电连接的连接线。
38.根据权利要求37所述的多芯片封装，其中，还包括形成在所述中心焊盘外侧的所述第一芯片上的绝缘支撑结构。
39.根据权利要求38所述的多芯片封装，其中，还包括设置在所述第一芯片和所述第二芯片之间的一插入层。
40.根据权利要求39所述的多芯片封装，其中，还包括在所述第二芯片的底面上形成的一绝缘带。
41.一种形成多芯片封装的方法，该方法包括：
提供一封装衬底；
在所述封装衬底上安装一第一芯片，该芯片具有大体在其中心部分上的中心焊盘；
使用连接导线电连接所述封装衬底和至少一个所述中心焊盘；以及
在所述第一芯片上方层叠一第二芯片。
42.根据权利要求41所述的方法，其中，还包括在所述中心焊盘外侧的所述第一芯片上形成绝缘支撑结构。
43.根据权利要求42所述的方法，其中，还包括在层叠所述第二芯片前，在所述第一芯片上在所述绝缘支撑结构之间形成一插入层。
44.根据权利要求41所述的方法，其中，所述第二芯片包括在其底部的一绝缘带。
45.一种形成多芯片封装的方法，该方法包括：
提供一上面设有键合指的封装衬底；
在所述封装衬底上安装一第一芯片，该芯片具有大体在其中心部分上的中心焊盘；
在位于所述中心焊盘的外侧的所述第一芯片上形成绝缘支撑结构；
使用连接导线将一个所述键合指与至少一个所述中心焊盘电连接；以及
在所述连接导线上方层叠一第二芯片并且覆盖所述绝缘支撑结构。
46.根据权利要求45所述的方法，其中，所述形成绝缘支撑结构包括使用分配技术。
47.根据权利要求45所述的方法，其中，在使用连接导线将一个所述键合指与至少一个所述第一焊盘电连接之后形成绝缘支撑结构。
48.根据权利要求47所述的方法，其中，使所述连接导线穿过所述绝缘支撑结构。
49.根据权利要求45所述的方法，其中，所述支撑结构沿所述第一芯片的两相对侧延伸。
50.根据权利要求49所述的方法，其中，所述支撑结构沿所述第一芯片的两相对边以线形延伸。
51.根据权利要求45所述的方法，其中，所述支撑结构包括多个分离的堆形结构。
52.根据权利要求45所述的方法，其中，还包括在层叠所述第二芯片之前，在所述绝缘支撑结构之间的所述第一芯片上形成一插入层。
53.根据权利要求52所述的方法，其中，形成所述插入层包括在所述第一芯片上形成一插入层材料，其中，层叠一第二芯片包括朝所述第一芯片的周缘表面铺展所述插入层材料。
54.根据权利要求45所述的方法，其中，所述第二芯片包括在其底面上的一绝缘带。
55.一种晶片层封装方法，包括：
提供一具有集成电路芯片的晶片，所述芯片具有大体在其中心部分上的中心焊盘；
在至少一个所述芯片上形成绝缘支撑结构，该绝缘支撑结构位于中心焊盘外侧；以及
单分所述芯片。
56.根据权利要求55所述的方法，其中，形成绝缘支撑结构包括使用分配技术。
57.根据权利要求55所述的方法，其中，形成绝缘支撑结构包括使用丝网印刷技术。
58.根据权利要求55所述的方法，其中，还包括：
提供一上面设有键合指的封装衬底；
在所述封装衬底上安装具有所述绝缘支撑结构的被单分的芯片之一；
使用连接导线将一个所述键合指与至少一个所述中心焊盘电连接；以及
在所述连接导线上方层叠另一芯片并覆盖所述绝缘支撑结构。
CNA2004100477958A 2003-04-08 2004-04-08 半导体多芯片封装和制备方法 Pending CN1551351A (zh)

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CN109906507A (zh) * 2016-10-26 2019-06-18 硅工厂股份有限公司 多芯片结构的半导体器件及使用其的半导体模块
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CN108010898A (zh) * 2017-11-02 2018-05-08 上海玮舟微电子科技有限公司 一种芯片封装结构
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TWI258823B (en) 2006-07-21

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