TWI258823B - Semiconductor multi-chip package and fabrication method - Google Patents
Semiconductor multi-chip package and fabrication method Download PDFInfo
- Publication number
- TWI258823B TWI258823B TW093109027A TW93109027A TWI258823B TW I258823 B TWI258823 B TW I258823B TW 093109027 A TW093109027 A TW 093109027A TW 93109027 A TW93109027 A TW 93109027A TW I258823 B TWI258823 B TW I258823B
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- Taiwan
- Prior art keywords
- wafer
- chip package
- semiconductor multi
- insulating support
- disposed
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 77
- 238000000034 method Methods 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 235000012431 wafers Nutrition 0.000 claims description 207
- 125000006850 spacer group Chemical group 0.000 claims description 44
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 23
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000004413 injection moulding compound Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims 4
- 239000013078 crystal Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 238000000465 moulding Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000166541 Plumeria alba Species 0.000 description 1
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Classifications
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Description
1258823 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種半導體元件,且特別是有關於一 種半導體多晶片封裝(semiconductor multi-chip package)及其製造方法。 【先前技術】 傳統半導體晶片不是中央焊墊配置結構(center pad configuration)就是周圍焊墊配置結構(peripherai pad configuration),其中,中央焊墊配置結構中的焊墊12係 形成在晶片的中央區域上’而周圍焊墊配置結構中的焊塾 1 4係形成在晶片的周圍區域上。圖1 A %示為具有中央焊塾 配置結構之半導體晶片的平面示意圖,而圖1B繪示為具有 周圍焊墊配置結構之半導體晶片的平面示意圖。中央焊塾 配置結構通常較適合達到半導體元件的高速度操作。 近年來’半導體工業花費相當多的資源在製造能夠滿 足南速度、南封裝密度以及多功能需求的半導體多晶片封 裝。由於上述努力,業界已提出了包含多個具有周圍焊塾 配置結構之堆豐晶片(stacked chips)的半導體多晶片封 裝。 曰曰、 圖2繪示為其中一種傳統多晶片封褒。請參照圖2,— 半導體多晶片封裝包括多個具有周圍焊墊配置結構之堆義 晶片2 0 ’ 4 0。堆疊晶片4 0係藉由一間隙物(s p a c e r ) 3 〇而堆 疊在另一堆疊晶片20的頂部。很不幸的,在圖2的多晶片 封裝中’並無法使用具有中央焊墊配置結構的晶片作為下 方的晶片(1 〇 w e r c h i p),原因在於中央焊墊之間並無法提
1258823 五、發明說明(2) 供足夠的空間以供間隙物3 0設置。 圖3繪示為一種傳統多晶片封裝300,其包括_下士曰u t t 广万晶片 3 2,其中下方晶片3 2原本為中央焊墊配置結構,咅即,下
方晶片3 2的中央區域上原本形成有中央焊墊線 ^ I 繪示)。 回” Q未 圖4與圖5繪示為將中央焊墊線路圖案36重新分佈至 圍焊墊38的技術,其中周圍焊墊38是實際上進行打線製程 (whe bonding process)的位置。請參照圖3至圖5、、,^二 例子中的傳統多晶片封裝3 0 0包括多個原本為中央配 置結構之堆疊晶片32,34。堆疊晶片32,34上之中央 線路圖案36係藉由重配置圖案39由中央區域重新分佈至 圍區域。 ° 換言之,中央焊塾線路圖案36係透過重配置圖率39而 ,周圍焊侧連接。此作法使得間隙物37能夠設置在下方 日日片32上的周圍焊墊38之間,以形成一多曰 而此多晶片封裝30 0包括多數個呈右成中/二片封裝3 0 0, 之摊聶曰伽祕Λ 有中央焊塾線路圖案36 之堆:i晶片3 2與堆豐晶片3 4。 然而,重新分佈焊塾線路圖案的成本相當高, 與封裝之信賴性仍未達到預_水準。因此,五人 一 性高且成本適當的半導體多晶片封裝方二: 有中央焊墊配置結構的晶片進行封裝。 — 【發明内容】 t 依據本發明的原則,可利用 曰Η决制你山古—☆ j用具有中央焊墊配置結構的 曰曰片未衣作出尚禮度之半導體多晶片封裝。本發明例如可 13420pif.ptd 第8頁 1258823
五、發明說明(3) 藉由現行的組裝設備完成,不需要使用到高成本 性不佳的焊墊重配置製程(pad redlstributiQn 及信賴 processes) 〇 依照本發明之一較佳實施例,多晶片封裝 具有多數個焊接手指之封裝基材。一第一 a 如包括一 裝基材上’此第一晶片上的一中央部分上較佳包:^於封 第一焊墊。多數個絕緣支撐結構較佳係配置於=夕數個 以及上述第一焊墊之間。焊線較佳係連接於其 晶片上 ::與至少其中一個第—焊墊之間。料的二部份::埤接 錯由絕緣支撐結構而與第一晶片分離。二s 奴佳係 置於焊線以及絕緣支揮結構上方。 到如係配 為讓本發明之上述和其他目#、特徵 易懂,下文特舉一較佳杂浐你丨* M人 霞,’’、占此更明顯 說明如下。 佳“例,並配合所附圖式,作詳細 【實施方式】 _ 00本^ $將舉ώ乡種實施例並搭配所附®示進行^ 既明入下。然巾,值得注意的是,本發明所舉Ϊ:::細的 !列與細節上可作適當輸文,本發明的涵蓋範;::在 :::述之實施例。此外,w施例係用以: 技術者闡述本發明的精神。 …、S忒項 圖12繪示為依照本發明一較佳實 睛參昭圖1 9 ,夕B u丄 又日日;ΐ封叙。 …、ϋ 2 夕日日片封裝4 00例如包括一呈有吝I w & 手指220之封裝美姑9nn 曰七& ”有夕數個焊接 晶片210,此第:二片焊墊配置結構之第-弟 Μ片210具有多數個形成在其中央部分之
1258823 五、發明說明(4) 第一焊墊215。第一晶片210較佳係配置於封裝基材2〇〇 上。 絕緣支撐結構2 6 0較佳係形成在第一晶片2丨〇上,且位 於第-焊墊215的外側。絕緣支撐結構26〇例如係藉由位於 其間之第一焊墊215而彼此分離,並且沿著第一晶片21〇的 二對邊分佈。絕緣支撐結構2 6 0例如係沿著第一晶片21〇之 至少兩個對邊的周圍而延伸成條狀(請參照圖9 )。 然而,絕緣支撐結構2 6 0並不僅限定於條狀,豆他形 狀亦屬於本發明之範疇。舉例而言,絕緣支撐結構26〇例 如為多個彼此分離,且沿著第一晶片21〇的邊緣配置之丘 狀結構(mound-like structure)。絕緣支撐結構26〇亦可 以是形成在第一晶片21 0的角落上,如圖j 4A〜圖j 4B所 不。與條狀之絕緣支撐結構2 6 〇相較,採用彼此分離的丘 狀支撐結構,由於形成絕緣支撐結構26〇所需要材料量的 減少,其製造成本與製程時間將可降低。此外,絕緣支撐 結構2 60並不僅限定是圖9中所繪示之直線形條狀結構。如 波浪條狀等其他形狀亦屬於本發明之範疇。再者,依據其 製造目的,本發明可於第一晶片21 〇之對邊上形成一個以、 上的條狀絕緣支撐結構2 6 0。 焊線230較佳係連接於其中一個焊接手指22〇與至少其 中一個第一焊墊215之間。焊線230較佳係藉由絕緣支撐結 = 260而與第一晶片21〇分離。原則上,焊線23〇的頂部實 質上不應該於絕緣支撐結構2 β 〇的頂部。具有多數個第二 焊墊3 1 5之第二晶片3 1 0較佳係配置於焊線2 3 〇上方,並且
1258823 五、發明說明(5) 位於絕緣支撐結構2 6 0的上方 圖1 3繪示為依照本發明另一較佳實施例之多晶片封 裝。請參照圖1 3,焊線2 3 0例如係穿過絕緣支撐結構2 6 〇, 而不是位於絕緣支撐結構2 6 0上方。在此架構中,絕緣支 撐結構2 6 0將可直接支撐住第二晶片3 1 表 然而’在本發明另一較佳實施例中,依據其製造目 的,焊線230亦可不需直接接觸絕緣支撐結構26〇,意即, 焊線2 3 0例如可亦非接觸的方式排列於條狀或是彼此分離 之丘狀絕緣支撐結構2 6 0上方,或是沿著條狀或是彼此分 離之丘狀絕緣支撐結構2 6 0排列。 刀 圖11繪示為依照本發明又一較佳實施例之多晶片封 t。请參照圖11 ’多晶片封裝4 〇 〇較佳包括一配置於第一 晶片2 1 0與第二晶片3 1 0之間的間隙物2 7 〇,以將二者黏 著。間隙物2 7 0可支撐第二晶片3 1 〇 ,以避免第二晶片3工〇 與連接至第一晶片2 1 0之焊線2 3 0接觸。間隙物2 7 〇較佳係 將一間隙物材料1 7 0 (請參照圖1 〇 )置於彼此分離之絕緣 支樓結構2 6 0之間所形成,間隙物材料1 了 〇例如係採用一不 具有填料(如二氧化矽)之環氧樹脂。然而,本發明之其 他實施例亦可不使用間隙物2 70,而使用絕緣支撐結構26〇 及/或絕緣貼片340以支撐住第二晶片31〇,並使第二晶片 310與焊線230電性絕緣。 @ 卜请再參照圖1 2,多晶片封裝4 0 0例如更包括一配置於 第二晶片310與焊線230之間的絕緣貼片34〇,以使得二者 彼此電性絕緣。絕緣貼片340較佳係配置於第二晶片3 i 〇的 13420pif.ptd $ 11頁 1258823 五、發明說明(6) 下表面上。絕緣貼片340例如係直接接觸焊線230 (未繪示 )。此外,當焊線2 3 0是穿過絕緣支撐結構2 6 0時(如圖1 3 或圖1 4B所示),絕緣貼片34 0亦可係直接與絕緣支撐結構 2 6 0接觸。在其他實施例中,絕緣貼片3 4 0亦可以是直接於 間隙物2 70接觸,而不與焊線23 0或是絕緣支撐結構260接 觸。 多晶片封裝4 0 0例如更包括一環氧樹脂注模化合物 (epoxy molding compound ,EMC)350 ,以將第一晶片210 以及第二晶片3 1 〇包覆。雖圖中未繪示,但當第一晶片2 1 〇 上未形成有間隙物2 7 0時,環氧樹脂注模化合物3 5 0例如可 配置於第一晶片2 1 0與第二晶片3 1 0之間,以取代間隙物 270。 製造方法 上述之半導體多晶片封裝4 〇 〇的較佳製造方法將搭配 圖6至圖1 2進行詳細之說明。請參照圖6,半導體多晶片封 裝40 0首先係將一下方(或第一)半導體晶片21〇設置於一 封農基材2 0 0上。上述設置晶片的動作例如可藉由傳統技 f來成。接著’可利用具有塗佈單元之傳統晶片黏著機 台(die-bonder)提供一黏著物240,以將黏著物240塗佈於 封裝基材2 0 0上。此外,黏著物24〇例如係採用常用於半導 體封裝製程中的傳統黏著材料。 封裝基材2 0 0例如為一印刷電路板或是其他封裝基 材,例如導線架(lead frame)或是線路貼片^wiring 土 tape)。封裝基材2〇〇較佳具有多數個焊線手指(或是線路
13420pi f.ptd 第12頁 1258823
接點)2 2 Ο ’以電性連接於封妒 間。第一晶片210較佳且有多數二^志/、/办一日日片21〇之 -焊墊(中央焊墊)二有 成在其中央部分的第 ^甲夬谇墊)215。下方半導體晶片( 曰 210較佳係利用黏著物24〇貼附於封裝基材2〇〇上。曰曰 非導ΪΪ,Γμ絕緣支撐結構26°例如係藉由提供液態的 =體%乳树月日或疋其他任何適合之非導體絕緣材料,如 'a型黏著物(hybrid type adhedv^、矽型黏著物 (SlllC〇n type adhesive)或薄膜型黏著物(film type adhesive),於下方晶片2i〇的周圍表面(即周圍區域的表 上而形成.。上述動作可使用傳統技術完成,例如塗佈 技術(dispensing technique)。用以提供黏著物於封裝基 材2 0 〇上之傳統晶片黏著機台内的塗佈單元例如可用以提 供一環氧樹脂於下方晶片21 〇的周圍表面上。絕緣支撐結 構26 0例如係沿著下方晶片21〇的周圍區域排列成條狀(請 參照圖9),另外,絕緣支撐結構26〇亦可以是由多個與中 央焊墊2 1 5對齊且彼此分離排列之丘狀結構所構成。 之後’上述之完成結構較佳係經過依約攝氏丨〇 〇度或 更高溫的熱處理,以將絕緣支撐結構26〇中的環氧樹脂以 及黏著物240固化,進而使得絕緣支撐結構26〇能夠形成於 下方晶片2 1 0的周圍區域上。絕緣支撐結構2 6 〇的寬度d丨較 佳係小於焊墊215中央到第一晶片21〇邊緣之一最近距離d2 的一半。此外,絕緣支撐結構2 6 0之高度h較佳係介於25微 米至2 0 0微米之間。 請參照圖8,部分焊接手指2 2 0較佳係透過第一焊線
13420pif .pt(j 第13頁 1258823 五、發明說明(8) 23 0電性連接至第一焊墊21 5上,而第一焊線230的材質例 如為金或疋銅專導電材料。打線製程(wire bonding process)例如係利用擠入接合技術(wedge bonding technique)或是凸塊轉換為焊球之接合技術(bump reverse ball bonding technique)等傳統技術進行,但 非限定只有這些技術。打線製程例如係在第一晶片2丨〇之 中央部分上的中央焊墊2 15的直接進行。第一焊線23 0例如 係與纟巴緣支撐結構2 6 0的頂表面直接接觸(意即,第一焊 線2 3 0係直接配置於絕緣支撐結構2 6 〇上),如區域a所繪 不。此外,焊線2 3 0亦可穿過絕緣支撐結構2 6 〇 (參照圖i 3 )’或是位於絕緣支撐結構2 6 0的上方,而不與絕緣支撐 結構2 6 0接觸。本發明使用絕緣支撐結構26〇將可改善習知 技術所存在的問題,如焊線下彎(sagging)的問題可以被 改善。 凊苓照圖1 0,間隙物材料1 7 0較佳係提供於下方晶片 210的表面上。間隙物材料170例如為_液體,且其材料例 如與形成絕緣支撐結構26 0之材料相同。間隙物材料17〇例 如係使用傳統的塗佈技術提供。 清芩照圖11 ’上方晶片(第二晶片)31 0係設置於第 -晶片210上。弟二晶片310例如具有中 墊配置、ΐ構。焊線230的高度與形狀較佳係控制 ,適:乾圍’:使得焊線230不與第二晶片31〇的下表面接 本貫施例 焊線230例如具有低焊線高纟,且具有 貝貝平坦部分’以利第二晶片310堆疊於第一晶片21〇上。
1258823 五、發明說明(9) 因此,封裝體厚度可以縮減,且焊線2 3 0與第二晶片3 1 0之 間不必要之接觸(unwanted contact)所導致的元件不合格 (device failure)情況也可以避免。 苐一晶片3 1 0的下表面上可選擇性地配置一絕緣貼片 340。絕緣貼片340可避免第二晶片310的下表面與第一焊 線2 3 0接觸,以使得第二晶片3 1 〇能夠更接近第一晶片2 1 0 配置,進而縮減整個封裝體的厚度。 然而,絕緣貼片3 4 0亦絕非必須,即使不使用絕緣貼 片340,本發明同樣可利用配置在第一晶片2 1 0與第二晶片 3 1 0之間的間隙物2 7 0及/或絕緣支撐結構2 6 0,以於焊線 2 3 0與第二晶片3 1 0之間獲得足夠的隔絕空間。舉例而言, 若焊線2 3 0係穿過絕緣支撐結構26 0時(如圖13或圖14B所 繪示),第一晶片2 1 0與第二晶片3 1 0之間便不需要使用絕 緣貼片3 4 0。在上述之貫施例中,焊線2 3 0較佳係距離第二 晶片3 1 0的下表面一段足夠的距離,以於其間提供足夠的 隔絕空間。因此,本發明的多個實施例中,焊線2 3 0的高 度可被縮減,同時也使得整個封裝體的度厚度縮減。 在將第二晶片3 1 0設置或是貼附於第一晶片2 1 0上的期 間,間隙物材料1 7 0會被下壓並向外分散至第一晶片2 1 0的 周圍表面上。在上述製程中,沿著第一晶片2 1 0長度方向 延伸之絕緣支撐結構2 6 0 (請參照圖9 )係用以作為屏障結 構(d a m s t r u c t u r e ),以使得間隙物材料1 7 0能夠維持在第 一晶片2 1 0的邊界内,而避免其外漏至封裝基材2 0 0上。雖 然絕緣支撐結構2 6 0亦可以排列在第一晶片2 1 0的兩個以上
13420pif.ptd 第15頁 1258823 五、發明說明(10) 之側邊上,但由於在將第二晶片3 1 0設置或貼附第一晶片 2 1 0上時,間隙物材料1 7 〇内可能會有孔洞(v 〇 i d s )產生’ 故本實施例所採用的絕緣支撐結構2 6 0較佳係僅沿著第一 晶片2 1 0的二對邊延伸。 藉由絕緣支撐結構2 6 0避免間隙物材料1 7 0流出第一晶 片1 2 0的側邊,便能夠維持間隙物2 7 0的厚度。此外,藉由 避免間隙物材料1 7 〇流到第一晶片與封裝膠體 (h 〇 u s i n g) 3 5 0之間’便能夠避免二者之間的黏著性變差。 舉例而言,若間隙物材料1 7 0會從第一晶片2 1 0的邊緣洩 漏,具有較差黏著特性之間隙物材料1 7 0會位於第一晶片 2 1 0以及包覆住第一晶片2 1 0與第二晶片3 1 0的環氧樹脂注 模化合物之間,進而使得第一晶片2 1 0與封裝膠體3 50 (請 參照圖1 2 )之間強大的直接黏著性(d i r e c t a d h e s i ο η)降 低。間隙物材料1 7 0的外漏將會使得整個封裝體的信賴性 (rel iabi 1 i ty)降低。在第二晶片310與第一晶片210的貼 附過程中,絕緣支撐結構2 6 0對於第二晶片3 1 0與第一晶片 2 1 0之間平行關係的維持有很大的幫助。此外,絕緣支撐 結構2 6 0改善了封裝良率,並且減低了整個封裝體的厚 度。 在第二晶片3 1 0設置於第一晶片2 1 〇之後,間隙物材料 1 7 0可藉由熱處理而固化以形成間隙物2 7 0,其固化溫度約 介於攝氏50度至攝氏20 0度之間。間隙物2 7 0使得第一晶片 2 1 0與第二晶片3 1 0能夠相互結合在一起,並且確保焊線 2 3 0能夠位在固化後之間隙物2 7 0中。在轉移注模過程中,
13420pif.ptd 第16頁 1258823 五、發明說明(11) 由於間隙物2 7 0能夠避免第一焊線2 3 〇因注模化合物之模流 而沖斷(sweeping)或彎曲(bending),因此傳統的封模 (encapsulation)問題,如焊線被包覆材料沖斷或下彎 (sagging)等現象可有效避免。此外,間隙物270亦提供了 第一晶片2 1 0與第二晶片3 1 0之間的隔絕空間。 其他部分的焊接手指2 2 0較佳係透過第二焊線3 3 〇而電 性連接至第二晶片310上之第二焊墊315上。此動作亦可使 用上述之傳統打線技術來完成。第二晶片丨3 〇上例如同樣 具有絕緣支撐結構,而這些絕緣支撐結構係利用與上述相 似之方法形成。 請參照圖1 2,接著對上述之完成結構進行一注模製 程,以形成一封裝膠體350。此步驟可使用傳統的環氧樹 月曰庄模化合物注模製程(molding process using EMC)。 然而’對於熟習該項技術者而言,封裝膠體3 5 〇亦可使用 其他的注模製程。如前述,在轉移注模過程中,間隙物 2 7 0旎夠避免第一焊線2 3 〇因注模化合物之模流而沖斷或彎 曲。因此,與具有焊線被包覆材料沖斷或下彎等現象之傳 統封裝體相較,本發明的打線信賴性以及封裝體之信賴性 月匕夠獲得貫質上的改善。此外,間隙物2 了 〇亦提供了第— 晶片2 1 0與第二晶片3 1 〇之間的隔絕空間。一導電球格陣列 (conductive ball array),如焊球陣列(solde;r ball array) ’例如係形成在封裝基材2〇〇的丁表面上,以構成 一球格陣列封裝(BGA Package),進而與外界系統相連 接。
13420pi f.ptd 第17頁 1258823 五、發明說明(12) 其他實施例 圖1 3綠示為利用本發明精神之其他實施例。請參照圖 1 3 ’除了絕緣支撐結構26 0係在第一焊線230之後形成之 外,本實施例與圖6〜圖】3B所舉之實施例相似。據此,在 本實施例中’第一焊線23〇例如係穿過絕緣支撐結構26 0。 如詳細之實施例所述,第一焊線2 3 〇係穿過絕緣支撐結構 260的中間部分(middle p〇rt ion),以使得第一焊線23 0能 夠固疋(fix)或是侷限(secure)於絕緣支撐結構2g〇中。本 貫施例的優點是第一焊線2 3 〇頂部的高度係低於絕緣支撐 結構2 6 0的高度。由於第二晶片31〇的下表面能夠充分地與 焊線2 3 0隔離,故焊線被沖斷或是彎曲的問題有效地被避 免,且不需使用絕緣貼片340。第二晶片310也能夠盥第一 晶片210維持平行。 ” 根據本發明另一實施例,本發明之精神亦可應用於單 晶片封裝(single-chip package)。在本實施例中,、 成絕緣支撐結構26 0之後,對上述之完成結構進行一注^ 製程(molding process)以及一形成焊球陣列的製 ’ +、 單一晶片封裝的實施例中,在注膜的過程中,絕^王。在 構2 6 0對於避免第一焊線23 0被沖斷以及彎曲 =了支樓結 的幫助。 、場有很大 晶圓級製造技術 圖1 5以及圖1 6繪示為依照本發明另_梦、^ 圓級製造技術。除了絕緣支撐結構2 6 0係在米成曰 ^之晶 晶圓級製造製程與圖6〜圖1 3B中所解釋之制^ Λ _圓上, 心衣轾相似。
13420pif.ptd 第18頁 1258823 五、發明說明(13) 々 請參照圖1 5,晶圓包括多數個第一晶片2 1 0,每一個 第 晶片2 1 0表面上皆具有絕緣支撐結構2 6 0。絕緣支撐結 構260例如係利用與前述塗佈技術相似之晶圓級塗佈製程 (Wafer~level dispensing technique)。絕緣支撐結構 亦~T係利用網板印刷技術(s c r e e n — p r ^ n t i n g technique)所形成。圖丨6繪示為用以形成條狀絕緣支撐結 ,260之網印遮罩(screen mask)402。網印遮罩402亦可以 =使用夕個彼此分離、散置(hterSpersed)的 結f所構成。網板印刷技術對於絕緣支撐結構26〇的寬度 與间f能夠提供較佳的控制。在形成絕緣支撐結構2 6 0之 ^ ’晶圓會被切割以將第一晶片2丨〇單體化。接著根據本 舍:的精神進行上述的製程或方法,以形成多晶片封裝。 本發明在晶圓層級形成絕緣支撐結構260的方法亦可應用 在具有單一晶片的封裝體中。 的多晶片封奘 曰圖丨/綠示為依照本發明又一實施例具有兩個以上堆疊 二π片之多-晶片封裝。請參照圖1 7,本實施例之多晶片封裝 包括t個或是更多個堆疊晶片510 ’ 520 ’ 530 ’ 540。 ,I,化說明’圖示中所有的焊線5丨2僅繪示其係連接到 火干接手寸曰5 1 4上。然、而’熟習該項技術者應知,個別 I t 5 1 2可依所需連接至對應之焊接手指5 1 4上。每一個堆 =曰曰片5 1 0,5 2 0,5 3 0,5 4 0例如具有中央焊墊配置結構或 疋周圍~塾配置結構。並非所有的堆疊晶片5 1 〇,5 2 〇, 5 3 0,5 4 0都需要具有相同的焊墊配置結構。
1258823
13420pif.ptd 第20貢 1258823 圖式簡單說明 圖1 A繪示為習知技術中具有中央焊墊配置結構之半導 體晶片的平面不意圖。 圖1 B繪示為習知技術中具有周圍焊墊配置結構之半導 體晶片的平面示意圖。 圖2繪示為具有多個晶片之傳統多晶片封裝的剖面示 意圖,其中之各晶片具有周圍焊墊配置結構。 圖3繪示為具有一晶片之傳統多晶片封裝的剖面示意 圖,其中之晶片具有一由周圍焊墊重新配置而成之中央焊 塾 ° 圖4繪不為傳統半導體晶片之平面不意圖’其具有一 由周圍焊墊重新配置而成之中央焊墊。 圖5繪不為傳統半導體晶片之剖面不意圖’其具有一 由周圍焊墊重新配置而成之中央悍墊。 圖6至圖1 2繪示為依照本發明一較佳實施例多晶片封 裝的製造流程剖面示意圖。 圖1 3繪示為依照本發明另一較佳實施例絕緣支撐結構 的剖面示意圖。 圖1 4A繪示為依照本發明一較佳實施例具有絕緣支撐 結構之半導體晶片的平面示意圖。 圖1 4B繪示為依照本發明一較佳實施例具有絕緣支撐 結構之半導體晶片的平面示意圖。 圖1 5繪示為依照本發明另一較佳實施例晶圓級封裝的 平面示意圖。 圖1 6繪示為網印遮罩的平面示意圖,其係用以形成圖
13420pi f.ptd 第21頁 1258823
13420pif.ptd 第22頁 1258823 圖式簡單說明 3 4 0 :絕緣貼片 3 5 0 :封裝膠體 4 0 0、5 0 0 :多晶片封裝 4 0 2 :網印遮罩 510 、5 2 0 、5 3 0 、5 4 0 :堆疊晶片 5 1 2 :焊墊 5 1 4 :焊接手指
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Claims (1)
1258823 六、申請專利範圍 1. 一種半導體多晶片封裝,包括: 一封裝基材,具有多數個焊接手指; 一第一晶片,具有多數個配置於該第一晶片之一中央 部分上之第一焊墊,其中該第一晶片係配置於該封裝基材 上; 多數個絕緣支撐結構,配置於該第一晶片上,並且位 於該些第一焊墊的外側; 一焊線,連接於該些焊接手指其中之一與該些第一焊 墊至少其中之一之間;以及 一第二晶片,具有多數個第二焊墊,其中該第二晶片 係配置於該些焊線上方,並且位於該些絕緣支撐·結構上 方。 2. 如申請專利範圍第1項所述之半導體多晶片封裝, 其中該些絕緣支撐結構係沿著該第一晶片的二對邊延伸。 3. 如申請專利範圍第2項所述之半導體多晶片封裝, 其中該些絕緣支撐結構包括延伸為一條狀。 4. 如申請專利範圍第3項所述之半導體多晶片封裝, 其中該悍線包括穿過該些絕緣支撐結構。 5. 如申請專利範圍第3項所述之半導體多晶片封裝, 其中該焊線包括位於該些絕緣支撐結構上方,且該焊線未 與該些絕緣支撐結構直接接觸。 6. 如申請專利範圍第3項所述之半導體多晶片封裝, 其中該焊線係直接配置於該些絕緣支撐結構上。 7. 如申請專利範圍第1項所述之半導體多晶片封裝,
13420pif.ptd 第24頁 1258823 六、申請專利範圍 其中該些絕緣支撐結構包括多數個分離的丘狀結構 (mound- 1 ike structures) 〇 8 ·如申請專利範圍第7項所述之半導體多晶片封裝, 其中該些分離的丘狀結構包括分別配置於該第一晶片的多 數個角落。 9 ·如申請專利範圍第7項所述之半導體多晶片封裳, 其中該焊線包括穿過該些絕緣支撐結構。 I 0 ·如申請專利範圍第7項所述之半導體多晶片封裝, 其中該焊線包括位於該些絕緣支撐結構上方,且該烊線未 與該些絕緣支撲結構直接接觸。 II ·如申請專利範圍第7項所述之半導體多晶片封裝, 其中該焊線係直接配置於該此絕緣支樓結構上。 1 2.如申請專利範圍第1項所述之半導體多晶片封裝, 更包括一間隙物,配置於該第一晶片與該第二晶片之間。 1 3 ·如申請專利範圍第丨2項所述之半導體多晶片封 裝,其中該間隙物的一實質部分係位於該些絕緣支撐沾 之間,且位於該第一晶片上。 〜構 1 4 ·如申請專利範圍第丨2項所述之半導體多晶片封 裝,其中該間隙物係支樓該第二晶片以必面該第二晶 該焊線接觸。 巧為 1 5 ·如申明專利範圍第1 2項户斤述之半導體多晶片封 衣其中該間隙物係採用與該些絕緣支撐結構相同之柯 所形成。 、一 科 16.如申請專利範圍第12項所述之半導體多晶片封
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1258823 —---- 申請專利範圍 裝’其中該間隙物俜梃 x a . , 成。 ^用一不具有填料之環氧樹脂而形 更包1括7如範圍第1項所述之半導體多晶片封裝, 18如申車片,配置於該第二晶片與該焊線之間。 发.上甲峋專利範圍第1 7項所述之半導體多晶片 〃中6亥絕緣貼片包括與該焊線直接接觸。 2 ·如申請專利範圍第1 7項所述之半導體多晶片封 ,、中該絕緣貼片包括與該些絕緣支撐結構直接接觸。 复 〇 ·日如申請專利範圍第1項所述之半導體多晶片封裝, ” 该焊線的頂部未高於該些絕緣支撐結構的頂部。 21 ·如申請專利範圍第1項所述之半導體多晶·片封裝, 匕括封裝膠體,以將該第〆晶片與該第二晶片包覆。 2 2 ·如申請專利範圍第2 1項所述之半導體多晶片封 ’其中該封裝膠體包括一環氧樹脂注模化合物。 2 3 ·如申請專利範圍第2 1項所述之半導體多晶片封 ,其中該環氧樹脂注模化合物係配置於該第一晶片該第 晶片之間。 裝 裝 更 裴 裝 2 4 ·如申請專利範圍第1項所述之半導體多晶片封裝, 其中該封裝基材包括一導線架(lead frame)或一線路貼片 (wiring tape) ° 2 5 ·如申請專利範圍第1項所述之半導體多晶片封裝, 其中該些絕緣支撐結構的寬度小於該些焊墊中央到該第_ 晶片邊緣之一最近距離的一半。 2 6 ·如申請專利範圍第1項所述之半導體多晶片封裝,
1258823 六、申請專和範圍 其中該些絕緣支撐結構之高度係介於2 5微米至2 0 0微米之 間。 2 7.如申請專利範圍第1項所述之半導體多晶片封裝, 其中該些第二焊墊係配置於該第二晶片的一周圍區域上。 2 8.如申請專利範圍第1項所述之半導體多晶片封裝, 其中該些第二焊墊係配置於該第二晶片的一中央區域上。 2 9.如申請專利範圍第1項所述之半導體多晶片封裝, 更包括一或多數個晶片,堆疊於該第二晶片上。 3 0.如申請專利範圍第2 9項所述之半導體多晶片封 裝,其中該些晶片中的至少一個晶片的焊墊位置係與其他 晶片的焊墊位置不同。 3 1.如申請專利範圍第1項所述之半導體多晶片封裝, 更包括一焊球陣列,配置於該封裝基材的一下表面,以形 成一球格陣列封裝。 3 2.如申請專利範圍第1項所述之半導體多晶片封裝, 其中該些絕緣支撐結構係彼此分離,且該些第一焊墊係位 於該些絕緣支撐結構之間。 3 3.如申請專利範圍第1項所述之半導體多晶片封裝, 其中該焊線係沿著該些絕緣支撐結構排列。 34. —種半導體多晶片封裝,包括: 一封裝基材,具有多數個焊接手指; 一第一晶片,具有多數個配置於該第一晶片之一中央 部分上之第一焊墊,其中該第一晶片係配置於該封裝基材
13420pif.ptd 第27頁 1258823
夕數個絕緣支撐結構,配置於該第一晶片上,並且位 於該些第一焊墊的外側; 力干、線’連接於該些焊接手指其中之一與該些第一焊 $少甘ψ夕_ /、T < 一之間,該焊線係藉由該些絕緣支撐結構與 该第一晶片分離; 一第二晶片’堆疊於該些焊線上方,並且位於該些絕 緣支樓結構上方;以及 一絕緣間隙物,配置於該第一晶片與該第二晶片之 間。 3 5 ·如申請專利範圍第34項所述之半導體多晶片封 I ’更包括: —導電球格陣列,配置於該封裝基材的一下表面上。 事,2·如申請專利範圍第34項所述之半導體多晶片封 = 其中該焊線具有一配置於該第二晶片下方之實質平坦 邵分。 7 ·種半導體多晶片封裝,包括: 一封裝基材; 夕一第一晶片,配置於該封裝基材上,該第一晶片具有 夕丈個配置於該第一晶片之一中央部分上之中央焊墊; ^ 第二晶片,堆疊於該第一晶片上,該第二晶片係電 性連^於該封裝基材;以及 多數個焊線,電性連接於該射裝基材與該些中央焊墊 之間。 … 38·如申請專利範圍第37項所述之半導體多晶片封
13420pif ·_ 第28頁 1258823 六、申請專利i圍........................................ 裝,更包括多數個絕緣支撐結構,配置於該第一晶片上, 並且位於該些中央焊塾外側。 3 9.如申請專利範圍第3 8項所述之半導體多晶片封 裝,更包括一間隙物,配置於該第一晶片與該第二晶片之 間。 4 0.如申請專利範圍第3 9項所述之半導體多晶片封 裝,更包括一絕緣貼片,配置於該第二晶片的一下表面 上。 4 1. 一種半導體多晶片封裝的製造方法,包括: 提供一封裝基材; 將一第一晶片配置於該封裝基材上,該第一晶片具有 多數個配置於該第一晶片之一中央部分上之中央焊墊; 藉由一焊線將該封裝基材與該些中央焊墊至少其中之 一電性連接;以及 堆疊一第二晶片於該第一晶片上。 4 2.如申請專利範圍第41項所述之半導體多晶片封裝 的製造方法,更包括於該第一晶片上以及該些中央焊墊外 側形成一絕緣支撐結構。 43.如申請專利範圍第42項所述之半導體多晶片封裝 的製造方法,其中在堆疊該第二晶片之前,更包括於該第 一晶片上以及該些絕緣支撐結構之間形成一間隙物。 4 4.如申請專利範圍第41項所述之半導體多晶片封裝 的製造方法,其中該第二晶片包括一絕緣貼片,配置於該 第二晶片的一下表面上。
13420pif.ptd 第29頁 1258823 六、申請專利範圍 4 5. —種半導體多晶片封裝的製造方法,包括: 提供一具有多數個焊接手指之封裝基材; 將一第一晶片配置於該封裝基材上,該第一晶片具有 多數個配置於該第一晶片之一中央部分上之中央焊墊; 於該第一晶片上以及該些中央焊墊外側形成一絕緣支 撐結構; 藉由一焊線將該些焊接手指其中之一與該些中央焊墊 至少其中之一電性連接;以及 堆疊一第二晶片於該焊線以及該些絕緣支撐結構上 方。 4 6.如申請專利範圍第4 5項所述之半導體多晶片封裝 的製造方法,其中該些絕緣支撐結構的形成方法包括塗佈 技術。 4 7.如申請專利範圍第45項所述之半導體多晶片封裝 的製造方法,其中該些絕緣支撐結構係在藉由一焊線將該 些焊接手指其中之一與該些中央焊墊至少其中之一電性連 接之後形成。 4 8.如申請專利範圍第47項所述之半導體多晶片封裝 的製造方法,其中該焊線包括穿過該些絕緣支撐結構。 4 9.如申請專利範圍第4 5項所述之半導體多晶片封裝 的製造方法,其中該些絕緣支撐結構係沿著該第一晶片的 二對邊延伸。 5 0.如申請專利範圍第4 9項所述之半導體多晶片封裝 的製造方法,其中該些絕緣支撐結構包括沿著該第一晶片
13420pif.ptd 第30頁 1258823 六、申請專莉範圍 的該些對邊延伸延伸為一條狀。 5 1.如申請專利範圍第4 5項所述之半導體多晶片封裝 的製造方法,其中該些絕緣支撐結構包括多數個分離的丘 狀結構。 5 2.如申請專利範圍第4 5項所述之半導體多晶片封裝 的製造方法,其中在堆疊該第二晶片之前,更包括於該第 一晶片上以及該些絕緣支撐結構之間形成一間隙物。 5 3.如申請專利範圍第5 2項所述之半導體多晶片封裝 的製造方法,其中該間隙物的形成方法包括於該第一晶片 上形成一間隙物材料,並藉由堆疊該第二晶片以將該間隙 物材料向外分散至該第一晶片的一周圍表面上。 5 4.如申請專利範圍第4 5項所述之半導體多晶片封裝 的製造方法,其中該第二晶片包括一絕緣貼片,配置於該 第二晶片的一下表面上。 5 5. —種晶圓級封裝方法,包括: 提供一具有多數個積體電路晶片之晶圓,該些晶片的 一中央部分具有多數個中央焊墊; 於該些晶片至少其中之一上形成多數個絕緣支撐結 構,該些絕緣支撐結構係位於該些中央焊墊的外侧;以及 將該些晶片單體化。 5 6.如申請專利範圍第5 5項所述之晶圓級封裝方法, 其中該些絕緣支撐結構的形成方法包括塗佈技術。 5 7.如申請專利範圍第5 5項所述之晶圓級封裝方法, 其中該些絕緣支撐結構的形成方法包括網印技術。
13420pif.ptd 第31頁 1258823 六、申請專利範圍 5 8.如申請專利範圍第5 5項所述之晶圓級封裝方法, 更包括: 提供一具有多數個焊接手指之封裝基材; 將具有該些絕緣支撐結構之該些晶片其中之一配置於 該封裝基材上, 藉由一焊線將該些焊接手指其中之一與該些中央焊墊 至少其中之一電性連接;以及 堆疊另一晶片於該焊線以及該些絕緣支撐結構上方。
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CN104835808A (zh) | 2015-03-16 | 2015-08-12 | 苏州晶方半导体科技股份有限公司 | 芯片封装方法及芯片封装结构 |
WO2018063188A1 (en) * | 2016-09-28 | 2018-04-05 | Intel Corporation | Compact wirebonding in stacked-chip system in package, and methods of making same |
CN109906507B (zh) * | 2016-10-26 | 2023-09-05 | 硅工厂股份有限公司 | 多芯片结构的半导体器件及使用其的半导体模块 |
AT519780B1 (de) * | 2017-03-20 | 2020-02-15 | Zkw Group Gmbh | Verfahren zum Herstellen von Bondverbindungen |
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CN109887850B (zh) * | 2019-02-18 | 2021-10-01 | 长江存储科技有限责任公司 | 一种3d封装多点焊接的方法及装置、设备及存储介质 |
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US5847445A (en) * | 1996-11-04 | 1998-12-08 | Micron Technology, Inc. | Die assemblies using suspended bond wires, carrier substrates and dice having wire suspension structures, and methods of fabricating same |
KR100297451B1 (ko) * | 1999-07-06 | 2001-11-01 | 윤종용 | 반도체 패키지 및 그의 제조 방법 |
US6531784B1 (en) * | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
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KR100401020B1 (ko) * | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지 |
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JP3688249B2 (ja) * | 2002-04-05 | 2005-08-24 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6683385B2 (en) * | 2002-04-23 | 2004-01-27 | Ultratera Corporation | Low profile stack semiconductor package |
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2004
- 2004-03-31 JP JP2004107243A patent/JP2004312008A/ja active Pending
- 2004-04-01 TW TW093109027A patent/TWI258823B/zh not_active IP Right Cessation
- 2004-04-06 DE DE200410018434 patent/DE102004018434A1/de not_active Ceased
- 2004-04-08 CN CNA2004100477958A patent/CN1551351A/zh active Pending
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2007
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US20080026506A1 (en) | 2008-01-31 |
JP2004312008A (ja) | 2004-11-04 |
TW200425357A (en) | 2004-11-16 |
DE102004018434A1 (de) | 2004-12-09 |
CN1551351A (zh) | 2004-12-01 |
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