CN1612340A - 具有多个倒装芯片的多芯片封装及其制造方法 - Google Patents

具有多个倒装芯片的多芯片封装及其制造方法 Download PDF

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Publication number
CN1612340A
CN1612340A CNA2004100832714A CN200410083271A CN1612340A CN 1612340 A CN1612340 A CN 1612340A CN A2004100832714 A CNA2004100832714 A CN A2004100832714A CN 200410083271 A CN200410083271 A CN 200410083271A CN 1612340 A CN1612340 A CN 1612340A
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China
Prior art keywords
flip
chip
group
projection
printed circuit
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CNA2004100832714A
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姜仁九
金震镐
安相镐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1612340A publication Critical patent/CN1612340A/zh
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Abstract

提供了具有至少两个倒装芯片的多芯片封装及其制造方法。该多芯片封装可以包括具有基板和形成在基板前表面上的多个互连线的印刷电路板。该至少两个倒装芯片可以层叠在该基板的前表面上。可以层叠所述倒装芯片使得所述倒装芯片的焊盘面对印刷电路板。第一组凸起可以置于第一倒装芯片的焊盘和多个线的第一组互连线之间。此外，第二组凸起可以置于该至少一个上倒装芯片的焊盘和多个线的第二组互连线之间。

Description

具有多个倒装芯片的多芯片封装及其制造方法
本申请要求2003年6月27日申请的韩国专利申请No.2003-0042730的优先权，这里引入其内容作为参考。
技术领域
本发明涉及半导体封装，更具体地说，涉及具有多个倒装芯片的多芯片封装及其制造方法。
背景技术
随着便携式电子设备的变小，安装在便携式电子设备中的半导体封装也在变小。此外，为了增加封装容量，已经采用在单个半导体封装中安装多个半导体芯片的技术，例如多芯片封装技术。
图1是常规的多芯片封装的剖面图。参考图1，可以将下芯片3和上芯片5叠置在印刷电路板1上。下芯片3的背表面可以通过粘合剂7接触印刷电路板1的顶表面，上芯片5的背面可以通过粘合剂9接触下芯片3的顶表面。在这种情况下，为了暴露形成在下芯片3边缘上的焊盘，上芯片5的宽度可以比下芯片3的宽度小，如图1所示。
下芯片3的焊盘和上芯片5的焊盘可以分别通过第一组键合线11和第二组键合线15与形成在印刷电路板1边缘上的互连线13电连接。
图1所示的多芯片封装可以采用常规的键合线将上芯片5和下芯片3电连接到印刷电路板1上的线13。即，第二组键合线15可以延伸到比上芯片5更高的水平面。这样，在减小用于封装键合线11和15以及芯片3和5的环氧成型化合物(epoxy molding compound)的厚度方面存在限制。此外，这些键合线可以作为电感和/或电阻以降低芯片3、5的高频特性。
图2是说明另一常规多芯片封装的透视图，图3是沿着穿过图2所示的下芯片和上芯片的中央部分的线截取的垂直截面图。
参考图2和3，可以依次将下芯片23和上芯片25叠置在印刷电路板21上。例如，上芯片25可以交叉放置在下芯片23上，如图2所示，下芯片23和上芯片25可以基本垂直。下芯片23可以具有与上芯片25相同的尺寸和/或功能。下芯片23的背表面可以通过粘合剂22接触印刷电路板21的顶表面，上芯片25的背表面可以通过粘合剂27接触下芯片23的顶表面。在这种情况下，上芯片25的长度可以比下芯片23的宽度大，如图2和3所示。这样，上芯片25可以具有“伸出部分”，例如不与下芯片23重叠的两端。
形成在下芯片23端部上的焊盘可以通过第一组键合线29与形成在印刷电路板21边缘上的第一组线31电连接。同样，形成在上芯片25端部上的焊盘可以通过第二组键合线33与形成在印刷电路板21边缘上的第二组线35电连接。为了形成第一和第二组键合线29和33，可以使用图3所示的常规键合线端头41。键合线端头41可以持有键合线43。
为了形成键合线29和33，端头41可以向下移向焊盘。结果，由端头41所持有的引线43接触焊盘，并且压力可施加给焊盘。在形成第二组键合线33期间伸出部分有可能弯曲，如图3箭头所示。伸出部分的弯曲会导致第二组键合线33的接触失效。伸出部分越长，第二组键合线33的接触失效率有可能越大。
日本专利特开No.06-302645公开了一种连接发光器件和光接收器件的方法。根据日本专利特开No.06-302645，发光器件基板安装在光接收器件基板上。光接收器件基板具有形成在其表面上的光接收器件，发光器件基板具有形成在其表面上的发光器件。发光器件基板安装在光接收器件基板上方，使得发光器件和光接收器件彼此面对。即，发光器件基板倒装并且位于光接收器件基板上方。可将透明隔离物置于光接收器件基板和发光器件基板之间。这样，发光器件与光接收器件间隔开。此外，光接收器件基板上的互连线通过多个层叠凸起与发光器件基板上的互连线电连接。
发明内容
本发明的示例性实施例提供了更薄和/或更小巧的多芯片封装。
在本发明的示例性实施例中，多芯片封装可以包括：包括具有上表面和下表面的基板的印刷电路板；包括第一芯片和第二芯片的至少两个芯片。在上表面上可以形成至少第一和第二多个互连线。第一芯片可以安装在基板的上表面上，多个第一凸起可以置于第一芯片的焊盘和多个第一互连线之间。第二芯片可以安装在第一芯片上。多个第二凸起可以置于第二芯片的多个焊盘和多个第二互连线之间。
在本发明的一示例性实施例中，多个第一凸起的每个凸起都是单个的柱状凸起(stud bump)。
在本发明的一示例性实施例中，多个第二凸起的每个凸起都是单个的焊接凸起(soldering bump)。
在本发明的一示例性实施例中，多个第二凸起的每个凸起都可以包括多个层叠的柱状凸起。
在本发明的一示例性实施例中，第二芯片可以交叉层叠在第一芯片上。
在本发明的一示例性实施例中，第二芯片可以具有比第一芯片更大的尺寸。
在本发明的一示例性实施例中，环氧树脂可以密封所述至少两个芯片和所述印刷电路板。在本发明的另一示例性实施例中，环氧成型化合物可以密封所述至少两个芯片和所述印刷电路板，并且可以覆盖第二芯片。这样，可以形成上多芯片封装(upper multi-chip package)。在本发明的另一示例性实施例中，下多芯片封装(lower multi-chip package)可以形成在基板的下表面上。下多芯片封装可以具有与上多芯片封装相同的结构。
在本发明的一示例性实施例中，第三芯片可以形成在第二芯片上，并且具有形成在与所述至少两个芯片相对的表面上的焊盘。多个键合线可以连接焊盘和形成在基板上的多个第三互连线。环氧成型化合物可以密封所述至少两个芯片、第三芯片和键合线。这样，可以形成上多芯片封装。在另一示例性实施例中，下多芯片封装可以形成在基板的下表面上，并且具有与上多芯片封装相同的结构。
在本发明的一示例性实施例中，第二组凸起的高度比第一组凸起的高度和下倒装芯片的高度的总和大。
其它示例性实施例涉及用于制造本发明的各种多芯片封装的方法。
附图说明
通过下面结合附图对示例性实施例的描述，本发明的上述和/或其它特征将变得更加显而易见，其中：
图1是一常规多芯片封装的剖面图；
图2是另一常规多芯片封装的透视图；
图3是图2所示常规多芯片封装的其它方向的剖面图；
图4是根据本发明一示例性实施例说明多芯片封装的剖面图；
图5是根据本发明另一示例性实施例说明多芯片封装的剖面图；
图6是根据本发明另一示例性实施例说明多芯片封装的剖面图；
图7是根据图4至6所示的示例性实施例说明倒装芯片层叠结构的一实例的透视图；
图8至12是说明图4的多芯片封装的制造方法的剖面图；
图13是说明图5的多芯片封装的制造方法的剖面图；
图14是说明图6的多芯片封装的制造方法的剖面图；
具体实施方式
下面将参考附图更全面地描述本发明，附图中示出了本发明的示例性实施例。然而，本发明可以通过不同的形式实施，并且不应解释为限于此处所描述的示例性实施例。此外，所提供的这些示例性实施例用于说明；本发明覆盖了本领域技术人员可以预期的各种形式和细节上的变化。
应注意，为了更清楚，图中放大了各个层的厚度和层叠封装中的区域，并且在不同的图中使用相同的附图标记表示相同的部件。
应注意，当某层直接形成在参考层或者基板上或者形成在覆盖参考层的其它层或者图形上时，就认为该层形成在另一层或者基板“上”。
图4是根据本发明一示例性实施例说明多芯片封装的剖面图。
参考图4，下倒装芯片53和上倒装芯片71可以依次层叠在印刷电路板的前表面上。该印刷电路板可以包括平的基板51、第一组线61a和/或第二组线61b，这两组线都形成在基板51的前表面上。下倒装芯片53可以包括面对印刷电路板的焊盘55。同样，上倒装芯片71也可以包括面对印刷电路板的焊盘73。这样，可以在焊盘55之间倒装芯片53的主表面上设置集成电路，也可以在焊盘73之间倒装芯片71的主表面上设置其它的集成电路。焊盘55可以放置在第一组线61a上方，焊盘73可以放置在第二组线61b上方。
在一示例性实施例中，上倒装芯片71可以具有比下倒装芯片53更大的尺寸，如图4所示。换句话说，上倒装芯片71可以具有比下倒装芯片53更大的宽度和/或更大的长度。而且，上倒装芯片71可以具有与下倒装芯片53不同的功能。第一组凸起57可以设置在焊盘55和第一组线61a之间。第一组凸起57的每一个凸起都可以是单个的柱状凸起。可以利用常规的引线键合技术在焊盘55上制造柱状凸起57。结果，焊盘55可以通过第一组凸起57与第一组线61a电连接。
可以在焊盘73和第二组线61b之间设置第二组凸起。第二组凸起的每个凸起都可以由依次层叠的多个柱状凸起75构成。可以选择的是，第二组凸起可以是高度比柱状凸起(一个或者多个)57高的单个焊接凸起75a。在每个层叠的柱状凸起75中的凸起数量可以通过上倒装芯片71和第二组线61b或者印刷电路板之间的距离确定。也可以利用常规的引线键合技术在焊盘73上制造层叠的柱状凸起75。结果，焊盘73可以通过第二组凸起75或者75a与第二组线61b电连接。
可以用环氧树脂81填充上倒装芯片71和印刷电路板51之间的空间。在一示例性实施例中，可以暴露上倒装芯片71的背表面(图4的71b)，环氧树脂81密封凸起57、75和/或75a以及下倒装芯片53。此外，粘合剂59可以置于下倒装芯片53和印刷电路板51之间。同样，粘合剂77可以置于倒装芯片53和71之间。
倒装芯片53和71、凸起57、75和75a以及环氧树脂81可以构成上多芯片封装101a。此外，下多芯片封装101b可以附着到印刷电路板的底表面上。下多芯片封装101b可以具有与上多芯片封装101a相同的结构。
根据上面讨论的示例性实施例，可以在印刷电路板上安装多个倒装芯片。这样，与常规的多芯片封装相比，根据本发明的多芯片封装的厚度可以降低。
图5是根据本发明另一示例性实施例的多芯片封装的剖面图。
参考图5，根据一示例性实施例的多芯片封装包括与参考图4描述的结构和配置相同的印刷电路板51、倒装芯片53和71以及凸起57、75和/或75a。倒装芯片53和71以及凸起57、75和/或75a可以被环氧成型化合物83完全覆盖，该环氧成型化合物83具有与图4所示的环氧树脂81不同的结构。即，上倒装芯片71的背表面71b也可以被环氧成型化合物83覆盖。粘合剂77可以置于倒装芯片53和71之间，粘合剂59可以置于下倒装芯片53和印刷电路板51之间。环氧成型化合物83、倒装芯片53和71以及凸起57、75和/或75a可以构成上多芯片封装103a。此外，与图4所示的实施例类似，下多芯片封装103b可以附着到印刷电路板的底表面上。下多芯片封装103b可以具有与上多芯片封装103a相同的结构。
图6是根据本发明另一示例性实施例的多芯片封装的剖面图。
参考图6，该多芯片封装可以包括与参考图4的示例性实施例中描述的结构和配置相同的倒装芯片53和71以及凸起57、75和/或75a。倒装芯片53和71以及凸起57、75和/或75a可以层叠在印刷电路板51上。除了图4所示的第一和第二组互连线61a和61b，印刷电路板51还可以包括第三组互连线61c。
第三芯片87可以层叠在上倒装芯片71上。第三芯片87可以具有设置在与倒装芯片53和71相对的表面上的焊盘89。焊盘89可以通过键合线91与第三组线61c电连接。粘合剂85可以置于上倒装芯片71和第三芯片87之间。可以利用环氧成型化合物93完全密封倒装芯片53和71、第三芯片87、凸起57、75和/或75a以及键合线91。环氧成型化合物93、倒装芯片53和71、第三芯片87、凸起57、75和/或75a以及键合线91可以构成上多芯片封装105a。此外，与参考图4和5描述的实施例类似，下多芯片封装105b可以附着到印刷电路板的底表面上。下多芯片封装105b可以具有与上多芯片封装105a相同的结构。
图7是说明图4至6所示倒装芯片的层叠结构的示例性实施例透视图。
参考图7，可以将下倒装芯片53层叠在印刷电路板上，可以将上倒装芯片71层叠在下倒装芯片53上。由俯视图，下倒装芯片53和上倒装芯片71可以具有矩形形状。下倒装芯片53和上倒装芯片71可以具有在下倒装芯片53和上倒装芯片之间形成伸出部分的任何设置。具体地说，上倒装芯片71的长度可以比下倒装芯片53的宽度大。在一示例性实施例中，可以将上倒装芯片71交叉层叠在下倒装芯片53上，如图7所示。结果，上倒装芯片71的两端与下倒装芯片53不重叠。上倒装芯片71的两端可以称为伸出部分。第二组凸起75可以置于伸出部分和第二组线61b之间，从而支撑伸出部分。
下面根据本发明的示例性实施例描述多芯片封装的制造方法。
图8至12是图4所示多芯片封装的制造方法的剖面图。
参考图8，可以设置具有焊盘55的第一芯片53。可以利用常规的引线键合技术在焊盘55上形成第一组凸起57。第一凸起57的每个突起都可以是单个柱状凸起。例如，可以利用金(Au)线形成第一凸起57。
参考图9，还可以设置印刷电路板。该印刷电路板可以包括基板51、第一组互连线61a和形成在基板51前表面上的第二组互连线61b。第一组线61a的端部可以设置在与一个或者多个焊盘55对应的位置上。可以将具有第一组凸起57的第一芯片53安装在基板51上。在一示例性实施例中，可以倒装第一芯片53，使得第一凸起57面对基板51。即，第一芯片53可以对应为下倒装芯片。此外，可以设置下倒装芯片53，使得第一凸起57分别与相应的第一线61a接触。可以利用例如超声芯片键合装置将第一凸起57键合到第一线61a。在一示例性实施例中，第一凸起57可以由金(Au)构成，第一和第二组线61a和61b可以用金(Au)涂覆。具体地说，当使用铜(Cu)线作为第一和第二组线61a和61b时，可以用镍涂覆该铜线，并且可以用金涂覆镍层表面。这样便于第一组凸起57和第一组线61a之间的接触和键合。
可以在印刷电路板上安装下倒装芯片53之前，在印刷电路板上设置粘合剂59。在一示例性实施例中，粘合剂59可以填充下倒装芯片53和印刷电路板之间的空间。这样，可以增强下倒装芯片53和印刷电路板之间的粘接。
参考图10，可以设置具有焊盘73的第二芯片71。第二芯片71可以具有比下倒装芯片53更大的平面面积。可以利用常规的引线键合技术在焊盘73上形成第二组凸起75。第二凸起75的每个突起都可以通过层叠多个柱状凸起形成。即，第二凸起75可以形成得比第一凸起57更高。更具体地说，第二凸起75的高度可以比第一凸起57的高度和下倒装芯片53的厚度的总和高。可以选择的是，第二凸起75的每个突起可以由单个焊接凸起75a形成，以取代层叠的柱状凸起。在一示例性实施例中，单个焊接凸起75a的高度也可以比第一凸起57的高度和下倒装芯片53的厚度的总和高。
参考图11，可以将具有第二凸起75和/或75a的第二芯片71安装在印刷电路板上，例如下倒装芯片53上。在一示例性实施例中，可以倒装第二芯片71，使得第二凸起75或者75a面对基板51。因此，第二芯片71可以对应为上倒装芯片。此外，可以设置上倒装芯片71，使得第二凸起75或者75a分别接触相应的第二线61b。可以利用例如超声芯片键合装置将第二凸起75或者75a键合到第二线61b上。
如果当从顶部看时上倒装芯片71具有与下倒装芯片53相同的矩形形状，上倒装芯片71可以安装为与下倒装芯片53交叉，或者形成伸出部分，如图7所示。在一示例性实施例中，上倒装芯片71的两端形成与下倒装芯片53不重叠的伸出部分。根据这一实施例，第二凸起75或者75a可以支撑伸出部分。换句话说，在伸出部分上不需要形成键合线。因此，可以减少键合线的接触失败。
可以在下倒装芯片53上提供粘合剂77，以在下倒装芯片53上安装上倒装芯片71。在一示例性实施例中，当安装和粘接上倒装芯片71时，粘合剂77可以填充上倒装芯片71和下倒装芯片53之间的空间。这样，可以增强倒装芯片53和71之间的粘接。
此外，粘合剂59和77可以降低下倒装芯片53弯曲的可能性或者防止其弯曲。形成在下倒装芯片53前表面上的聚酰亚胺层的应力会引起下倒装芯片53的弯曲。如果增加聚酰亚胺层的厚度，那么也增加了施加给下倒装芯片53的应力。因此，通过采用填充下倒装芯片53和印刷电路板之间的空间以及倒装芯片53和71之间的空间的粘合剂59和77，可以减小或者防止下倒装芯片53的弯曲。
参考图12，可以用环氧树脂81填充上倒装芯片71和印刷电路板之间的空间。可以通过喷嘴79提供环氧树脂81。结果，环氧树脂81可以密封下倒装芯片53和凸起57、75和/或75a。在一示例性实施例中，可以暴露上倒装芯片71的背表面(图4的71b)。环氧树脂81、倒装芯片53和71以及凸起57、75和75a可以构成上多芯片封装101a。
根据上述示例性实施例，可以层叠多个倒装芯片，以降低封装的厚度或者使封装的厚度最小。此外，层叠的芯片可以通过凸起与印刷电路板电连接。即，本发明的示例性实施例可以不需要形成键合线，该键合线会引起高的寄生电感和/或高的电阻。因此，可以实现适用于较快速器件的更高性能的封装。
图13是制造图5所示多芯片封装的示例性方法的剖面图。
参考图13，可以利用与参考图8至11描述的示例性实施例相同的技术在印刷电路板上层叠下倒装芯片53和上倒装芯片71。环氧成型化合物83可以形成在印刷电路板的前表面上，以密封倒装芯片53和71以及凸起57、75和/或75a。环氧成型化合物83可以形成为完全覆盖上倒装芯片71。环氧成型化合物83、倒装芯片53和71以及凸起57、75和/或75a可以构成上多芯片封装103a。
与图13类似的示例性实施例也可以提供适用于快速器件的更高性能封装的制造方法。
图14是制造图6所示多芯片封装的示例性方法的剖面图。
参考图14，可以与参考图8至11所描述的示例性实施例一样的方式在印刷电路板上层叠下倒装芯片53和上倒装芯片71。除了第一和第二组互连线61a和61b之外，该印刷电路板还可以包括第三组互连线61c，如图6所示。可以将第三芯片87安装在上倒装芯片71上。第三芯片87可以具有形成在与倒装芯片53和71相对的表面上的焊盘89。可以在安装第三芯片87之前，在上倒装芯片71上设置粘合剂85。这样，可以通过粘合剂85将第三芯片87固定到上倒装芯片71上。
可以利用例如常规的引线键合技术形成用于电连接焊盘89和第三线61c的键合线91。在一示例性实施例中，第三芯片87可以是与倒装芯片53和71相比具有较低工作速度的低速器件。因此，这里本发明的以上示例性实施例可以适用于制造具有不同速度的器件的多芯片封装，例如具有较慢和较快器件的多芯片封装。
可以在印刷电路板的前表面上形成环氧成型化合物93，从而密封倒装芯片53和71、第三芯片87、凸起57、75和/或75a以及键合线91。环氧成型化合物93、倒装芯片53和71、第三芯片87、凸起57、75和/或75a以及键合线91可以构成上多芯片封装105a。
如上所述，根据本发明的示例性实施例，在印刷电路板上层叠多个倒装芯片。因此，在大容量封装的实现中，可以实现工作速度的改进和/或厚度的减小。
这里描述了本发明，很显然可以以许多方式改变本发明。不应认为这些改变偏离了本发明的精神和范围。所有这些修改对于本领域技术人员来说都是显而易见的，并应包含在下列权利要求的范围内。

Claims (34)

1.一种多芯片封装，包括：
一印刷电路板，该印刷电路板包括一基板和形成在该基板前表面上的多个互连线；
层叠在该印刷电路板前表面上的多个倒装芯片，该多个倒装芯片包括一最下面的倒装芯片和至少一个上倒装芯片，该最下面的倒装芯片具有面对印刷电路板的焊盘；和
置于所述最下面的倒装芯片的焊盘和所述多个互连线的第一互连线之间的第一组凸起；和
置于所述至少一个上倒装芯片的焊盘和所述多个互连线的第二互连线之间的第二组凸起。
2.根据权利要求1的多芯片封装，其中所述第一组凸起的每个凸起都是单个的柱状凸起。
3.根据权利要求1的多芯片封装，其中所述第二组凸起的每个凸起都是单个的焊接凸起。
4.根据权利要求1的多芯片封装，其中所述第二组凸起的每个凸起都包括多个层叠的柱状凸起。
5.根据权利要求1的多芯片封装，进一步包括填充所述多个倒装芯片的最上面的倒装芯片和所述印刷电路板之间的空间的环氧树脂，其中所述环氧树脂、所述多个倒装芯片和所述第一及第二组凸起构成一上多芯片封装。
6.根据权利要求5的多芯片封装，进一步包括填充所述多个倒装芯片的最下面的倒装芯片和所述印刷电路板之间的空间以及所述多个倒装芯片的倒装芯片之间的空间的至少一粘合剂。
7.根据权利要求5的多芯片封装，进一步包括形成在所述印刷电路板背表面上的一下多芯片封装，其中该下多芯片封装具有与所述上多芯片封装相同的结构。
8.根据权利要求1的多芯片封装，进一步包括密封所述多个倒装芯片和所述第一及第二组凸起的一环氧成型化合物，其中该环氧成型化合物覆盖所述多个倒装芯片的最上面的倒装芯片，并且该环氧成型化合物、所述多个倒装芯片和所述第一及第二组凸起构成一上多芯片封装。
9.根据权利要求8的多芯片封装，进一步包括填充所述多个倒装芯片的最下面的倒装芯片和所述印刷电路板之间的空间以及所述多个倒装芯片的倒装芯片之间的空间的至少一粘合剂。
10.根据权利要求8的多芯片封装，进一步包括形成在所述印刷电路板背表面上的一下多芯片封装，其中该下多芯片封装具有与所述上多芯片封装相同的结构。
11.根据权利要求1的多芯片封装，进一步包括：
层叠在所述多个倒装芯片的最上面的倒装芯片上的第三芯片，该第三芯片具有形成在所述多个倒装芯片的相对表面上的焊盘；和
将所述第三芯片的焊盘电连接到所述多个互连线的第三组互连线的键合线。
12.根据权利要求11的多芯片封装，进一步包括密封所述多个倒装芯片、所述第三芯片、所述第一及第二组凸起和所述键合线的一环氧成型化合物，其中该环氧成型化合物覆盖所述第三芯片，并且该环氧成型化合物、所述多个倒装芯片、所述第三芯片、所述第一及第二组凸起和所述键合线构成一上多芯片封装。
13.根据权利要求11的多芯片封装，进一步包括填充所述多个倒装芯片之间的空间、所述多个倒装芯片的最下面的倒装芯片和所述印刷电路板之间的空间以及所述多个倒装芯片的最上面的倒装芯片和所述第三芯片之间的空间的至少一粘合剂。
14.根据权利要求12的多芯片封装，进一步包括形成在所述印刷电路板背表面上的一下多芯片封装，其中该下多芯片封装具有与所述上多芯片封装相同的结构。
15.一种多芯片封装，包括：
一印刷电路板，该印刷电路板包括一基板和形成在该基板一表面上的第一组互连线和第二组互连线；
层叠在该基板所述表面上的一下倒装芯片和一上倒装芯片，该下倒装芯片和上倒装芯片包括面对所述印刷电路板的焊盘；
置于所述下倒装芯片的焊盘和所述第一组互连线之间的第一组凸起；
置于所述上倒装芯片的焊盘和所述第二组互连线之间的第二组凸起；
填充所述上倒装芯片和所述印刷电路板之间的空间的一环氧树脂。
16.根据权利要求15的多芯片封装，其中所述第一组凸起的每个凸起都是单个的柱状凸起。
17.根据权利要求15的多芯片封装，其中所述第二组凸起的每个凸起都是单个的焊接凸起。
18.根据权利要求15的多芯片封装，其中所述第二组凸起的每个凸起都具有多个层叠的柱状凸起。
19.根据权利要求15的多芯片封装，进一步包括填充所述下倒装芯片和所述印刷电路板之间的空间以及所述上倒装芯片和所述下倒装芯片之间的空间的至少一粘合剂。
20.根据权利要求15的多芯片封装，其中所述上倒装芯片安置为与所述下倒装芯片交叉，以便形成与所述下倒装芯片不重叠的伸出部分，且所述第二组凸起置于该伸出部分和所述第二组互连线之间。
21.根据权利要求15的多芯片封装，其中所述上倒装芯片具有比所述下倒装芯片更大的平面面积。
22.一种多芯片封装，包括：
一印刷电路板，该印刷电路板包括一基板和形成在该基板一表面上的第一组互连线和第二组互连线；
层叠在该基板所述表面上的一下倒装芯片和一上倒装芯片，该下和上倒装芯片包括面对所述印刷电路板的焊盘；
置于所述下倒装芯片的焊盘和所述第一组互连线之间的第一组凸起；
置于所述上倒装芯片的焊盘和所述第二组互连线之间的第二组凸起；
密封所述下和上倒装芯片以及所述第一和第二组凸起的一环氧成型化合物，该环氧成型化合物覆盖所述上倒装芯片。
23.根据权利要求22的多芯片封装，其中所述第一组凸起的每个凸起都是单个的柱状凸起。
24.根据权利要求22的多芯片封装，其中所述第二组凸起的每个凸起都是单个的焊接凸起。
25.根据权利要求22的多芯片封装，其中所述第二组凸起的每个凸起都具有多个层叠的柱状凸起。
26.根据权利要求22的多芯片封装，进一步包括填充所述下倒装芯片和所述印刷电路板之间的空间以及所述上倒装芯片和所述下倒装芯片之间的空间的至少一粘合剂。
27.根据权利要求22的多芯片封装，进一步包括：
层叠在所述上倒装芯片上的第三芯片，该第三芯片具有形成在所述下和上倒装芯片相对表面上的焊盘；和
将所述第三芯片的焊盘电连接到所述印刷电路板上的第三组互连线的键合线，其中所述环氧成型化合物覆盖所述第三芯片和所述键合线。
28.根据权利要求27的多芯片封装，进一步包括置于所述上倒装芯片和所述第三芯片之间的一粘合剂。
29.根据权利要求22的多芯片封装，其中所述上倒装芯片交叉层叠在所述下倒装芯片上，以便形成与所述下倒装芯片不重叠的伸出部分，所述第二组凸起置于该伸出部分和所述第二组互连线之间。
30.根据权利要求22的多芯片封装，其中所述上倒装芯片具有比所述下倒装芯片更大的平面面积。
31.一种方法，包括：
提供一印刷电路板，该印刷电路板包括一基板和该基板一表面上的多个互连；
在该印刷电路板的所述表面上层叠多个倒装芯片，其中最下面的倒装芯片具有面对所述印刷电路的焊盘；和
在所述最下面的倒装芯片的焊盘和所述多个互连线的第一互连线之间置入第一组凸起；和
在所述至少一个上倒装芯片的焊盘和所述多个互连线的所述第二互连线之间置入第二组凸起。
32.一种方法，包括：
提供一印刷电路板，该印刷电路板包括一基板和该基板一表面上形成的第一组互连线和第二组互连线；
在该基板的所述表面上层叠一下倒装芯片和一上倒装芯片，该下倒装芯片和上倒装芯片包括面对所述印刷电路板的焊盘；
在所述下倒装芯片的焊盘和所述第一组互连线之间置入第一组凸起；
在所述上倒装芯片的焊盘和所述第二组互连线之间置入第二组凸起；
用一环氧树脂填充所述上倒装芯片和所述印刷电路板之间的空间。
33.一种方法，包括：
提供一印刷电路板，该印刷电路板包括一基板和该基板一表面上的第一组互连线和第二组互连线；
在该基板的所述表面上层叠一下倒装芯片和一上倒装芯片，该下和上倒装芯片包括面对所述印刷电路板的焊盘；
在所述下倒装芯片的焊盘和所述第一组互连线之间置入第一组凸起；
在所述上倒装芯片的焊盘和所述第二组互连线之间置入第二组凸起；
用一环氧成型化合物密封所述下和上倒装芯片以及所述第一和第二组凸起，使得该环氧成型化合物覆盖所述上倒装芯片。
34.一种通过权利要求31-33之一的方法制造的多芯片封装。
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CN101378051B (zh) * 2007-08-27 2012-10-10 富士通半导体股份有限公司 半导体器件及其制造方法
CN102593110A (zh) * 2012-01-05 2012-07-18 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法
CN102543939A (zh) * 2012-01-05 2012-07-04 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及其制造方法
CN102593110B (zh) * 2012-01-05 2015-07-15 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法
CN102543939B (zh) * 2012-01-05 2015-09-16 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及其制造方法
CN104704631B (zh) * 2012-10-08 2020-09-08 高通股份有限公司 堆叠式多芯片集成电路封装
CN104704631A (zh) * 2012-10-08 2015-06-10 高通股份有限公司 堆叠式多芯片集成电路封装
US9406649B2 (en) 2012-10-08 2016-08-02 Qualcomm Incorporated Stacked multi-chip integrated circuit package
CN103824818A (zh) * 2014-03-13 2014-05-28 扬州大学 射频微机电器件板级互连封装结构及其封装方法
CN103824818B (zh) * 2014-03-13 2016-08-31 扬州大学 射频微机电器件板级互连封装结构及其封装方法
CN108475671A (zh) * 2016-02-05 2018-08-31 英特尔公司 用于堆叠引线接合转换的倒装芯片管芯的系统和方法
CN109087895A (zh) * 2017-06-13 2018-12-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN109087895B (zh) * 2017-06-13 2020-09-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN113179131A (zh) * 2021-04-22 2021-07-27 青岛海信宽带多媒体技术有限公司 一种光模块

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