TWI426591B - 多晶片封裝系統 - Google Patents

多晶片封裝系統 Download PDF

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Publication number
TWI426591B
TWI426591B TW096101384A TW96101384A TWI426591B TW I426591 B TWI426591 B TW I426591B TW 096101384 A TW096101384 A TW 096101384A TW 96101384 A TW96101384 A TW 96101384A TW I426591 B TWI426591 B TW I426591B
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Taiwan
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integrated circuit
circuit die
substrate
interconnect
opening
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TW096101384A
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TW200742029A (en
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Sungwon Choi
Tae Sung Jeong
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Stats Chippac Ltd
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Publication of TW200742029A publication Critical patent/TW200742029A/zh
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Publication of TWI426591B publication Critical patent/TWI426591B/zh

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Description

多晶片封裝系統
本發明大體上係關於積體電路封裝件，且詳言之，係關於堆疊之積體電路封裝系統。
現代消費性電子，譬如智慧型電話、個人數位助理、和基於位置之服務裝置，以及企業電子，譬如伺服器和儲存陣列，係包裝更多的積體電路於非常縮小之實體空間以期減少成本。已發展出許多的技術來滿足這些需求。某些研究和發展策略集中在新的封裝技術，而其他的策略集中在改進現有的和成熟的封裝技術。於現有的封裝技術中研究和發展可進行於許多不同之方向。
一種已獲得證實降低成本之方法為使用具有現有製造方法和規格之封裝技術。違反常理地，再使用現有的製造方法通常無法獲得減少封裝尺寸。現有的封裝技術艱困地進行著有效降低成本以滿足一直存在著之要求現今積體電路和封裝件之整合(integration)。
回應於要求改進封裝，已構想出許多創新的封裝設計並已帶入市場。多重晶片模組已在減少板空間方面達成重要的任務。許多的封裝件施行堆疊多重積體電路、封裝件層堆疊、或封裝件疊加(package－on－package；POP)。已知良好裸晶(known－good－die；KGD)和組合製程產量(assembly process yield)並非問題，因為在組合之前能測試各封裝件，允許KGD用於組裝堆疊。但是堆疊積體裝置、封裝件疊加、或他們的組合有系統層級上之困難。封裝件疊加結構用於減少封裝件之組合產量損失並方便測試組合產品。然而，其高度已增加因其係由二個一般的封裝件所組成。
因此，仍存在著需要一種提供低製造成本、改進產量、減少積體電路封裝件尺寸和彈性的堆疊和整合配置之可堆疊之積體電路封裝系統。有鑑於仍持續增加需求以節省成本和改進效率，愈來愈嚴格要求對於這些問題提出解決之方式。
已長時間尋求對這些問題之解決方式，但是先前的研發尚未揭示或建議任何的解決方法，因此，對於這些問題之解決方法長期以來難倒了熟悉此項技術者。
本發明提供一種多晶片封裝系統，該系統包括形成具有第一側、第二側、和第一開口之第一基板，通過該第一開口連接第一積體電路晶粒至該第一基板，連接第二積體電路晶粒於該第一基板上，以及包覆該第一積體電路晶粒和第二積體電路晶粒於該第一基板上。
除了或取代上述該等提及的或顯然的態樣外，本發明之某些實施例尚具有其他的態樣。由讀取下列之詳細說明並參照所附的圖式，對於熟悉此項技術者而言，該等態樣將變得顯而易知。
於下列說明中，提出了許多特定的詳細說明以提供對本發明之完全瞭解。然而，很顯然的對於熟悉本技藝者而言，可不必作如此詳細說明即能實施本發明。為了避免模糊了本發明，並未詳細揭露一些已知的系統配置和製程步驟。同樣情況，顯示裝置之實施例之圖式為半圖式且未按尺寸繪製，而尤其是，一些之尺寸為了清楚表示之目的，於圖形中被很誇大地顯示。相同之元件符號用於所有之圖式中相關於相同的元件。
此處所用之“水平面(horizontal)”一詞定義為平行於習知積體電路表面之平面，而無關於其方向。“垂直的(vertical)”一詞參考為垂直於剛才所定義之水平面之方向。相關於該水平面而定義譬如“在上方(above)”、“在下方(below)”、“底部(bottom)”、“頂部(top)”、“側(side)”(如側壁)、“較高(higher)”、“較低(lower)”、“較上面(upper)”、“在．．．之上(over)”、和“在．．．下面(under)”等詞彙。詞彙“在上面(on)”表示各元件間直接接觸。
此處所用詞彙“處理(processing)”包括沉積材料、圖案化(patterning)、暴露、顯影(development)、蝕刻、清洗、模製(molding)、和/或去除材料或如要求形成所描述之結構。
茲參照第1圖，其中顯示於本發明之實施例中第一多晶片封裝系統100之剖面圖。第一積體電路晶粒102包括第一非作用側(non－active side)104和具有電路製造於其上之第一作用側(active side)106。第一積體電路晶粒102安裝在基板110之第一側108(譬如底側)上，其中第一作用側106用黏著劑112黏著於基板110上。第一作用側106之中央部分具有焊接墊(bonding pad)140。基板110具有開口114用於第一側108上所黏著之第一積體電路102與基板110之第二側116(譬如頂側)間之電氣連接。譬如結合導線之第一互連件(interconnect)118用晶片貼板(board－on－chip；BOC)配置電氣連接焊接墊140和第二側116。
第二積體電路晶粒120包括第二非作用側122和具有電路製造於其上之第二作用側124。第二積體電路晶粒120安裝於第二側116，其中第二非作用側122用黏著劑112黏著於基板110上。譬如結合導線之第二互連件電氣連接第二積體電路晶粒120與基板110之第二側116。第二積體電路晶粒120之位置是在開口114之一側而使得開口114不被第二積體電路晶粒120所覆蓋。而且，並不阻礙第一互連件118至第二側116之連接，而第一互連件118與第二互連件126之不留心交錯若即使沒有排除的話，亦減至最小。
為了例示目的，第二積體電路晶粒120顯示為焊接線裝置，雖然了解到可使用具有不同電氣互連件結構之其他類型裝置，譬如覆晶或細間距球格陣列(fine pitch ball grid array；FBGA)。亦為了例示目的，第二非作用側122亦顯示黏著至基板110，雖然了解到第二作用側124可用適當的互連件結構和裝置黏著至基板110。
相似情況，第三積體電路晶粒128包括第三非作用側130和具有電路製造於其上之第三作用側132。第三積體電路晶粒128安裝在第二側116，其中第三非作用側130用黏著劑112黏著至基板110。譬如焊接線之第三互連件134電氣連接第三積體電路晶粒128與基板110之第二側116。第三積體電路晶粒128之位置係在開口114之相對於第二積體電路晶粒120之側，而使得開口114不被第三積體電路晶粒128所覆蓋。而且，不阻礙第一互連件118至第二側116之連接，而第一互連件118與第三互連件134之不留心交錯若沒有排除的話，亦減至最小。
為了例示目的，第三積體電路晶粒128顯示為焊接線裝置，雖然了解到可使用具有不同電氣互連件結構之其他類型裝置，譬如覆晶或細間距球格陣列(FBGA)。亦為了例示目的，第三非作用側130亦顯示黏著至基板110，雖然了解到第三作用側132可用適當的互連件結構和裝置黏著至基板110。
如上所述，基板110具有第一側108和第二側116。該二側具有接觸位置(未顯示)，以用來連接互連件結構。第一側108和第二側116可具有導電跡線(conductive trace)(未顯示)，以將電氣訊號傳送至該接觸位置，並從該接觸位置接收電氣訊號。電氣通孔(electrical via)(未顯示)可於通當位置將該導電跡線從第一側108連接至第二側116。基板110可具有絕緣層(未顯示)，以電氣隔離該導電跡線與第一側108和第二側116。基板110之第一側108具有黏著於其上之外部互連件136。基板110可以是任何數目之層並可以由許多種材料製成，譬如有機物或無機物。
模製化合物(mold compound)138，譬如環氧樹脂模製化合物(epoxy mold compound,EMC)，包覆第一積體電路晶粒102、第二積體電路晶粒120、第三積體電路晶粒128、第一互連件118、第二互連件126、和第三互連件134於基板110上。沿著第一側108之模製化合物138形成覆蓋第一積體電路晶粒102之中心閘模(center gate mold)，而使得該中心閘模之尺寸不妨礙外部互連件136之連接至次一個系統級(未顯示)(譬如印刷電路板)。開口114實質上由模製化合物138所充填。
已發現到以並排配置多個積體電路晶粒於基板之一側(例如，頂側)與一或多個積體電路晶粒於基板之另一側(例如，底側)之方式可最小化該多晶片封裝件之高度、寬度、和長度。底側積體電路晶粒和對應的包覆不延伸超過外部互連件而使得存在空間可用於裝填更多之積體電路容量於封裝件中，而不會增加封裝件高度。用此種使用BOC設計之底側積體電路晶粒，底側積體電路晶粒位於頂側積體電路晶粒之間，該封裝件之寬度和長度進一步減小。
現參照第2圖，其中顯示了本發明之另一實施例中第二多晶片封裝系統200之剖面圖。第一積體電路晶粒202包括第一非作用側204和具有電路製造於其上之第一作用側206。第一積體電路晶粒202安裝在基板210之第一側208(譬如頂側)上，其中第一作用側206用黏著劑212黏著於基板210上。第一作用側206之中央部分具有第一焊接墊240。基板210包括第一開口214和第二開口216。第一開口214用於第一側208上所黏著之第一積體電路202與基板110之第二側218(譬如頂側)間之電氣連接。譬如結合導線之第一互連件220用晶片貼板(BOC)配置電氣連接焊接墊240和第二側218。
相似情況，第二積體電路晶粒222包括第二非作用側224和具有電路製造於其上之第二作用側226。第二積體電路晶粒222安裝鄰接於基板210之第一側208(譬如上側)上之第一積體電路晶粒202，其中第二作用側226用黏著劑212黏著於基板210上。第二作用側226之中央部份具有第二焊接墊242。第二開口216用來電氣連接黏著於第一側208之第二積體電路晶粒222與基板210之第二側218(譬如底側)之間。譬如焊接線之第二互連件228用晶片貼板(BOC)配置電氣連接第二焊接墊242和第二側218。
如上所述，基板210具有第一側208和第二側218。該二側具有接觸位置(未顯示)用來連接互連件結構。第一側208和第二側218可具有導電跡線(未顯示)，用以將電氣訊號傳送至該接觸位置，並從該接觸位置接收電氣訊號。電氣通孔(未顯示)可於適當位置將該導電跡線從第一側208連接至第二側218。基板210可具有絕緣層(未顯示)，以電氣隔離導電跡線與第一側208和第二側218。基板210之第一側208具有黏著於其上之外部互連件230。基板210可以是任何數目之層並可以由許多種材料製成，譬如有機物或無機物。
模製化合物232，譬如環氧樹脂模製化合物(EMC)，包覆第一積體電路晶粒202、第二積體電路晶粒222、第一互連件220、第二互連件228於基板210上。模製化合物232沿著第二側218形成覆蓋第一互連件220和第二互連件228之中心閘模，而使得中心閘模之尺寸不妨礙外部互連件230之連接至次一個系統級(未顯示)(譬如印刷電路板)。第一開口214和第二開口216實質上由模製化合物232所充填。
已發現到將該積體電路晶粒以並排(side by side)配置之方式設置於基板之頂側並將該積體電路晶粒以BOC配置之方式連接至該基板之底側，可最小化多晶片封裝件之尺寸。底側電氣連接和對應的包覆不延伸超過外部互連件而減少封裝件高度。
現參照第3圖，其中顯示具有第一多晶片封裝系統100之第一積體電路封裝件疊加系統300之剖面圖。第一多晶片封裝系統100安裝於底封裝件302形成封裝件疊加結構。底封裝件302包括具有頂側306和底側308之底基板304。該二側具有接觸位置(未顯示)用來連接互連件結構。第一多晶片封裝系統100之外部互連件136連接該接觸位置於底基板304之頂側306。
頂側306和底側308可具有導電跡線(未顯示)，用以將電氣訊號傳送至該接觸位置，並從該接觸位置接收電氣訊號。電氣通孔(未顯示)可於適當位置將該導電跡線從頂側306連接至底側308。底基板304可具有絕緣層(未顯示)，以電氣隔離該導電跡線與頂側306和底側308。底基板304之底側308具有黏著於其上之底外部互連件310。底基板304可以是任何數目之層並可以由許多種材料製成，譬如有機物或無機物。
積體電路晶粒312包括非作用側314和具有電路製造於其上之作用側316。積體電路晶粒312安裝在底側308，其中非作用側314用黏著劑320黏著於底基板304。譬如焊接線之互連件322電氣連接積體電路晶粒312和底側308。
模製化合物324，譬如環氧樹脂模製化合物(EMC)，包覆積體電路晶粒312和互連件322於底基板304之底側308。模製化合物324形成中心閘模而沒有妨礙底外部互連件310至譬如印刷電路板之次一系統級(未顯示)之連接。第一積體電路晶粒102之中心閘模不影響第一積體電路封裝件疊加系統300之高度超出第一多晶片封裝系統100之外部互連件136之z軸要求。
茲參照第4圖，其中顯示具有第一多晶片封裝系統100之第二積體電路封裝件疊加系統400之剖面圖。第一多晶片封裝系統100安裝於底封裝件402形成封裝件疊加結構。底封裝件402包括具有頂側406和底側408之底基板404。該二側具有接觸位置(未顯示)用來連接互連件結構。第一多晶片封裝系統100之外部互連件136連接該接觸位置於底基板404之頂側406。
頂側406和底側408可具有導電跡線(未顯示)，用以將電氣訊號傳送至該接觸位置，並從該接觸位置接收電氣訊號。電氣通孔(未顯示)可於適當位置將導電跡線從頂側406連接至底側408。底基板404可具有絕緣層(未顯示)，以電氣隔離該導電跡線與頂側406和底側408。底基板404之底側408具有黏著於其上之底外部互連件410。底基板404可以是任何數目之層並可以由許多種材料製成，譬如有機物或無機物。
積體電路晶粒412(譬如覆晶)包括非作用側414和具有電路和互連件418(譬如焊塊(solder bump))製造於其上之作用側416。積體電路晶粒412安裝在底側408，其中互連件418黏著於底側308。
模製化合物420，譬如環氧樹脂模製化合物(EMC)，包覆互連件418於底側408。模製化合物420亦以暴露之非作用側414環繞積體電路晶粒412而不妨礙底外部互連件410至譬如印刷電路板之次一系統級(未顯示)之連接。模製化合物420和第一積體電路晶粒102不影響第二積體電路封裝件疊加系統400之高度超出第一多晶片封裝系統100之外部互連件136之z軸要求。
茲參照第5圖，其中顯示具有第二多晶片封裝系統200之第三積體電路封裝件疊加系統500之剖面圖。第二多晶片封裝系統200安裝於底封裝件502形成封裝件疊加結構。底封裝件502包括具有頂側506、底側508和開口510之底基板504。該二側具有接觸位置(未顯示)用來連接互連件結構。第二多晶片封裝系統200之外部互連件136連接該接觸位置於底基板504之頂側506。
頂側506和底側508可具有導電跡線(未顯示)，用以將電氣訊號傳送至該接觸位置，並從該接觸位置接收電氣訊號。電氣通孔(未顯示)於適當位置將該導電跡線從頂側506連接至底側508。底基板504可具有絕緣層(未顯示)，以電氣隔離該導電跡線與頂側506和底側508。底側508具有黏著於其上之底外部互連件512。底基板504可以是任何數目之層並可以由許多種材料製成，譬如有機物或無機物。
積體電路晶粒514包括非作用側516和具有電路製造於其上之作用側518。積體電路晶粒514安裝在底基板504之底側508，其中作用側518用黏著劑520黏著於底側508。作用側518之中央部分具有第三焊接墊530。開口510用於於底側508上積體電路晶粒514與頂側506之間之電氣連接。譬如結合導線之互連件522用晶片貼板(BOC)配置電氣連接第三焊接墊530和上側506。
模製化合物524，譬如環氧樹脂模製化合物(EMC)，包覆互連件522於頂側506並填滿開口510。模製化合物524形成相襯於第二多晶片封裝系統200之中心閘模之間之凹部526之結構，而不妨礙於頂側506上外部互連件136之連接。積體電路晶粒514不影響底封裝件502之高度超出底外部互連件512之z軸要求。
茲參照第6圖，其中顯示於本發明之實施例中用於製造多晶片封裝系統100之多晶片封裝系統600之流程圖。系統600包括於方塊602形成具有第一側、第二側、和第一開口之第一基板；於方塊604連接第一積體電路晶粒通過該第一開口至該第一基板；於方塊606連接第二積體電路晶粒於該第一基板上；以及於方塊608包覆該第一積體晶粒和該第二積體電路晶粒於該第一基板上。
發現到本發明因此有許多的態樣。
已發現到以並排配置多個積體電路晶粒於基板之一側(例如，頂側)與一或多個積體電路晶粒於基板之另一側(例如，底側)之方式而可最小化該多晶片封裝件之高度、寬度、和長度。底側積體電路晶粒和對應的包覆不延伸超過外部互連件而使得存在空間可用於裝填更多之積體電路容量於封裝件中，而不會增加封裝件高度。用此種使用BOC設計之底側積體電路晶粒，底側積體電路晶粒位於頂側積體電路晶粒之間，該封裝件之寬度和長度進一步減小。
已發現到以並排配置多個積體電路晶粒於基板之一側(例如，頂側)與積體電路晶粒之間的電氣連接至基板於基板之另一側(例如，底側)，而可最小化該多晶片封裝件之高度、寬度、和長度。底側電氣連接和對應的包覆不延伸超過外部互連件而減少封裝件高度。
一個態樣為本發明為利用一個封裝件之底側空間之晶片貼板(board－on－chip；BOC)封裝件設計。於封裝件之頂側，使用分離之單一晶粒代替堆疊晶粒以避免增加頂厚度。此修改的封裝結構能夠減少整個封裝厚度以及其亦能藉由面對任何的封裝結構譬如BOC、FBGA和覆晶而利用更多的空間。
本發明之另一態樣為修改BOC設計封裝件藉由面對具有頂側和底側結構朝向於封裝件疊加配置中之一個單底封裝件之頂封裝件以改進實際使用。其結構亦能與用於底側封裝件之覆晶封裝件使用。
本發明之又另一態樣為藉由應用二個BOC設計於修改的BOC設計封裝件改進實際使用封裝件疊加配置。
本發明之又另一態樣為其有價值地支援和服務減少成本和增加性能之歷史趨勢。本發明之這些和其他的有價值態樣結果進一步促進技術狀態至至少次一水準。
因此，發現到本發明之多晶片封裝系統方法提供重要的和迄今未知和未曾使用之解決方法、能力、和功能態樣，來增加晶片密度同時最小化系統中所需空間。所得到的製程和配置係簡單易作的，能藉由採用已知的技術而施行低成本、不複雜、高度多樣性及效果，而因此容易適合有效率和節省地製造堆疊積體電路封裝裝置。
雖然本發明已結合特定之最佳實施模式而作了說明，但應瞭解到對於熟習此技藝者而言，在鑑於上述之說明後，可瞭解該實施例可作許多之替換、修飾和改變。因此，本發明將包含所有落於所包含之申請專利範圍之精神和範圍內之此等的替換、修飾和改變。此說明書中所提出和所附圖式中所顯示之所有內容係將作例示說明用而並非欲用來限制本發明。
100．．．第一多晶片封裝系統
102．．．第一積體電路晶粒
104、204．．．第一非作用側
106、206．．．第一作用側
108、208．．．第一側
110、210．．．基板
112、212、320、520．．．黏著劑
114、510．．．開口
116、218．．．第二側
118、220．．．第一互連件
120．．．第二積體電路晶粒
122、224．．．第二非作用側
124、226．．．第二作用側
126、228．．．第二互連件
128．．．第三積體電路晶粒
130．．．第三非作用側
132．．．第三作用側
134．．．第三互連件
136、230．．．外部互連件
138、232、324、420、524．．．模製化合物
140．．．焊接墊
200．．．第二多晶片封裝系統
202．．．第一積體電路晶粒
214．．．第一開口
216．．．第二開口
222．．．第二積體電路晶粒
240．．．第一焊接墊
242．．．第二焊接墊
300．．．第一積體電路封裝件疊加系統
302、402、502．．．底封裝件
304、404、504．．．底基板
306、406、506．．．頂側
308、408、508．．．底側
310、410、512．．．底外部互連件
312、412、514．．．積體電路晶粒
314、414、516．．．非作用側
316、416、518．．．作用側
322、418、522．．．互連件
400．．．第二積體電路封裝件疊加系統
500．．．第三積體電路封裝件疊加系統
530．．．第三焊接墊
526．．．凹部
600．．．多晶片封裝系統
602、604、606、608．．．方塊
第1圖為於本發明之實施例中第一多晶片封裝系統之剖面圖；第2圖為於本發明之另一實施例中第二多晶片封裝系統之剖面圖；第3圖為具有第一多晶片封裝系統之第一積體電路封裝件疊加系統之剖面圖；第4圖為具有第一多晶片封裝系統之第二積體電路封裝件疊加系統之剖面圖；第5圖為具有第二多晶片封裝系統之第三積體電路封裝件疊加系統之剖面圖；以及第6圖為於本發明之實施例中用來製造多晶片封裝系統之多晶片封裝系統之流程圖。
600．．．多晶片封裝系統
602、604、606、608．．．方塊

Claims (10)

  1. 一種多晶片封裝系統(600)，包括：形成具有第一側(108)(208)、第二側(116)(218)、和第一開口(114)(214)之第一基板(110)(210)，其中，該第一基板(110)(210)係於其兩側皆提供電性連接；將第一積體電路晶粒(102)(202)通過該第一開口(114)(214)連接至該第一基板(110)(210)；連接第二積體電路晶粒(120)(222)於該第一基板(110)(210)上；以及包覆該第一積體電路晶粒(102)(202)和第二積體電路晶粒(120)(222)於該第一基板(110)(210)上。
  2. 如申請專利範圍第1項之系統(600)，其中：將該第一積體電路晶粒(102)通過該第一開口(114)連接至該第一基板(110)包括：黏著該第一積體電路晶粒(102)之作用側(106)於該第一側(108)上，以及連接該作用側(106)與該第二側(116)間之互連件(118)；連接該第二積體電路晶粒(120)復包括：安裝該第二積體電路晶粒(120)於該第二側(116)上於該第一開口(114)之一側；以及該系統復包括：安裝第三積體電路晶粒(128)於該第二側(116)上於該第一開口(114)之相對側；以及 包覆該互連件(118)。
  3. 如申請專利範圍第1項之系統(600)，復包括：使該第一基板(210)形成有第二開口(216)；黏著該第一積體電路晶粒(202)之第一作用側(206)於該第一側(208)上；連接該第一作用側(206)與該第二側(218)間之第一互連件(220)；黏著該第二積體電路晶粒(222)之第二作用側(226)於該第一側(208)上；通過該第二開口(216)連接該第二作用側(226)與該第二側(218)間之第二互連件(228)；以及包覆該第一互連件(220)與第二互連件(228)。
  4. 如申請專利範圍第1項之系統(600)，其中：連接該第一積體電路晶粒(102)包括：連接該第一積體電路晶粒(102)於該第一側(108)上，以及黏著外部互連件(136)於該第一側(108)上；以及該系統復包括：形成具有第二基板(304)之底積體電路封裝件(302)；黏著積體電路晶粒(312)於該第二基板(304)之底側(308)上；以及黏著該外部互連件(136)於該第二基板(304)之頂側(306)上。
  5. 如申請專利範圍第1項之系統(600)，其中：連接該第一積體電路晶粒(202)包括：連接該第一積體電路晶粒(202)於該第一側(208)上；以及該系統復包括：黏著外部互連件(230)於該第二側(218)上；形成具有含開口(510)之第二基板(504)之底積體電路封裝件(502)；將該第二基板(504)之底側(508)上之積體電路晶粒(514)通過該開口(510)連接至該第二基板(504)之頂側(506)；以及黏著該外部互連件(136)於該頂側(506)上。
  6. 一種多晶片封裝系統(100)，包括：具有第一側(108)(208)、第二側(116)(218)、和第一開口(114)(214)之第一基板(110)(210)；通過該第一開口(114)(214)連接至該第一基板(110)(210)之第一積體電路晶粒(102)(202)；於該第一基板(110)(210)上之第二積體電路晶粒(120)(222)；以及用以覆蓋該第一積體電路晶粒(102)(202)和該第一基板(110)(210)上之該第二積體電路晶粒(120)(222)之模製化合物(138)(232)。
  7. 如申請專利範圍第6項之系統(100)，其中：通過該第一開口(114)至該第一基板(110)之該第一 積體電路晶粒(102)包括：該第一側(108)上之該第一積體電路晶粒(102)之作用側(106)，以及該作用側(106)與該第二側(116)間之互連件(118)；該第二積體電路晶粒(120)復包括：於該第二側(116)上於該第一開口(114)之一側之該第二積體電路晶粒(120)；以及該系統復包括：於該第二側(116)上於該第一開口(114)之相對側之第三積體電路晶粒(128)；以及用以覆蓋該互連件(134)之模製化合物(138)。
  8. 如申請專利範圍第6項之系統(200)，復包括：具有第二開口(216)之該第一基板(210)；於該第一側(208)上之該第一積體電路晶粒(202)之第一作用側(206)；該第一作用側(206)與該第二側(218)間之第一互連件(220)；於該第一側(208)上之該第二積體電路晶粒(222)之第二作用側(226)；該第二作用側(226)與該第二側(218)間通過該第二開口(216)之第二互連件(228)；以及用以覆蓋該第一互連件(220)與該第二互連件(228)之模製化合物(232)。
  9. 如申請專利範圍第6項之系統(300)，其中： 該第一積體電路晶粒(102)包括：於該第一側(108)上之該第一積體電路晶粒(102)，以及於該第一側(108)上之外部互連件(136)；以及該系統復包括：具有第二基板(304)之底積體電路封裝件(302)；於該第二基板(304)之底側(308)上之積體電路晶粒(312)；以及於該第二基板(304)之頂側(306)上之外部互連件(136)。
  10. 如申請專利範圍第6項之系統(500)，其中：於該第一積體電路晶粒(514)包括：該第一側(108)上之該第一積體電路晶粒(514)，以及該系統復包括：於該第二側(116)上之外部互連件(136)；具有含開口(510)之第二基板(504)之底積體電路封裝件(502)；通過開口(510)連接至該第二基板(504)之底側(508)之該第二基板(504)之頂側(506)上之積體電路晶粒(514)；以及於該頂側(506)上之該外部互連件(136)。
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