JP5964438B2 - パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の2重の組を使用するスタブ最小化 - Google Patents
パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の2重の組を使用するスタブ最小化 Download PDFInfo
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- JP5964438B2 JP5964438B2 JP2014534599A JP2014534599A JP5964438B2 JP 5964438 B2 JP5964438 B2 JP 5964438B2 JP 2014534599 A JP2014534599 A JP 2014534599A JP 2014534599 A JP2014534599 A JP 2014534599A JP 5964438 B2 JP5964438 B2 JP 5964438B2
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Description
本出願は、2011年10月3日に出願された米国仮特許出願第61/542,553号及び2012年2月17日に出願された米国仮特許出願第61/600,483号の出願日の利益を主張する2012年4月4日に出願された米国特許出願第13/439,228号の継続出願であり、それらの特許文献の開示は参照することにより本明細書の一部をなすものとする。
なお、出願当初の特許請求の範囲は以下の通りである。
(請求項1)
超小型電子アセンブリであって、
互いに反対側の第1の表面及び第2の表面と、前記第1の表面及び前記第2の表面においてそれぞれ露出する第1のパネルコンタクト及び第2のパネルコンタクトとを有する回路パネルと、
それぞれが前記それぞれのパネルコンタクトに取り付けられる端子を有する第1の超小型電子パッケージ及び第2の超小型電子パッケージと、
を備え、各超小型電子パッケージは、
面と、該面において露出する複数の素子コンタクトとを有する超小型電子素子であって、メモリ記憶アレイ機能を有する、超小型電子素子と、
互いに反対側の第1の表面及び第2の表面を有する基板であって、前記超小型電子素子の前記素子コンタクトに面する前記第1の表面において露出し、該超小型電子素子の該素子コンタクトに接合される1組の基板コンタクトを有する、基板と、
前記超小型電子パッケージを、該パッケージの外部にある少なくとも1つの構成要素に接続するように構成される、前記第2の表面において露出する複数の端子であって、該端子は、前記基板コンタクトに電気的に接続され、複数の第1の端子を含み、該第1の端子は、理論的軸の第1の側に配置される第1の端子の第1の組と、前記第1の側と反対側の前記軸の第2の側に配置される第1の端子の第2の組とを含み、前記第1の組及び前記第2の組のそれぞれは、前記超小型電子素子のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から1つのアドレス指定可能メモリ位置を決定するのに前記超小型電子パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成される、複数の端子と、
を備え、
前記第1の組内の前記第1の端子の信号割り当ては、前記第2の組内の前記第1の端子の信号割り当ての鏡像である、超小型電子アセンブリ。
(請求項2)
各超小型電子パッケージの前記超小型電子素子は、メモリ記憶アレイ機能を提供する能動素子の数をいかなる他の機能よりも多く具体化する、請求項1に記載の超小型電子アセンブリ。
(請求項3)
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記アドレス指定可能メモリ位置を決定するのに前記それぞれの超小型電子パッケージ内の前記回路によって使用可能な前記アドレス情報の全てを運ぶように構成される、請求項1に記載の超小型電子アセンブリ。
(請求項4)
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージの前記超小型電子素子の動作モードを制御する情報を運ぶように構成される、請求項1に記載の超小型電子アセンブリ。
(請求項5)
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージに転送されるコマンド信号の全てを運ぶように構成され、前記コマンド信号は、ライトイネーブル信号、行アドレスストローブ信号、及び列アドレスストローブ信号である、請求項4に記載の超小型電子アセンブリ。
(請求項6)
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージに転送されるクロック信号を運ぶように構成され、前記クロック信号は、前記アドレス情報を運ぶ信号をサンプリングするのに用いられるクロックである、請求項1に記載の超小型電子アセンブリ。
(請求項7)
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージに転送されるバンクアドレス信号の全てを運ぶように構成される、請求項1に記載の超小型電子アセンブリ。
(請求項8)
各超小型電子パッケージの前記第1の組及び前記第2の組の前記第1の端子は、各超小型電子パッケージのそれぞれの第1のグリッド及び第2のグリッド内の場所に配置され、前記第1のパッケージの前記第2のグリッド内の前記第1の端子は、前記回路パネルを通して、前記第2のパッケージの前記第1のグリッド内の前記第1の端子に接続され、前記第1のパッケージの前記第2のグリッドの前記第1の端子は、前記第1の回路パネル表面及び前記第2の回路パネル表面に平行な直交するx方向及びy方向において、該第2のグリッドの該第1の端子が接続される前記第2のパッケージ上の前記第1のグリッドの対応する前記第1の端子の1つのボールピッチ内に位置合わせされる、請求項1に記載の超小型電子アセンブリ。
(請求項9)
前記グリッドは、該グリッドの前記端子が互いに一致するように、直交する前記x方向及び前記y方向において互いに位置合わせされる、請求項8に記載の超小型電子アセンブリ。
(請求項10)
各グリッドの各場所は前記端子のうちの1つによって占有される、請求項8に記載の超小型電子アセンブリ。
(請求項11)
各グリッドのうちの少なくとも1つのグリッドの少なくとも1つの場所は端子によって占有されない、請求項8に記載の超小型電子アセンブリ。
(請求項12)
前記第1のパッケージ及び前記第2のパッケージの前記グリッドの前記場所の少なくとも半分は、前記回路パネルの前記第1の表面に平行な直交するx方向及びy方向において互いに位置合わせされる、請求項8に記載の超小型電子アセンブリ。
(請求項13)
前記第1の超小型電子パッケージの前記第1の端子のうちの1つと、前記第2の超小型電子パッケージの前記第1の端子のうちの対応する1つとの間の電気接続のうちの少なくとも1つのスタブの長さは、前記超小型電子パッケージのそれぞれの前記第1の端子の最小ピッチの7倍未満である、請求項8に記載の超小型電子アセンブリ。
(請求項14)
前記第1の超小型電子パッケージの前記第1の端子と前記第2の超小型電子パッケージの前記第1の端子との間の前記回路パネルを通る前記電気的接続の少なくともいくつかは、前記回路パネルの厚み程度の電気長を有する、請求項8に記載の超小型電子アセンブリ。
(請求項15)
前記回路パネルの前記第1の表面及び前記第2の表面において露出する、電気的に結合される第1のパネルコンタクト及び第2のパネルコンタクトの各対を接続する前記導電性素子を結合した全長は、前記パネルコンタクトの最小ピッチの7倍未満である、請求項13に記載の超小型電子アセンブリ。
(請求項16)
前記回路パネルは、前記超小型電子パッケージのそれぞれに転送される全ての前記アドレス情報を運ぶように構成される複数の導体を有するバスを含み、前記導体は、前記第1の表面及び前記第2の表面に平行な第1の方向に延在する、請求項1に記載の超小型電子アセンブリ。
(請求項17)
各超小型電子パッケージの第1の端子の前記第1のグリッド及び前記第2のグリッドのそれぞれは、単一の列を有し、前記回路パネルは、前記超小型電子パッケージのうちの1つ又は複数の超小型電子パッケージの前記端子が電気的に接続される前記回路パネル上のそれぞれの接続サイト間で前記アドレス情報をルーティングする1つ以下のルーティング層を含む、請求項8に記載の超小型電子アセンブリ。
(請求項18)
各超小型電子パッケージの第1の端子の前記第1のグリッド及び前記第2のグリッドのそれぞれは、2つの平行な列を有し、前記回路パネルは、前記超小型電子パッケージのうちの1つ又は複数の超小型電子パッケージの前記端子が電気的に接続される前記回路パネル上のそれぞれの接続サイト間で前記アドレス情報をルーティングする2つ以下のルーティング層を含む、請求項8に記載の超小型電子アセンブリ。
(請求項19)
前記超小型電子パッケージのうちの1つ又は複数の超小型電子パッケージの前記端子が電気的に接続される前記回路パネル上のそれぞれの接続サイト間で、前記アドレス情報をルーティングする1つ以下のルーティング層がある、請求項18に記載の超小型電子アセンブリ。
(請求項20)
各超小型電子パッケージは、前記それぞれの端子のうちの少なくともいくつかに電気的に接続される半導体素子と、前記それぞれの超小型電子パッケージ内の前記超小型電子素子とを備え、各半導体素子は、前記超小型電子素子へ転送するように、前記それぞれの超小型電子パッケージの前記端子のうちの1つ又は複数において受信されるアドレス情報又はコマンド情報のうちの少なくとも一方を再生すること、又は少なくとも部分的に復号化することのうちの少なくとも1つを行うように構成される、請求項1に記載の超小型電子アセンブリ。
(請求項21)
各超小型電子パッケージの前記超小型電子素子は第1の超小型電子素子であり、各基板の前記基板コンタクトの組は基板コンタクトの第1の組であり、
各超小型電子パッケージは、面と、該面において露出する複数の素子コンタクトとを有する第2の超小型電子素子を更に備え、前記第2の超小型電子素子はメモリ記憶アレイを有し、
各基板は、前記それぞれの第2の超小型電子素子の前記素子コンタクトに面する前記第1の表面において露出され、該それぞれの第2の超小型電子素子の該素子コンタクトに接合される基板コンタクトの第2の組を有し、前記それぞれの超小型電子パッケージの前記端子は、前記基板コンタクトの第2の組に電気的に接続され、
各超小型電子パッケージの前記第1の組及び前記第2の組のそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージの前記第1の超小型電子素子及び前記第2の超小型電子素子のうちの少なくとも1つの超小型電子素子のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から1つのアドレス指定可能メモリ位置を決定するのに、前記それぞれの超小型電子パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成される、請求項1に記載の超小型電子アセンブリ。
(請求項22)
前記回路パネルは、12パーツパーミリオン/摂氏温度(「ppm/°C」)未満の熱膨張係数(「CTE」)を有する要素を含み、前記第1の表面及び前記第2の表面において露出する前記パネルコンタクトは、前記要素を通って延在するビアによって接続される、請求項1に記載の超小型電子アセンブリ。
(請求項23)
前記要素は本質的に、半導体、ガラス、セラミック、又は液晶ポリマー材料からなる、請求項1に記載の超小型電子アセンブリ。
(請求項24)
請求項1に記載の超小型電子アセンブリと、該超小型電子アセンブリに電気的に接続された1つ又は複数の他の電子構成要素とを備えるシステム。
(請求項25)
筐体を更に備え、前記超小型電子アセンブリ及び前記1つ又は複数の他の電子構成要素は、前記筐体に組み付けられる、請求項24に記載のシステム。
(請求項26)
請求項24に記載のシステムであって、前記超小型電子アセンブリは第1の超小型電子アセンブリであり、該システムは、第2の超小型電子アセンブリを更に備える、請求項24に記載のシステム。
(請求項27)
モジュールであって、請求項1に記載の超小型電子アセンブリを複数含み、各超小型電子アセンブリは、各超小型電子アセンブリに信号を搬送するとともに、各超小型電子アセンブリから信号を搬送するように、第2の回路パネルに取り付けられ、電気的に接続される、モジュール。
(請求項28)
超小型電子アセンブリであって、
互いに反対側の第1の表面及び第2の表面と、前記第1の表面及び前記第2の表面のそれぞれにおける第1のパネルコンタクト及び第2のパネルコンタクトとを有する回路パネルと、
それぞれが前記それぞれのパネルコンタクトに取り付けられる端子を有する第1の超小型電子パッケージ及び第2の超小型電子パッケージと、
を備え、各超小型電子パッケージは、
面と、該面上の複数の素子コンタクトとを有する超小型電子素子であって、メモリ記憶アレイ機能を提供する能動素子の数をいかなる他の機能よりも多く具体化する、超小型電子素子と、
互いに反対側の第1の表面及び第2の表面を有する基板であって、前記超小型電子素子の前記素子コンタクトに面する前記第1の表面上に、該超小型電子素子の該素子コンタクトに接合される1組の基板コンタクトを有する、基板と、
前記超小型電子パッケージを、該パッケージの外部にある少なくとも1つの構成要素に接続するように構成される、前記第2の表面上の複数の端子であって、該端子は、前記基板コンタクトに電気的に接続され、平行な第1のグリッド及び第2のグリッド内の場所に配置される第1の端子を含み、前記第1のグリッド及び前記第2のグリッドのそれぞれの前記第1の端子は、前記超小型電子素子内のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から1つのアドレス指定可能メモリ位置を決定するのに前記超小型要素パッケージ内の回路によって使用可能なアドレス情報の大部分を運ぶように構成される、複数の端子と、
を備え
前記第1のグリッド内の前記第1の端子の信号割り当ては、前記第2のグリッド内の前記第1の端子の信号割り当ての鏡像である、超小型電子アセンブリ。
(請求項29)
各超小型電子パッケージの前記第1のグリッド及び前記第2のグリッドのそれぞれの前記第1の端子は、前記アドレス指定可能メモリ位置を決定するのに前記それぞれの超小型要素パッケージ内の回路によって使用可能な前記アドレス情報の少なくとも3/4を運ぶように構成される、請求項28に記載の超小型電子アセンブリ。
(請求項30)
超小型電子アセンブリであって、
互いに反対側の第1の表面及び第2の表面と、前記第1の表面及び前記第2の表面においてそれぞれの露出する第1のパネルコンタクト及び第2のパネルコンタクトとを有する回路パネルと、
それぞれが前記それぞれのパネルコンタクトに取り付けられる端子を有する第1の超小型電子パッケージ及び第2の超小型電子パッケージと、
を備え、各超小型電子パッケージは、
面と、該面において露出する複数の素子コンタクトとを有する超小型電子素子であって、メモリ記憶アレイ機能を有する、超小型電子素子と、
互いに反対側の第1の表面及び第2の表面を有する基板であって、前記超小型電子素子の前記素子コンタクトに面する前記第1の表面において露出し、該超小型電子素子の該素子コンタクトに接合される1組の基板コンタクトを有する、基板と、
前記超小型電子パッケージを、該パッケージの外部にある少なくとも1つの構成要素に接続するように構成される、前記第2の表面において露出する複数の端子であって、該端子は、前記基板コンタクトに電気的に接続され、複数の第1の端子を含み、該第1の端子は、理論的軸の第1の側に配置される第1の端子の第1の組と、前記第1の側と反対側の前記軸の第2の側に配置される第1の端子の第2の組とを含み、前記第1の端子の第1の組は第1の個々の列に配置され、前記第1の端子の第2の組は第2の個々の列に配置され、前記第1の列及び前記第2の列のそれぞれの前記第1の端子は、前記超小型電子素子のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から1つのアドレス指定可能メモリ位置を決定するのに前記超小型電子パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成される、複数の端子と、
前記第1の列内の前記第1の端子の信号割り当ては、前記第2の列内の前記第1の端子の信号割り当てに関して、前記第1の列と前記第2の列との間に延在する理論的軸について対称である、超小型電子アセンブリ。
(請求項31)
各超小型電子パッケージの前記超小型電子素子は、メモリ記憶アレイ機能を提供する能動素子の数をいかなる他の機能よりも多く具体化する、請求項30に記載の超小型電子アセンブリ。
Claims (10)
- 超小型電子アセンブリであって、
互いに反対側の第1の表面及び第2の表面と、前記第1の表面における第1のパネルコンタクト及び前記第2の表面における第2のパネルコンタクトとを有する回路パネルと、
それぞれが前記それぞれのパネルコンタクトに取り付けられる端子を有する第1の超小型電子パッケージ及び第2の超小型電子パッケージと、
を備え、各超小型電子パッケージは、
面と、該面上の複数の素子コンタクトとを有する超小型電子素子であって、メモリ記憶アレイ機能を有する超小型電子素子と、
互いに反対側の第1の表面及び第2の表面を有する基板であって、前記超小型電子素子の前記素子コンタクトに面する前記第1の表面上にあって該素子コンタクトに接合される1組の基板コンタクトを有する、基板と、
前記基板の前記第2の表面において露出するそれぞれの超小型電子パッケージの前記端子であって、該端子は、前記基板コンタクトに電気的に接続され、平行な第1のグリッド及び第2のグリッド内の場所において配置された第1の端子を含み、それぞれのグリッドは、軸のそれぞれの側に配置され、前記それぞれの超小型電子パッケージの前記第1のグリッド及び前記第2のグリッドのそれぞれの前記第1の端子は、それぞれの超小型電子素子内のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中からアドレス指定可能メモリ位置を決定するのに前記それぞれの超小型電子パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成され、前記それぞれの超小型電子パッケージの前記端子は、平行な第3のグリッド及び第4のグリッド内の場所において配置されかつ第2の情報を運ぶように構成された第2の端子を含み、該第2の情報は、前記それぞれの超小型電子パッケージの前記第1の端子によって運ばれる前記情報以外の情報であり、該第2の情報は、データ信号を含み、前記それぞれの超小型電子パッケージの前記第1のグリッド及び前記第2のグリッドは、前記第3のグリッド及び前記第4のグリッドを互いから分離する、前記端子と、
を備え、
前記第1の端子は、信号割り当てを有し、前記第1のグリッド内の前記第1の端子の信号割り当ては、アドレス情報を運ぶように構成された前記第1のグリッドの前記第1の端子の信号割り当てのような、前記第2のグリッド内の前記第1の端子の信号割り当てと、前記軸に関して対称であり、当該第1の端子のそれぞれは、当該第1の端子に関し、前記軸に関して対称な位置における前記第2のグリッドの前記第1の端子のうちの対応する端子と同じアドレス情報を運ぶように構成される、超小型電子アセンブリ。 - 各超小型電子パッケージの前記第1のグリッド及び前記第2のグリッドのそれぞれの前記第1の端子は、前記アドレス指定可能メモリ位置を決定するのに前記それぞれの超小型電子パッケージ内の前記回路によって使用可能な前記アドレス情報の全てを運ぶように構成される、請求項1に記載の超小型電子アセンブリ。
- 前記第1の超小型電子パッケージの前記第2のグリッド内の前記第1の端子は、前記回路パネルを通して、前記第2の超小型電子パッケージの前記第1のグリッド内の前記第1の端子に接続され、前記第1の超小型電子パッケージの前記第2のグリッドの前記第1の端子は、前記回路パネルの前記第1の表面及び前記第2表面に平行な直交するx方向及びy方向において、該第2のグリッドの該第1の端子が接続される前記第2の超小型電子パッケージの前記第1のグリッド内の対応する前記第1の端子の1ボールピッチ内に位置合わせされる、請求項1に記載の超小型電子アセンブリ。
- 前記第1の超小型電子パッケージの前記第1の端子のうちの1つと、前記第2の超小型電子パッケージの前記第1の端子のうちの対応する1つとの間の電気的接続のうちの少なくとも1つの電気的接続のスタブの長さは、前記超小型電子パッケージのそれぞれの前記第1の端子の最小ピッチの7倍未満である、請求項3に記載の超小型電子アセンブリ。
- 前記回路パネルの前記第1の表面及び前記第2の表面において露出する、電気的に結合される第1のパネルコンタクト及び第2のパネルコンタクトの各対を接続する導電性素子を結合した全長は、前記パネルコンタクトの最小ピッチの7倍未満である、請求項4に記載の超小型電子アセンブリ。
- 前記第1の超小型電子パッケージの前記第1の端子と前記第2の超小型電子パッケージの前記第1の端子との間の前記回路パネルを通る電気的接続の少なくともいくつかは、前記回路パネルの厚み程度の電気長を有する、請求項3に記載の超小型電子アセンブリ。
- 前記回路パネルは、前記超小型電子パッケージのそれぞれに転送される前記アドレス情報の全てを運ぶように構成される複数の導体を有するバスを含み、前記導体は、前記第1の表面及び前記第2の表面に平行な第1の方向に延在する、請求項1に記載の超小型電子アセンブリ。
- 各超小型電子パッケージの前記超小型電子素子は第1の超小型電子素子であり、各基板の前記基板コンタクトの組は基板コンタクトの第1の組であり、
各超小型電子パッケージは、面と、該面上の複数の素子コンタクトとを有する第2の超小型電子素子を更に備え、該第2の超小型電子素子は、メモリ記憶アレイ機能を有し、
各基板は、前記第2の超小型電子素子の前記素子コンタクトに面する前記第1の表面上にありかつ該素子コンタクトに接合される基板コンタクトの第2の組を有し、前記それぞれの超小型電子パッケージの前記端子は、前記基板コンタクトの第2の組に電気的に接続され、
各超小型電子パッケージの前記第1のグリッド及び前記第2のグリッドのそれぞれの前記第1の端子は、前記それぞれの超小型電子パッケージの前記第1の超小型電子素子及び前記第2の超小型電子素子内のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中からアドレス指定可能メモリ位置を決定するのに前記それぞれの超小型電子パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成される、請求項1に記載の超小型電子アセンブリ。 - 請求項1に記載の超小型電子アセンブリと、該超小型電子アセンブリに電気的に接続された1つ又は複数の他の電子構成要素とを備えるシステム。
- 筐体を更に備え、前記超小型電子アセンブリ及び前記1つ又は複数の他の電子構成要素は、前記筐体に組み付けられる、請求項9に記載のシステム。
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US13/439,228 US8659139B2 (en) | 2011-10-03 | 2012-04-04 | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
PCT/US2012/057173 WO2013052321A2 (en) | 2011-10-03 | 2012-09-26 | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9425237B2 (en) | 2014-03-11 | 2016-08-23 | Crossbar, Inc. | Selector device for two-terminal memory |
US9768234B2 (en) * | 2014-05-20 | 2017-09-19 | Crossbar, Inc. | Resistive memory architecture and devices |
US10211397B1 (en) | 2014-07-07 | 2019-02-19 | Crossbar, Inc. | Threshold voltage tuning for a volatile selection device |
US9633724B2 (en) | 2014-07-07 | 2017-04-25 | Crossbar, Inc. | Sensing a non-volatile memory device utilizing selector device holding characteristics |
US9698201B2 (en) | 2014-07-09 | 2017-07-04 | Crossbar, Inc. | High density selector-based non volatile memory cell and fabrication |
US10115819B2 (en) | 2015-05-29 | 2018-10-30 | Crossbar, Inc. | Recessed high voltage metal oxide semiconductor transistor for RRAM cell |
US9685483B2 (en) | 2014-07-09 | 2017-06-20 | Crossbar, Inc. | Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process |
US9460788B2 (en) | 2014-07-09 | 2016-10-04 | Crossbar, Inc. | Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor |
US10079192B2 (en) * | 2015-05-05 | 2018-09-18 | Mediatek Inc. | Semiconductor chip package assembly with improved heat dissipation performance |
WO2017049587A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Packaged integrated circuit device with recess structure |
TWI615717B (zh) * | 2016-01-25 | 2018-02-21 | 凌陽科技股份有限公司 | 高階製程晶片與低階製程晶片的資料傳輸方法以及使用其之積體電路 |
US20180005944A1 (en) * | 2016-07-02 | 2018-01-04 | Intel Corporation | Substrate with sub-interconnect layer |
US10607977B2 (en) | 2017-01-20 | 2020-03-31 | Google Llc | Integrated DRAM with low-voltage swing I/O |
US10096362B1 (en) | 2017-03-24 | 2018-10-09 | Crossbar, Inc. | Switching block configuration bit comprising a non-volatile memory cell |
JP7059970B2 (ja) * | 2019-03-11 | 2022-04-26 | 株式会社デンソー | 半導体装置 |
KR102026163B1 (ko) * | 2019-07-02 | 2019-09-27 | 김복문 | 반도체 패키지의 배선 보정방법 |
TWI768294B (zh) * | 2019-12-31 | 2022-06-21 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
JPH08186227A (ja) * | 1995-01-05 | 1996-07-16 | Hitachi Ltd | 半導体装置及び電子装置 |
JPH1187640A (ja) * | 1997-09-09 | 1999-03-30 | Hitachi Ltd | 半導体装置および電子装置 |
JP2000315776A (ja) * | 1999-05-06 | 2000-11-14 | Hitachi Ltd | 半導体装置 |
JP3874062B2 (ja) * | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | 半導体装置 |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
JP5004385B2 (ja) * | 2001-08-03 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | 半導体メモリチップとそれを用いた半導体メモリ装置 |
DE10139085A1 (de) * | 2001-08-16 | 2003-05-22 | Infineon Technologies Ag | Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung |
KR100454123B1 (ko) * | 2001-12-06 | 2004-10-26 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그것을 구비한 모듈 |
JP4906047B2 (ja) * | 2005-11-28 | 2012-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20070241441A1 (en) * | 2006-04-17 | 2007-10-18 | Stats Chippac Ltd. | Multichip package system |
JP2007013146A (ja) * | 2006-06-26 | 2007-01-18 | Renesas Technology Corp | 半導体集積回路装置 |
JP4362784B2 (ja) * | 2006-07-06 | 2009-11-11 | エルピーダメモリ株式会社 | 半導体装置 |
US7696629B2 (en) * | 2007-04-30 | 2010-04-13 | Chipmos Technology Inc. | Chip-stacked package structure |
KR20100046760A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 반도체 패키지 |
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