CN104701272B - 一种芯片封装组件及其制造方法 - Google Patents
一种芯片封装组件及其制造方法 Download PDFInfo
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- CN104701272B CN104701272B CN201510126379.5A CN201510126379A CN104701272B CN 104701272 B CN104701272 B CN 104701272B CN 201510126379 A CN201510126379 A CN 201510126379A CN 104701272 B CN104701272 B CN 104701272B
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Abstract
本申请提供了一种芯片封装组件及其制造方法,在本发明提供的芯片封装组件中,通过将用于与芯片第三表面和第四表面上的电极分别与位于芯片上下方和上方的第一组内引脚、第二组内引脚以及层间内引脚引出,再通过位于塑封体侧面且延伸至封装组件最底面或最顶面的第一组外引脚、第二组外引脚、层间外引脚组与第一组件内引脚、第二组内引脚、层间内引脚组电连接,以将芯片上的电极引到所述封装组件的外部,以用于与外部电路电连接,可有效的减小了芯片的封装面积和厚度,提高了芯片封装的效率,以及通过内引脚和外引脚引出电极的方式可有效减小了芯片封装的寄生电阻,且封装组件的外引脚均裸露在塑封体之外,有利于提高封装组件的散热性。
Description
技术领域
本发明涉及芯片封装技术领域,尤其涉及一种芯片封装组件及其制造方法。
背景技术
在传统的芯片正装封装组件结构中,芯片的非有源面粘附于引线框架的芯片承载盘上,芯片的有源面上的电极通过金属引线电连接到承载盘周围的引脚上,从而将芯片有源面上的电极引出与外部电路连接。
然而,随着电子元件的小型化、轻量化以及多功能化的需求的增加,对半导体封装面积及厚度的要求越来越高。传统的这种通过引线键合的封装方式由于引脚与承载盘具有一定的距离,再加上引脚本身也具有一定的尺寸,使得封装面积较大,而且通过引线键合,不利于减小封装组件的高度,再加上通过金属引线来引出电极的方式,还会使得封装组件具有较大的寄生电阻,不利于提高封装的质量。
有此可见,传统的这种通过引线键合技术实现的芯片正装封装组件,已经无法满足对半导体封装面积及厚度的要求,需要寻求新的芯片正装封装方式。
发明内容
有鉴于此,本发明的目的是提供一种芯片封装组件及其制造方法,以减小封装组件面积,降低封装组件的厚度,提高封装效率。
一种芯片封装组件,包括:
位于底层的第一基板,具有第一表面和与所述第一表面相对的第二表面,所述第二表面上设置有第一组内引脚;
位于所述第一组内引脚之上的至少一个芯片层,每一个芯片层均具有第三表面和与第三表面相对的第四表面,位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
位于最顶层的所述第四表面之上且具有第五表面的第二基板,所述第五表面上设置有第二组内引脚,所述第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接,所述第二基板还具有与所述第五表面相对的第六表面;
塑封体,位于所述第一基板与第二基板之间的空隙,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
第一组外引脚、第二组外引脚,均位于所述塑封体的侧面,以分别与所述第一组内引脚、第二组内引脚电连接,并均延伸至所述第二表面上或均延伸至所述第六表面。
优选的,所述塑封体具有第一侧面和所述第一侧面相对的第二侧面,
所述第一侧面裸露出所述第一组内引脚,所述第二侧面裸露出所述第二组内引脚,
所述第一组外引脚位于所述第一侧面,并延伸至所述第二表面上或第六表面的一侧,所述第二组外引脚位于所述第二侧面的另一侧,并延伸至所述第二表面上或第六表面的另一侧。
优选的,所述第一连接体为银胶、焊锡中的一种,或者所述第一连接体包括位于所述第一组内引脚上的第一共晶层和位于所述第三表面上的电极上的第二共晶层,且所述第一共晶层与所述第二共晶层形成共晶连接。
优选的,所述第二连接体包括位于所述第四表面的电极上的第三共晶层和位于所述第二组内引脚上的第四共晶层,且所述第三共晶层与所述第四共晶层形成共晶连接,或者所述第二连接体为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
优选的,所述第三共晶层为钛镍银合金层,所述第四共晶层为银或锡金属层。
优选的,所述第一组外引脚与第二组外引脚的一端分别延伸至所述第二表面的两侧,另一端分别延伸至所述第六表面的两侧。
优选的,所述第一组外引脚和第二组外引脚均包括与所述塑封体相接触的铜层或银层,以及位于铜层或银层上的锡层。
优选的,所述封装组件包括多个所述芯片层,还包括位于所述芯层之间的层间内引脚组和位于所述塑封体侧面并延伸至所述第二表面上或所述第六表面上的层间外引脚组,
位于最底层的所述第三表面之上的每一个所述第三表面上的电极均通过第一中间连接体与位于其下方的层间内引脚组电连接,
位于最顶层的所述第四表面之下的每一个所述第四表面上的电极均通过第二中间连接体与位于其上方的层间内引脚组电连接;
所述层间内引脚组裸露于所述塑封体的侧面,并与所述层间外引脚组电连接。
优选的,所述塑封体包括多个塑封体层,每一个所述塑封体层包封一个所述芯片层。
一种芯片封装组件的制造方法,包括:
在第一基板的第一表面上形成图案化的导电层,以作为第一组内引脚,所述第一基板还具有与所述第一表面与相对的第二表面;
在所述第一组内引脚之上安装至少一个芯片层,每一个所述芯片均具有第三表面和与所述第三表面相对的第四表面,将位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接;
在所述第一基板和第二基板之间填充塑封料,以形成塑封体,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
在所述塑封体的侧面上形成与所述第一内引脚电连接的第一组外引脚、与所述第二组内引脚电连接的第二组外引脚,且使所述第一外引脚、第二组外引脚均延伸至所述第二表面上或所述第二基板的第六表面上,所述第六表面为与所述第五表面相对的一面。
优选的,所述塑封体具有第一侧面和所述第一侧面相对的第二侧面,
使所述第一侧面裸露出所述第一组内引脚,所述第二侧面裸露出所述第二组内引脚,
且使所述第一组外引脚位于所述第一侧面,并延伸至所述第二表面上或第六表面的一侧,所述第二组外引脚位于所述第二侧面的另一侧,并延伸至所述第二表面上或第六表面的另一侧。
优选的,所述制造方法还包括在将所述第二组内引脚通过第二连接体与所述第四表面上的电极电连接之前,在所述第五表面上形成图案化的导电层,以作为第二组内引脚。
优选的,所述第一连接体为银胶、焊锡中的一种,或者所述第一连接体包括形成于所述第一组内引脚上的第一共晶层和形成于所述第三表面的电极上的第二共晶层,且所述第一共晶层与所述第二共晶层形成共晶连接。
优选的,所述第二连接体包括形成于所述第四表面的电极上的第三共晶层和形成于所述第二组内引脚上的第四共晶层,且所述第三共晶层与所述第四共晶层形成共晶连接,或者所述第二连接体为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
优选的,所述制造方法还包括在所述第四表面的电极上形成钛镍银合金层,以作为所述第三共晶层,在所述第二组内引脚上形成银或锡金属层,以作为所述第四共晶层。
优选的,使所述第一组外引脚与第二组外引脚的一端分别延伸至所述第二表面的两侧,另一端分别延伸至所述第六表面的两侧。
优选的,形成所述第一组外引脚和第二组外引脚的步骤为:采用掩模裸露出所述第一组外引脚和第二组外引脚所在的外引脚区域,再利用电镀工艺在所述外引脚区域生长铜层或银层,再在所述铜层或银层的表面涂敷锡层。
优选的,在所述第一组内引脚之上安装的所述芯片层包括第一芯片层和位于第一芯片层之上的第二芯片层,
在将位于所述第一芯片层的第三表面上的电极通过第一连接体与所述第一组内引脚电连接之后,和将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连接之前,所述制造方法还包括:
将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接;
去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接。
优选的,在所述第一基板和第二基板之间填充塑封料,以形成塑封体的步骤包括:
在将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接的步骤和去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接的步骤之间,在所述第一基板和所述中间基板之间填充塑封料,以形成包封所述第一芯片层的第一层塑封体,且使所述第一层塑封体的侧面裸露出所述第一组内引脚和层间组内引脚;
在将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连的步骤之后,在所述第层塑封体层和所述第二基板之间填充塑封料,以形成包封所述第二芯片层的第二层塑封体,且使所述第二层塑封体的侧面裸露出所述第二组内引脚;
所述第一塑封体层和第二塑封体层共同形成所述塑封体层。
优选的,所述制造方法还包括在所述塑封体侧面形成层间外引脚组,所述层间外引脚组与所述层间内引脚组电连接,且延伸至所述第二表面上或第六表面上。
由上可见,本发明提供的芯片封装组件及其制造方法,通过将用于与芯片第三表面和第四表面上的电极分别与位于芯片上下方和上方的第一组内引脚、第二组内引脚以及层间内引脚引出,再通过位于塑封体侧面且延伸至封装组件最底面或最顶面的第一组外引脚、第二组外引脚、层间外引脚组与第一组件内引脚、第二组内引脚、层间内引脚组电连接,以将芯片上的电极引到所述封装组件的外部,以用于与外部电路电连接,可有效的减小了芯片的封装面积和厚度,提高了芯片封装的效率,以及通过内引脚和外引脚引出电极的方式可有效减小了芯片封装的寄生电阻,且封装组件的外引脚均裸露在塑封体之外,有利于提高封装组件的散热性。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1为根据本发明实施例的芯片封装组件的剖面结构示意图。
图2为根据本发明实施例的芯片封装组件从第一侧面方向看的侧视图。
图3为根据本发明实施例的芯片封装组件从第二侧面方向看的侧视图;
图4为根据本发明实施例的芯片封装组件从第二表面B方向看的顶仰视图。
图5a~图5e为根据本发明实施例的一种芯片封装组件的制造工艺流程中各个工艺步骤形成结构的剖面示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中,相同的组成部分采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。此外,可能未示出某些公知的部分。为了简明起见,可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节,例如每个组成部分的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。
本发明提供的芯片封装组件,包括:
位于底层的第一基板,具有第一表面和与所述第一表面相对的第二表面,所述第二表面上设置有第一组内引脚;
位于所述第一组内引脚之上的至少一个芯片层,每一个芯片层均具有第三表面和与第三表面相对的第四表面,位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
位于最顶层的所述第四表面之上且具有第五表面的第二基板,所述第五表面上设置有第二组内引脚,所述第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接,所述第二基板还具有与所述第五表面相对的第六表面;
塑封体,位于所述第一基板与第二基板之间的空隙,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
第一组外引脚、第二组外引脚,均位于所述塑封体的侧面,以分别与所述第一组内引脚、第二组内引脚电连接,并均延伸至所述第二表面上或均延伸至所述第六表面。
这种芯片封装结构,由于通过与芯片层叠层放置的内引脚将位于芯片上的电极引出,再利用位于塑封体侧面的外引脚与对应的内引脚电连接,且使外引脚由塑封体的表面延伸至封装组件的最底面或最顶面,以把与外部电路连接的电极端子引到芯片层正上方或正下方,因此,可有效的减小了芯片的封装面积和厚度,且可提高芯片的散热性能和封装的可靠性。
在本发明提供的芯片封装组件中,所封装的芯片可以包括一个芯片层,也可以包括多个芯片层,下面的实施例中为了做图便于观看,以更好的理解发明的构思,均以封装一个芯片层为例来对本发明的封装组件及其制造方法进行具体的描述,但本领域的技术人员可以根据本申请中所提供的封装一个芯片层的实施例,再结合本发明的思想,可以很容易的扩展到两个芯片层或者多个芯片层的封装。因此,本发明提供的芯片封装组件,不限定于一个芯片层的封装。
图1为根据本发明实施例的芯片封装组件100的剖面结构示意图。
参考图1所示,在本发明实施例提供的芯片封装组100包括:位于底层且具有第一表面A与第二表面B的第一基板1,第一表面A上设置有第一组内引脚2;位于第一组内引脚2之上且具有第三表面C与第四表面D的芯片3,第三表面C与第四表面D相对,且其上的电极通过第一连接体4与第一组内引脚2 电连接;位于芯片3之上且具有第五表面E的第二基板5,第五表面E上设置有第二组内引脚6,第二组内引脚6通过第二连接体7与第四表面D上的电极电连接;位于第一基板1与第二基板2之间的空隙,且具有第一侧面G与第二侧面H的塑封体8,其中,第一侧面G裸露出第一组内引脚2,而第二侧面H 裸露出第二组内引脚6;位于第一侧面G而与第一组内引脚2电连接,并延伸至第二表面B的一侧的第一组外引脚9;位于第二侧面H而与第二组内引脚6 电连接,并延伸至第二表面B的另一侧的第二组外引脚10。
在本实施例中,所述第一组内引脚和第二组内引脚分别位于所述塑封体的第一侧和第二侧,这样有利于电极端子在封装组件外部的布局,但所述第一组内引脚和第二组内引脚只要裸露于塑封体的侧面既可,并不限定于本实施例这种方式。
在本发明实施例的芯片封装组件100中,第一基板1与第二基板5均选自绝缘材料形成,如可以为形成塑封体8的塑封料等。第一组内引脚1、中第二组内引脚6中所包括的内引脚数目可分别根据第三表面C上的电极或电路、第四表面D上的电极或电路来设定,而第一组外引脚9、第二组外引脚10中所包括的外引脚数目又可分别根据第一组内引脚1、中第二组内引脚6的引脚数目来设定。一般的是第三表面、第四表面上有多少个电极,则第一组内引脚、第二组内引脚包括多少个内引脚,同样第一组外引脚、第二组外引脚也包括多少个外引脚,但电极、内引脚和外引脚之间的关系不局限于一一对应关系,而可以根据实际电路的连接需求来设定。在封装组件100中,第三表面C、第四表面D 上的电极个数分别为1个、3个,则封装组件从第一侧面G方向看的侧视图如图2所示,从第二侧面H方向看的侧视图如图3所示,从第二表面B方向看的顶仰视图如图4所示。从图2至图4中可以看出,第一组内引脚2包括内引脚 21,则第一组外引脚9包括外引脚91,外引脚91位于第一侧面G上而与内引脚21电连接,且延伸至第二表面B的一侧,以将第三表面C上的电极引出到第二表面B的一侧,用于与外部电路电连接。第二组内引脚6包括内引脚61、内引脚62、内引脚63,则第二组外引脚10包括外引脚101、外引脚102、外引脚 103,均位于第而侧面G上而分别与内引脚61、内引脚62、内引脚63电连接,且均延伸至第二表面B的另一侧,以将第四表面D上的电极引出到第二表面B 的另一侧,用于与外部电路电连接。由此可见,在封装组件100中,第一组内引脚2、芯片3、第二组内引脚6三者叠层放置,只要保证芯片3离第二侧面H 的具体大于第二组内引脚离第二侧面H的距离即可,则三者组成的叠层结构横的尺寸(面积)可以设计得只略大于芯片3的尺寸,而用于引出芯片电极的第一组外引脚和第二组外引脚分别位于塑封体的两侧,且延伸至第二表面的两侧,因此整个封装组件100的面积可做到几乎的接近芯片3的面积,具有非常高的封装效率。此外,第一组外引脚和第二组外已经均裸露在塑封体的外面,有利于封装组件的散热。由于第一组外引脚和第二组外引脚需要附着与塑封体的两侧且向第二表面的两侧延伸,因此而二者可均由位于位于塑封体侧面上的铜层或银层或其它与塑封料粘附性较好的一种金属层,以及位于所述铜层或银层或其它与塑封料粘附性较好的一种金属层上的锡层形成。
在本实施例提供的封装组件100中,第二基板5还包括与第五表面E相对的第六表面F,第一组外引脚和第二组外引脚还可以进一步的均延伸至第六表面 F的两侧。因而封装组件100既可以通过将第二表面B贴在印刷电路板上与外部电路相连,又可以通过将第六表面F贴在印刷电路板上与外部电路相连,还可以双面接外部电路,便于灵活应用。
在本实施例提供的封装组件100中,用于将第三表面C上的电极和第一组内引脚2电连接的第一连接体4可以选自银胶、焊锡中的一种,即通过点胶或者焊接的方式将芯片第三表面上的电极与第一组内引脚电连接。在一些实施例中,第一连接体4还可是共晶连接结构,即其包括位于所述第一组内引脚2上的第一共晶层和位于所述第三表面C上的电极上的第二共晶层(第一共晶层与第二共晶层在图中未画出),且所述第一共晶层与所述第二共晶层形成共晶连接。
此外,在本封装组件100中,用于将第四表面D上的电极和第二组内引脚 6电连接的第二连接体7(图中虚线圈标记处)为共晶连接结构,第二连接体7 包括位于所述第四表面D的电极上的第三共晶层71和位于所述第二组内引脚6 上的第四共晶层72,且所述第三共晶层71与所述第四共晶层72形成共晶连接。第三共晶层71与第四共晶层72通常选用彼此能实现较好的共晶连接结构的材料,例如在本实施例中,第三共晶层71可以为钛镍银合金层,而第四共晶层72 为银或锡金属层。利于共晶连接,来实现芯片电极与内引脚之间的电连接,可以有效的减小封装组件的封装厚度,且相比于传统的键合引线连接,工艺步骤更加简化。当然在本发明中,第二连接体不局限于共晶连接结构,在一些实施例中,第二连接体还可为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
本实施例提供的芯片封装组件100只包括个芯片层,且该芯片层中只包括一块芯片3,但是在根据本发明思想实现的其它实施例中,每一个芯片层还可以包括多块芯片,同一层芯片层中的芯片的第三表面与第四表面上电极引出方式可相同。此外根据本发明思想实现的其它实施例中,封装组件中的芯片层还可以包括两个或两个以上的多层芯片层。在进行多层芯片层封装时(即封装组件 100的芯片3和第二组内引脚6之间还包括至少一个芯片层),所述封装组件,还包括位于所述芯层之间的层间内引脚组和位于所述塑封体侧面并延伸至所述第二表面上或所述第六表面上的层间外引脚组,每一个芯片层具有一个与芯片3 的第三表面、第四表面相对应的第三表面、第四表面,且位于最底层的所述第三表面之上的每一个所述第三表面(位于芯片3之上的芯片层的第三表面)上的电极均通过第一中间连接体与位于其下方的层间内引脚组电连接,位于最顶层的所述第四表面之下的每一个所述第四表面上的电极均通过第二中间连接体与位于其上方的层间内引脚组电连接;所述层间内引脚组裸露于所述塑封体的侧面,并与所述层间外引脚组电连接。
由于多层芯片的封装组件做图比较复杂,且本领域的技术人员根据一个芯片层的封装结构的构思比较容易的能得到多个芯片层的封装结构,因此不在对多个芯片层的封装组件做具体实施例分析。
在本发明提供的芯片封装组件中,通过将用于与芯片第三表面和第四表面上的电极分别与位于芯片上下方和上方的第一组内引脚、第二组内引脚以及层间内引脚引出,再通过位于塑封体侧面且延伸至封装组件最底面或最顶面的第一组外引脚、第二组外引脚、层间外引脚组与第一组件内引脚、第二组内引脚、层间内引脚组电连接,以将芯片上的电极引到所述封装组件的外部,以用于与外部电路电连接,可有效的减小了芯片的封装面积和厚度,提高了芯片封装的效率,以及通过内引脚和外引脚引出电极的方式可有效减小了芯片封装的寄生电阻,且封装组件的外引脚均裸露在塑封体之外,有利于提高封装组件的散热性。
本发明还提供一种芯片的封装组件的制造方法,其包括:
在第一基板的第一表面上形成图案化的导电层,以作为第一组内引脚,所述第一基板还具有与所述第一表面与相对的第二表面;
在所述第一组内引脚之上安装至少一个芯片层,每一个所述芯片均具有第三表面和与所述第三表面相对的第四表面,将位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接;
在所述第一基板和第二基板之间填充塑封料,以形成塑封体,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
在所述塑封体的侧面上形成与所述第一内引脚电连接的第一组外引脚、与所述第二组内引脚电连接的第二组外引脚,且使所述第一外引脚、第二组外引脚均延伸至所述第二表面上或所述第二基板的第六表面上,所述第六表面为与所述第五表面相对的一面。
上述工艺步骤的顺序在本发明中不做限定,此外,由制作多层芯片层封装组件的制造工艺步骤形成结构的剖面图比较复杂,且本领域的技术人员根据一个芯片层的封装工艺流程实施例以及多个芯片层的封装组件制造工艺的概述可以根据本发明构思,很容易的实现多个芯片层封装组件的制造,因此在本申请实施例中,将不对根据本发明思想的多个芯片层的封装组件的制造过程做比较详细的描述,仅对一个芯片层的封装组件的制造过程做具体的描述。
图5a~图5e为根据本发明实施例的一种芯片封装组件的制造工艺流程中各个工艺步骤形成结构的剖面示意图。
本发一明实施例提供的芯片封装组件的制造方法包括以工艺步骤,但本发明提供的芯片封装组件制备的工艺步骤顺序不局限于下述顺序。
步骤一,如图5a所示,在第一基板1的第一表面A上形成图案化的导电层,以作为第一组内引脚2,第一组内引脚2所包括的引脚个数或导电层的图案根据后续被封装的芯片3的上电极或电路所决定,此外,第一基板1还具有与第一表面A与相对的第二表面B。第一基板1的通常选用绝缘材料形成。
步骤二,如图5b所示,将芯片3的第三表面C上的电极通过第一连接体4 与第一组内引脚2电连接,其中,芯片3还具有与第三表面C相对的第四表面D。
用于将第三表面C上的电极和第一组内引脚2电连接的第一连接体4可以选自银胶、焊锡中的一种,即通过点胶或者焊接的方式将芯片第三表面C上的电极与第一组内引脚2电连接。在一些实施例中,第一连接体4还可是共晶连接结构,即其包括位于所述第一组内引脚2上的第一共晶层和位于所述第三表面C上的电极上的第二共晶层(第一共晶层与第二共晶层在图中未画出),且所述第一共晶层与所述第二共晶层形成共晶连接。
步骤三,如图5c所示,提供具有第五表面E上具有第二组内引脚6的第二基板5,将第二组内引脚6通过第二连接体7与第四表面上D的电极电连接。在此之前,本发明提供的芯片封装组件制造步骤还包括在第二基板5上形成图案化的导电层,以形成第二组内引脚6,第二组内引脚6的个数或形成其的导电层的图案可根据芯片3的第四表面上的电极或电路来设定。其中,二基板5一般也选自绝缘材料,其可与第一基板1的材料相同。
此外,在本发明中,用于将第四表面D上的电极和第二组内引脚6电连接的第二连接体7(图中虚线圈标记处)为共晶连接结构,即第二连接体7包括位于所述第四表面D的电极上的第三共晶层71和位于所述第二组内引脚6上的第四共晶层72,且所述第三共晶层71与所述第四共晶层72形成共晶连接。第三共晶层71与第四共晶层72通常选用彼此能实现较好的共晶连接结构的材料,例如在本实施例中,在第三四表面的电极上形成钛镍银合金层,以作为第三共晶层,在第二内引脚6上形成银或锡金属层,以作为第四共晶层72,然后利用利于共晶连接工艺,来实现芯片电极与内引脚之间的电连接。因此,这种共晶连接工艺,可以有效的减小封装组件的封装厚度,且相比于传统的键合引线连接,工艺步骤更加简化。当然在本发明中,第二连接体不局限于共晶连接结构,在一些实施例中,第二连接体还可为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
步骤四,如图5d所示,在第一基板1和第二基板5之间的空隙填充塑封料,以形成具有第一侧面G和第二侧面H的塑封体8,且使所述第一侧面G裸露出所述第一组内引脚2,所述第二侧面G裸露出所述第二组内引脚6,其中,所述第一侧面G与所述第二侧面H相对。使第一侧面G、第二侧面H上裸露出第一组内引脚2、第二组内引脚6的方法具体为,在完成第一基板1与第二基板2之间的塑封料填充工艺后,切割并打磨塑封体的两侧,以形成分别裸露出第一组内引脚、第二引脚的第一侧面、第二侧面。其中,形成塑封体8的材料可与第一基板1与第二基板6的材料相同。
在本实施例中,所述第一组内引脚和第二组内引脚分别位于所述塑封体的第一侧和第二侧,这样有利于电极端子在封装组件外部的布局,但所述第一组内引脚和第二组内引脚只要裸露于塑封体的侧面既可,并不限定于本实施例这种方式。
步骤五,如图5e所示,在第一侧面G、第二侧面H上分别形成与第一内引脚2电连接的第一组外引脚9、与第二组内引脚6电连接的第二组外引脚10,且使第一外引脚9延伸至所述第二表面B的一侧,第二组外引脚10延伸至所述第二表面B的另一侧。
第二基板5还具有与第五表面E相对的第六表面F,在一些实施例中,第一组外引脚9与第二组外引脚10还可分别延伸至所述第六表面的两侧。从而可使形成的封装组件既可以通过第二表面B与外部电路相连,又可通过第六表面F 与外部电路相连。
在本发明实施例中,形成第一组外引脚9和第二组外引脚10的具体步骤为:采用掩模裸露出第一组外引脚9和第二组外引脚10所在的外引脚区域,再利用电镀工艺在所述外引脚区域生长铜层或银层,再在所述铜层或银层的表面涂敷锡层。其中,锡层至少要覆盖在铜层或银层延伸至第二表面,从而可使芯片封装组件直接贴在印刷电路板上。
此外根据本申请提供的封装组件的制造方法,还可以实现在第一组内引脚上实现多个芯片层的安装,例如在所述第一组内引脚之上安装的所述芯片层包括第一芯片层和位于第一芯片层之上的第二芯片层,则在将位于所述第一芯片层的第三表面上的电极通过第一连接体与所述第一组内引脚电连接之后,和将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连接之前,所述封装组件的制造方法还包括:
将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接;
去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接。
对于实现两个芯片层的封装组件,在所述第一基板和第二基板之间填充塑封料以形成塑封体的步骤可以包括:
在将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接的步骤和去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接的步骤之间,在所述第一基板和所述中间基板之间填充塑封料,以形成包封所述第一芯片层的第一层塑封体,且使所述第一层塑封体的侧面裸露出所述第一组内引脚和层间组内引脚;
在将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连的步骤之后,在所述第层塑封体层和所述第二基板之间填充塑封料,以形成包封所述第二芯片层的第二层塑封体,且使所述第二层塑封体的侧面裸露出所述第二组内引脚;
所述第一塑封体层和第二塑封体层共同形成所述塑封体层。
进一步,在实现多个芯片层的封装时,所述封装组件的制造方法还包括在所述塑封体侧面形成层间外引脚组,所述层间外引脚组与所述层间内引脚组电连接,且延伸至所述第二表面上或第六表面上。
由上可见,通过将用于与芯片第三表面和第四表面上的电极分别与位于芯片上下方和上方的第一组内引脚、第二组内引脚以及层间内引脚引出,再通过位于塑封体侧面且延伸至封装组件最底面或最顶面的第一组外引脚、第二组外引脚、层间外引脚组与第一组件内引脚、第二组内引脚、层间内引脚组电连接,以将芯片上的电极引到所述封装组件的外部,以用于与外部电路电连接,可有效的减小了芯片的封装面积和厚度,提高了芯片封装的效率,以及通过内引脚和外引脚引出电极的方式可有效减小了芯片封装的寄生电阻,且封装组件的外引脚均裸露在塑封体之外,有利于提高封装组件的散热性。
依照本发明的实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (20)
1.一种芯片封装组件,包括:
位于底层的第一基板,具有第一表面和与所述第一表面相对的第二表面,所述第二表面上设置有第一组内引脚;
位于所述第一组内引脚之上的至少一个芯片层,每一个芯片层均具有第三表面和与第三表面相对的第四表面,位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
位于最顶层的所述第四表面之上且具有第五表面的第二基板,所述第五表面上设置有第二组内引脚,所述第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接,所述第二基板还具有与所述第五表面相对的第六表面;
塑封体,位于所述第一基板与第二基板之间的空隙,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
第一组外引脚、第二组外引脚,均位于所述塑封体的侧面,以分别与所述第一组内引脚、第二组内引脚电连接,并均延伸至所述第二表面上或均延伸至所述第六表面。
2.根据权利要求1所述的芯片封装组件,其特征在于,所述塑封体具有第一侧面和所述第一侧面相对的第二侧面,
所述第一侧面裸露出所述第一组内引脚,所述第二侧面裸露出所述第二组内引脚,
所述第一组外引脚位于所述第一侧面,并延伸至所述第二表面上或第六表面的一侧,所述第二组外引脚位于所述第二侧面的另一侧,并延伸至所述第二表面上或第六表面的另一侧。
3.根据权利要求2所述的芯片封装组件,其特征在于,所述第一连接体为银胶、焊锡中的一种,或者所述第一连接体包括位于所述第一组内引脚上的第一共晶层和位于所述第三表面上的电极上的第二共晶层,且所述第一共晶层与所述第二共晶层形成共晶连接。
4.根据权利要求3所述的芯片封装组件,其特征在于,所述第二连接体包括位于所述第四表面的电极上的第三共晶层和位于所述第二组内引脚上的第四共晶层,且所述第三共晶层与所述第四共晶层形成共晶连接,或者所述第二连接体为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
5.根据权利要求4所述的芯片封装组件,其特征在于,所述第三共晶层为钛镍银合金层,所述第四共晶层为银或锡金属层。
6.根据权利要求4所述的芯片封装组件,其特征在于,所述第一组外引脚与第二组外引脚的一端分别延伸至所述第二表面的两侧,另一端分别延伸至所述第六表面的两侧。
7.根据权利要求6所述的芯片封装组件,其特征在于,所述第一组外引脚和第二组外引脚均包括与所述塑封体相接触的铜层或银层,以及位于铜层或银层上的锡层。
8.根据权利要求2所述的芯片封装组件,其特征在于,所述封装组件包括多个所述芯片层,还包括位于所述芯片层之间的层间内引脚组和位于所述塑封体侧面并延伸至所述第二表面上或所述第六表面上的层间外引脚组,
位于最底层的所述第三表面之上的每一个所述第三表面上的电极均通过第一中间连接体与位于其下方的层间内引脚组电连接,
位于最顶层的所述第四表面之下的每一个所述第四表面上的电极均通过第二中间连接体与位于其上方的层间内引脚组电连接;
所述层间内引脚组裸露于所述塑封体的侧面,并与所述层间外引脚组电连接。
9.根据权利要求8所述的芯片封装组件,其特征在于,所述塑封体包括多个塑封体层,每一个所述塑封体层包封一个所述芯片层。
10.一种芯片封装组件的制造方法,包括:
在第一基板的第一表面上形成图案化的导电层,以作为第一组内引脚,所述第一基板还具有与所述第一表面与相对的第二表面;
在所述第一组内引脚之上安装至少一个芯片层,每一个所述芯片均具有第三表面和与所述第三表面相对的第四表面,将位于最底层的所述第三表面上的电极通过第一连接体与所述第一组内引脚电连接;
将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于最顶层的所述第四表面上的电极电连接;
在所述第一基板和第二基板之间填充塑封料,以形成塑封体,所述塑封体的侧面裸露出所述第一组内引脚和第二组内引脚;
在所述塑封体的侧面上形成与所述第一组内引脚电连接的第一组外引脚、与所述第二组内引脚电连接的第二组外引脚,且使所述第一组外引脚、第二组外引脚均延伸至所述第二表面上或所述第二基板的第六表面上,所述第六表面为与所述第五表面相对的一面。
11.根据权利要求10所述的制造方法,其特征在于,所述塑封体具有第一侧面和所述第一侧面相对的第二侧面,
使所述第一侧面裸露出所述第一组内引脚,所述第二侧面裸露出所述第二组内引脚,
且使所述第一组外引脚位于所述第一侧面,并延伸至所述第二表面上或第六表面的一侧,所述第二组外引脚位于所述第二侧面的另一侧,并延伸至所述第二表面上或第六表面的另一侧。
12.根据权利要求11所述的制造方法,其特征在于,还包括在将所述第二组内引脚通过第二连接体与所述第四表面上的电极电连接之前,在所述第五表面上形成图案化的导电层,以作为第二组内引脚。
13.根据权利要求12所述的制造方法,其特征在于,所述第一连接体为银胶、焊锡中的一种,或者所述第一连接体包括形成于所述第一组内引脚上的第一共晶层和形成于所述第三表面的电极上的第二共晶层,且所述第一共晶层与所述第二共晶层形成共晶连接。
14.根据权利要求13所述的制造方法,其特征在于,所述第二连接体包括形成于所述第四表面的电极上的第三共晶层和形成于所述第二组内引脚上的第四共晶层,且所述第三共晶层与所述第四共晶层形成共晶连接,或者所述第二连接体为位于所述第四表面的电极和所述第二组内引脚之间的导电凸块或者焊块。
15.根据权利要求14所述的制造方法,其特征在于,还包括在所述第四表面的电极上形成钛镍银合金层,以作为所述第三共晶层,在所述第二组内引脚上形成银或锡金属层,以作为所述第四共晶层。
16.根据权利要求15所述的制造方法,其特征在于,使所述第一组外引脚与第二组外引脚的一端分别延伸至所述第二表面的两侧,另一端分别延伸至所述第六表面的两侧。
17.根据权利要求10~16中任意一项所述的制造方法,其特征在于,形成所述第一组外引脚和第二组外引脚的步骤为:采用掩模裸露出所述第一组外引脚和第二组外引脚所在的外引脚区域,再利用电镀工艺在所述外引脚区域生长铜层或银层,再在所述铜层或银层的表面涂敷锡层。
18.根据权利要求10所述的制造方法,其特征在于,在所述第一组内引脚之上安装的所述芯片层包括第一芯片层和位于第一芯片层之上的第二芯片层,
在将位于所述第一芯片层的第三表面上的电极通过第一连接体与所述第一组内引脚电连接之后,和将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连接之前,所述制造方法还包括:
将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接;
去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接。
19.根据权利要求18所述的制造方法,其特征在于,在所述第一基板和第二基板之间填充塑封料,以形成塑封体的步骤包括:
在将位于中间基板上的层间内引脚组通过第二中间连接体与位于所述第一芯片层的第四表面上的电极电连接的步骤和去除所述中间基板,并将所述第二芯片层的第三表面通过第二中间连体与所述层间内引脚组电连接的步骤之间,在所述第一基板和所述中间基板之间填充塑封料,以形成包封所述第一芯片层的第一层塑封体,且使所述第一层塑封体的侧面裸露出所述第一组内引脚和层间组内引脚;
在将位于第二基板的第五表面上的第二组内引脚通过第二连接体与位于所述第二芯片层的第四表面上的电极电连的步骤之后,在所述第一层塑封体和所述第二基板之间填充塑封料,以形成包封所述第二芯片层的第二层塑封体,且使所述第二层塑封体的侧面裸露出所述第二组内引脚;
所述第一层塑封体和第二层塑封体共同形成所述塑封体层。
20.根据权利要求19所述的制造方法,其特征在于,还包括在所述塑封体侧面形成层间外引脚组,所述层间外引脚组与所述层间内引脚组电连接,且延伸至所述第二表面上或第六表面上。
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CN109920787B (zh) * | 2017-12-12 | 2021-05-25 | 中芯国际集成电路制造(北京)有限公司 | 互连结构的设计方法、装置及制造方法 |
CN109390127B (zh) * | 2018-11-12 | 2024-01-30 | 矽力杰半导体技术(杭州)有限公司 | 可支撑式封装器件和封装组件 |
CN211150513U (zh) * | 2019-08-30 | 2020-07-31 | 无锡天芯互联科技有限公司 | 封装体 |
CN113161335B (zh) * | 2021-02-23 | 2022-09-20 | 青岛歌尔智能传感器有限公司 | 心率模组封装结构及其制备方法、以及可穿戴电子设备 |
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