CN102693965B - 封装堆迭结构 - Google Patents

封装堆迭结构 Download PDF

Info

Publication number
CN102693965B
CN102693965B CN201110172866.7A CN201110172866A CN102693965B CN 102693965 B CN102693965 B CN 102693965B CN 201110172866 A CN201110172866 A CN 201110172866A CN 102693965 B CN102693965 B CN 102693965B
Authority
CN
China
Prior art keywords
support plate
chip
electrically connected
those
heating panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110172866.7A
Other languages
English (en)
Other versions
CN102693965A (zh
Inventor
周世文
潘玉堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of CN102693965A publication Critical patent/CN102693965A/zh
Application granted granted Critical
Publication of CN102693965B publication Critical patent/CN102693965B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种封装堆迭结构，包括第一封装结构、多个凸块以及第二封装结构。第一封装结构包括载板、芯片、散热板与封装胶体。芯片配置于载板上，且通过导线与载板电性连接。散热板包括支撑部分与连接部分。散热板的表面上具有线路层。支撑部分位于芯片上方，而连接部分分别位于支撑部分的相对二侧。散热板覆盖芯片与导线，且通过连接部分上的线路层电性连接至载板。封装胶体包覆芯片、导线、部分散热板与部分载板。凸块配置于支撑部分上。第二封装结构配置于第一封装结构上，并通过凸块与第一封装结构电性连接。

Description

封装堆迭结构
技术领域
本发明是有关于一种封装堆迭结构，且特别是有关于一种具有较佳散热及重配置缐路的封装堆迭结构(Package On Package structure)。
背景技术
随着科技日新月异，集成电路(integrated circuits，IC)元件已广泛地应用于我们日常生活当中。一般而言，集成电路的生产主要分为三个阶段：硅晶圆的制造、集成电路的制作及集成电路的封装。在目前的封装结构中，堆迭式封装(package onpackage，POP)为一种常见的封装型态。
如图4所示，传统的堆迭式封装通常是由堆迭的芯片封装结构40、42所构成。芯片封装结构40包括载板400、芯片402、隔离层(spacer)404、重配置线路板(re-layout board)406与封装胶体414。芯片402通过黏着层408固定至载板400上。隔离层404与重配置线路板406依序配置于芯片402上。芯片402通过导线410与载板400电性连接。重配置线路板406通过导线412与载板400电性连接。封装胶体414包覆部分载板400、芯片402、隔离层404、导线410与412以及部分重配置线路板406。芯片封装结构42包括载板416、芯片418与封装胶体420。芯片418通过黏着层422固定至载板416上，且通过导线424与载板416电性连接。封装胶体420包覆部分载板416、芯片418与导线424。此外，芯片封装结构42堆迭于芯片封装结构40上，且通过凸块426与芯片封装结构40的重配置线路板406电性连接。如此一来，芯片封装结构42可经由凸块426、重配置线路板406与导线412而电性连接至载板400。另外，芯片封装结构40还包括凸块428，使得封装堆迭结构40可通过凸块428电性连接至其他外部元件。
然而，在上述的堆迭式封装结构中，由于重配置线路板406配置于芯片402与隔离层404上方，使得导线412必须具有较长的长度，且因此容易造成导线412坍塌(collapse)。此外，上述的堆迭式封装结构亦容易产生散热不佳的问题。
此外，由于重配置线路板406是通过隔离层404设置于芯片402上，以供水平承载重配置线路板406及芯片封装结构42，整体的构件不仅较为繁多，且于充填封装胶体420时，由于胶体流动而易使重配置线路板406倾斜不平，进而影响产品的可靠度。
发明内容
有鉴于此，本发明的目的就是在提供一种封装堆迭结构，其同时具有较佳的散热及重配置缐路。
本发明提出一种封装堆迭结构，其包括第一封装结构、多个凸块以及第二封装结构。第一封装结构包括第一载板、第一芯片、散热板以及第一封装胶体。第一芯片配置于第一载板上，且通过多条第一导线与第一载板电性连接。散热板包括支撑部分与连接部分。散热板的表面上具有线路层。支撑部分位于第一芯片上方，而连接部分分别位于支撑部分的相对二侧。散热板覆盖第一芯片与第一导线，且通过连接部分上的线路层电性连接至第一载板。第一封装胶体包覆第一芯片、第一导线、部分散热板与部分第一载板。凸块配置于支撑部分上。第二封装结构配置于第一封装结构上，并通过凸块与第一封装结构电性连接。
依照本发明实施例所述的封装堆迭结构，上述的散热板例如具有上表面以及与上表面相对的下表面，其中上表面上具有线路层，而凸块与线路层电性连接，且第一封装结构还可以包括多条第二导线，而位于连接部分上的线路层通过第二导线与第一载板电性连接。
依照本发明实施例所述的封装堆迭结构，还可以包括黏着层，其配置于连接部分与第一载板之间。
依照本发明实施例所述的芯片封装结构，上述的黏着层例如为导电材料，而此导电材料选自于焊锡、银胶与异方性导电胶之一。
依照本发明实施例所述的封装堆迭结构，上述的黏着层例如为绝缘材料，而此绝缘材料选自于环氧树脂、两阶段性胶材(B-Stage)、非导电胶(non-conductive paste，NCP)与非导电膜(non-conductive film，NCF)之一。
依照本发明实施例所述的封装堆迭结构，上述的散热板例如由金属核心层与绝缘层构成。绝缘层配置于金属核心层的表面上，且线路层配置于绝缘层上。
依照本发明实施例所述的封装堆迭结构，上述的散热板例如具有上表面以及与上表面相对的下表面，其中下表面上具有线路层，且散热板中具有多个导通孔，而凸块通过导通孔与线路层电性连接，且散热板通过位于连接部分上的线路层与第一载板电性连接。
依照本发明实施例所述的封装堆迭结构，上述的导通孔的外周缘与散热板之间例如配置有绝缘层。
依照本发明实施例所述的封装堆迭结构，上述的第二封装结构包括第二载板、第二芯片以及第二封装胶体。第二载板通过凸块与第一封装结构电性连接。第二芯片配置于第二载板上，且通过多条第二导线与第二载板电性连接。第二封装胶体包覆第二芯片、第二导线与部分第二载板。
依照本发明实施例所述的封装堆迭结构，上述的第一载板例如具有正面、背面以及穿孔。第一芯片配置于第一载板的正面，且第一导线通过穿孔伸出并电性连接于第一载板的背面。
在本发明中，由于散热板具有线路层并经由线路层与载板电性连接，且散热板与芯片电性分离，因此散热板可以取代先前技术中的隔离层与重配置线路板而同时具有稳固承载位于上方的封装结构以及散热的功效，使得本发明的封装堆迭结构能够具有较佳的散热效果。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图，作详细说明如下。
附图说明
图1为依照本发明的第一实施例所绘示的封装堆迭结构的剖面示意图。
图2为依照本发明的第二实施例所绘示的封装堆迭结构的剖面示意图。
图3为依照本发明的第三实施例所绘示的封装堆迭结构的剖面示意图。
图4为传统一种堆迭式封装的剖面示意图。
【主要元件符号说明】
10、20、30：封装堆迭结构
40、42：芯片封装结构
100、100’、100”：第一封装结构
102、102’、202、400、416：载板
102a、202a：正面
102b、202b：背面
103a、103b、104a、203a、203b、204a：接垫
104、204、402、418：芯片
106、106’：散热板
106a：上表面
106b：下表面
107a：支撑部分
107b：连接部分
108、206、414、420：封装胶体
110、118、208、410、412、424：导线
112、120、210、408、422：黏着层
114、300、426、428：凸块
116、116’：线路层
122：导通孔
124：绝缘层
126：穿孔
200：第二封装结构
404：隔离层
406：重配置线路板
具体实施方式
图1为依照本发明的第一实施例所绘示的封装堆迭结构的剖面示意图。请参照图1，封装堆迭结构10包括第一封装结构100、第二封装结构200以及凸块300。第一封装结构100包括载板102、芯片104、散热板106以及封装胶体108。第二封装结构200包括载板202、芯片204以及封装胶体206。
在第一封装结构100中，芯片104配置于载板102的正面102a上。载板102例如为线路板。芯片104具有接垫104a，载板102具有接垫103a，且通过导线110使芯片104的接垫104a与载板102的接垫103a电性连接。在本实施例中，芯片104与载板102之间配置有黏着层112，以将芯片104固定于载板102上。此外，载板102的背面102b具有接垫103b。多个凸块114与接垫103b电性连接，使得封装堆迭结构10可通过凸块114电性连接至其他外部元件。
散热板106包括支撑部分107a与连接部分107b。支撑部分107a位于芯片104上方，而连接部分107b分别位于支撑部分107a的相对二侧，且芯片104与导线110位于这些连接部分107b之间，使得散热板106覆盖芯片104与导线110，且与二者电性隔离。在本实施例中，散热板106具有上表面106a以及与上表面106a相对的下表面106b。此外，散热板106具有位于上表面106a上的线路层116，且位于连接部分107b上的线路层116通过导线118与载板102的接垫103a电性连接。在一实施例中，散热板106例如由金属核心层与配置于金属核心层的表面上的绝缘层构成，而线路层116配置于绝缘层上。
此外，黏着层120配置于连接部分107b与载板102之间。在一实施例中，黏着层120为绝缘材料，其可选自于环氧树脂、两阶段性胶材、非导电胶与非导电膜之一。在另一实施例中，黏着层120也可以是导电材料，其可选自于焊锡、银胶与异方性导电胶之一。
封装胶体108包覆芯片104、导线110、部分载板102与部分散热板106，且封装胶体108暴露出散热板106的支撑部分107a顶面。
与第一封装结构100类似，在第二封装结构200中，芯片204配置于载板202的正面202a上。载板202例如为线路板。芯片204具有接垫204a，载板202具有接垫203a，且通过导线208使芯片204的接垫204a与载板202的接垫203a电性连接。在本实施例中，芯片204与载板202之间配置有黏着层210，以将芯片204固定于载板202上。此外，载板202的背面202b具有接垫203b。封装胶体206包覆芯片204、导线208与部分载板202。
凸块300配置于第一封装结构100中的散热板106的支撑部分107a上。第二封装结构200配置于第一封装结构200上方，并通过凸块300使接垫203b与支撑部分107a上的线路层116电性连接。
在本实施例中，由于散热板106上具有线路层116并通过线路层116使第二封装结构200与载板102电性连接，因此散热板106可以取代先前技术中的隔离层与重配置线路板而同时具有承载第二封装结构200以及散热的功效。此外，由于重配置线路(线路层116)可由散热板106的连接部份107b延伸，明显减少了打线长度，以及避免过长的打线于封装时塌陷、偏移等，使得封装堆迭结构10能够不仅具有较佳的散热功效，同时也具有重配置缐路、以及稳固支撑第二封装结构200与减少打线长度的效果。
图2为依照本发明的第二实施例所绘示的封装堆迭结构的剖面示意图。在图1与图2中，相似的元件将以相似的标号表示。请参照图2，封装堆迭结构20与封装堆迭结构10的差异在于散热板的结构。进一步说，在第一封装结构100’中，散热板106’具有位于下表面106b上的线路层116’，且散热板106’中具有多个导通孔122。导通孔122的材料例如为金、银、铜、铝等导电金属材料，且导通孔122与线路层116’电性连接。导通孔122的外周缘与散热板106’之间配置有绝缘层124。凸块300通过导通孔122与线路层116’电性连接，并通过位于连接部分107b上的线路层116’电性连接至载板102。较佳地，连接部分107b与载板102之间可配置有黏着层120。黏着层120可为导电材料，其可选自于焊锡、银胶与异方性导电胶之一，因此不需要再利用导线118电性连接至载板102。
图3为依照本发明的第三实施例所绘示的封装堆迭结构的剖面示意图。在图1与图3中，相似的元件将以相似的标号表示。请参照图3，封装堆迭结构30与封装堆迭结构10的差异在于载板的结构与芯片的配置方式。进一步说，在第一封装结构100”中，载板102’具有穿孔126。芯片104配置于载板102’的正面102a上。穿孔126暴露出接垫104a，导线110通过穿孔126伸出并电性连接于载板102’的接垫103b。
同样地，图2中所揭示的散热板106’以及散热板106’与第二封装结构200及载板102的接合方式亦可适用于如图3所示的载板102’与芯片104的配置型态，于此不另行说明。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当以权利要求所界定的为准。

Claims (10)

1.一种封装堆迭结构，包括：
一第一封装结构，包括：
一第一载板；
一第一芯片，配置于该第一载板上，且通过多条第一导线与该第一载板电性连接；
一散热板，包括支撑部分与连接部分，且该散热板的表面上具有一线路层，其中该支撑部分位于该第一芯片上方，而该些连接部分分别位于该支撑部分的相对二侧并朝向该第一载板延伸，使该散热板覆盖该第一芯片与该些第一导线，且通过该些连接部分上的该线路层电性连接至该第一载板；以及
一第一封装胶体，包覆该第一芯片、该些第一导线、部分该散热板与部分该第一载板；
多个凸块，配置于该支撑部分上；以及
一第二封装结构，配置于该第一封装结构上，并通过该些凸块与该第一封装结构电性连接。
2.如权利要求1所述的封装堆迭结构，其特征在于，该散热板具有一上表面以及与该上表面相对的一下表面，其中该上表面上具有该线路层，而该些凸块与该线路层电性连接，且该第一封装结构更包括多条第二导线，而位于该些连接部分上的该线路层通过该些第二导线与该第一载板电性连接。
3.如权利要求2所述的封装堆迭结构，其特征在于，更包括一黏着层，配置于该些连接部分与该第一载板之间。
4.如权利要求3所述的封装堆迭结构，其特征在于，该黏着层为一导电材料，该导电材料选自于焊锡、银胶与异方性导电胶之一。
5.如权利要求3所述的封装堆迭结构，其特征在于，该黏着层为一绝缘材料，该绝缘材料选自于环氧树脂、两阶段性胶材、非导电胶与非导电膜之一。
6.如权利要求1所述的封装堆迭结构，其特征在于，该散热板由一金属核心层与一绝缘层构成，该绝缘层配置于该金属核心层的表面上，且该线路层配置于该绝缘层上。
7.如权利要求1所述的封装堆迭结构，其特征在于，该散热板具有一上表面以及与该上表面相对的一下表面，其中该下表面上具有该线路层，且该散热板中具有多个导通孔，而该些凸块通过该些导通孔与该线路层电性连接，且该散热板通过位于该些连接部分上的该线路层与该第一载板电性连接。
8.如权利要求7所述的封装堆迭结构，其特征在于，该些导通孔的外周缘与散热板之间配置有一绝缘层。
9.如权利要求1所述的封装堆迭结构，其特征在于，该第二封装结构，包括：
一第二载板，通过该些凸块与该第一封装结构电性连接；
一第二芯片，配置于该第二载板上，且通过多条第二导线与该第二载板电性连接；以及
一第二封装胶体，包覆该第二芯片、该些第二导线与部分该第二载板。
10.如权利要求1所述的封装堆迭结构，其特征在于，该第一载板具有一正面、一背面以及一穿孔，该第一芯片配置于该第一载板的该正面，且该些第一导线通过该穿孔伸出并电性连接于该第一载板的该背面。
CN201110172866.7A 2011-03-24 2011-06-16 封装堆迭结构 Active CN102693965B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100110160A TWI419270B (zh) 2011-03-24 2011-03-24 封裝堆疊結構
TW100110160 2011-03-24

Publications (2)

Publication Number Publication Date
CN102693965A CN102693965A (zh) 2012-09-26
CN102693965B true CN102693965B (zh) 2014-12-31

Family

ID=46859321

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110172866.7A Active CN102693965B (zh) 2011-03-24 2011-06-16 封装堆迭结构

Country Status (3)

Country Link
US (1) US20120241935A1 (zh)
CN (1) CN102693965B (zh)
TW (1) TWI419270B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
KR102265243B1 (ko) 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20170127567A1 (en) * 2015-10-28 2017-05-04 Stmicroelectronics (Grenoble 2) Sas Electronic device equipped with a heat sink
CN106328620B (zh) * 2016-08-26 2021-03-09 苏州日月新半导体有限公司 集成电路封装体及其制造方法
CN106328611B (zh) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 半导体封装构造及其制造方法
US9953933B1 (en) * 2017-03-30 2018-04-24 Stmicroelectronics, Inc. Flow over wire die attach film and conductive molding compound to provide an electromagnetic interference shield for a semiconductor die
US11222877B2 (en) * 2017-09-29 2022-01-11 Intel Corporation Thermally coupled package-on-package semiconductor packages

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499630A (zh) * 2002-11-04 2004-05-26 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN1674276A (zh) * 2004-03-26 2005-09-28 乾坤科技股份有限公司 多层基板堆栈封装结构
CN1929120A (zh) * 2005-09-08 2007-03-14 南茂科技股份有限公司 堆叠型芯片封装结构、芯片封装体及其制造方法
CN101882606A (zh) * 2009-05-08 2010-11-10 日月光封装测试(上海)有限公司 散热型半导体封装构造及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
TW479337B (en) * 2001-06-04 2002-03-11 Siliconware Precision Industries Co Ltd High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TWI317549B (en) * 2003-03-21 2009-11-21 Advanced Semiconductor Eng Multi-chips stacked package
TWI227552B (en) * 2003-06-17 2005-02-01 Advanced Semiconductor Eng Stacked chip package structure
TWI227553B (en) * 2003-06-30 2005-02-01 Advanced Semiconductor Eng Stacked chip package structure
TWI423401B (zh) * 2005-03-31 2014-01-11 Stats Chippac Ltd 在上側及下側具有暴露基底表面之半導體推疊封裝組件
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
KR101210090B1 (ko) * 2006-03-03 2012-12-07 엘지이노텍 주식회사 금속 코어 인쇄회로기판 및 이를 이용한 발광 다이오드패키징 방법
TWI409924B (zh) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng 半導體封裝體及其製造方法
TWI356482B (en) * 2007-09-20 2012-01-11 Advanced Semiconductor Eng Semiconductor package and manufacturing method the
TW200917431A (en) * 2007-10-05 2009-04-16 Advanced Semiconductor Eng Stacked-type chip package structure and method of fabricating the same
TWI360877B (en) * 2008-02-13 2012-03-21 Walton Advanced Eng Inc Stackable window bga semiconductor package and sta
US9022632B2 (en) * 2008-07-03 2015-05-05 Samsung Electronics Co., Ltd. LED package and a backlight unit unit comprising said LED package
TWI389296B (zh) * 2009-06-25 2013-03-11 Advanced Semiconductor Eng 可堆疊式封裝結構及其製造方法及半導體封裝結構
KR101125296B1 (ko) * 2009-10-21 2012-03-27 엘지이노텍 주식회사 라이트 유닛

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499630A (zh) * 2002-11-04 2004-05-26 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN1674276A (zh) * 2004-03-26 2005-09-28 乾坤科技股份有限公司 多层基板堆栈封装结构
CN1929120A (zh) * 2005-09-08 2007-03-14 南茂科技股份有限公司 堆叠型芯片封装结构、芯片封装体及其制造方法
CN101882606A (zh) * 2009-05-08 2010-11-10 日月光封装测试(上海)有限公司 散热型半导体封装构造及其制造方法

Also Published As

Publication number Publication date
TW201240028A (en) 2012-10-01
CN102693965A (zh) 2012-09-26
US20120241935A1 (en) 2012-09-27
TWI419270B (zh) 2013-12-11

Similar Documents

Publication Publication Date Title
CN102693965B (zh) 封装堆迭结构
US20080174030A1 (en) Multichip stacking structure
TWI481001B (zh) 晶片封裝結構及其製造方法
CN103119711A (zh) 形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构
CN102646663B (zh) 半导体封装件
US20110062581A1 (en) Semiconductor package
US8680686B2 (en) Method and system for thin multi chip stack package with film on wire and copper wire
CN101656248A (zh) 具有凹槽的基板的芯片堆叠封装结构及其封装方法
US20130015589A1 (en) Chip-on-package structure for multiple die stacks
CN107680951A (zh) 一种多芯片叠层的封装结构及其封装方法
CN104701272B (zh) 一种芯片封装组件及其制造方法
US8828796B1 (en) Semiconductor package and method of manufacturing the same
KR101219484B1 (ko) 반도체 칩 모듈 및 이를 갖는 반도체 패키지 및 패키지 모듈
CN103337486B (zh) 半导体封装构造及其制造方法
CN109841605A (zh) 电子封装件及其制法
KR101685068B1 (ko) 시스템 인 패키지 및 이의 제조방법
TW201143018A (en) A three dimensional chip stacking electronic package with bonding wires
TWI409933B (zh) 晶片堆疊封裝結構及其製法
CN104051450B (zh) 半导体封装
TWI604593B (zh) 半導體封裝件及其製法
CN110648991A (zh) 一种用于框架封装芯片的转接板键合结构及其加工方法
CN106469706B (zh) 电子封装件及其制法
CN212182316U (zh) 一种无载体的半导体叠层封装结构
TWI473242B (zh) 晶片封裝結構
CN109256374B (zh) 电子封装件暨基板结构及其制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant