CN103337486B - 半导体封装构造及其制造方法 - Google Patents

半导体封装构造及其制造方法 Download PDF

Info

Publication number
CN103337486B
CN103337486B CN201310214068.5A CN201310214068A CN103337486B CN 103337486 B CN103337486 B CN 103337486B CN 201310214068 A CN201310214068 A CN 201310214068A CN 103337486 B CN103337486 B CN 103337486B
Authority
CN
China
Prior art keywords
layer
protuberance
pin
electrically connected
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310214068.5A
Other languages
English (en)
Other versions
CN103337486A (zh
Inventor
杨俊洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN201310214068.5A priority Critical patent/CN103337486B/zh
Publication of CN103337486A publication Critical patent/CN103337486A/zh
Application granted granted Critical
Publication of CN103337486B publication Critical patent/CN103337486B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

一种半导体封装构造，包含：一重布线层，具有一电源输入端与一电源输出端；至少一芯片，配置于所述重布线层上并具有一有源表面，所述有源表面电性连接所述重布线层，所述芯片的有源表面的一电源输入垫对应连接所述重布线层的电源输出端；以及至少一引脚，配置于所述重布线层上，其中所述引脚具有一连接部、一第一凸部与一第二凸部，所述连接部连接所述第一凸部与所述第二凸部，所述第一凸部对应电性连接所述重布线层的电源输入端，所述第二凸部对应电性连接所述重布线层的电源输出端。上述引脚提供较大接触面积、截面积与延长的传导路径，其在电源通过重布线层输入到芯片时可达到电性缓冲的效果，避免芯片受到损害。

Description

半导体封装构造及其制造方法
技术领域
本发明涉及一种半导体封装构造及其制造方法，特别是涉及一种端口设计具有弹性的半导体封装构造。
背景技术
在基本的半导体封装构造中，芯片会通过打线接合(wire bonding)或倒装芯片接合(flip chip bonding)的方式设置于一基板上，使芯片通过导线(wire)或凸块(bump)电性连接于基板。倒装芯片接合工艺主要是在一芯片的有源表面上的接垫先设置导电用的凸块，再将所述芯片翻转，使其有源表面通过凸块设置于一基板上。根据不同线路密度的需求，芯片有源表面可先设置一重布线层(redistribution layer，RDL)进行线路重新布局，再设置导电凸块，完成芯片与基板之间的电性连接。
上述的重布线层通常设有一电源端口，当芯片设置于基板上时，所述芯片便可通过重布线层与对应的导电凸块接收工作电源。然而，为了符合轻薄短小的封装产品的需求，目前的芯片有源表面所形成的重布线层线路的线径相当细小，且线路密度也较集中，导致导电凸块经过重布线层再到芯片的电流路径相对较短，当外部电源通过此电流路径对芯片供电时，所述芯片可能会在电流过大或是有突波产生的情况下立即受到伤害。
故，有必要提供一种半导体封装构造及其制造方法，以解决现有技术所存在的问题。
发明内容
本发明的主要目的在于提供一种半导体封装构造，其使用特殊形状引脚提供大接触面积、截面积且延长的电流传导路径，在电源通过重布线层输入到芯片时可达到缓冲的效果，避免芯片受到损害。
为达成前述目的，本发明一实施例提供一种半导体封装构造，其包含：一重布线层，具有一电源输入端与一电源输出端；至少一第一芯片，配置于所述重布线层上并具有一有源表面，所述有源表面面向所述重布线层而电性连接所述重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述重布线层的电源输出端；以及至少一引脚，配置于所述重布线层上，其中所述引脚具有一第一凸部、一第二凸部与一连接部，其中所述第一凸部对应电性连接所述重布线层的电源输入端，所述第二凸部对应电性连接所述重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部。
再者，本发明另一实施例提供一种半导体封装构造，其包含：一第一封装体，包含：一第一重布线层，具有一电源输入端与一电源输出端；至少一第一芯片，配置于所述第一重布线层上并具有一有源表面，所述有源表面面向所述第一重布线层而电性连接所述第一重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述第一重布线层的电源输出端；以及至少一第一引脚，配置于所述第一重布线层上，其中所述第一引脚具有一第一凸部、一第二凸部与一连接部，所述第一凸部对应电性连接所述第一重布线层的电源输入端，所述第二凸部对应电性连接所述第一重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部；以及一第二封装体，堆迭于所述第一封装体上并包含：一第二重布线层；至少一第二芯片，配置于所述第二重布线层下并具有一有源表面，所述有源表面朝上背对所述第一芯片并电性连接所述第二重布线层；以及至少一第二引脚，配置于所述第二重布线层下而电性连接所述第二重布线层，并且对应直接接触而电性连接所述第一引脚，使得所述第二重布线层从通过所述第二引脚与第一引脚电性连接至所述第一重布线层。
再者，本发明另一实施例提供一种半导体封装构造，其包含：一第一封装体，包含：一第一重布线层，具有一电源输入端与一电源输出端；至少一第一芯片，配置于所述第一重布线层上并具有一有源表面，所述有源表面面向所述第一重布线层而电性连接所述第一重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述第一重布线层的电源输出端；至少一第一引脚，配置于所述第一重布线层上，其中所述第一引脚具有一第一凸部、一第二凸部与一连接部，所述第一凸部对应电性连接所述第一重布线层的电源输入端，所述第二凸部对应电性连接所述第一重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部；以及一第二重布线层，所述第二重布线层形成于所述第一芯片的一背面与所述第一引脚的顶面，进而电性连接所述第一芯片与所述第一引脚；以及一第二封装体，堆迭于所述第一封装体上并包含：一第三重布线层，电性连接所述第一封装体的第二重布线层；至少一第二芯片，配置于所述第三重布线层上并具有一有源表面，所述有源表面电性连接所述第三重布线层；以及至少一第二引脚；配置于所述第三重布线层上而电性连接所述第三重布线层。
本发明的半导体封装构造通过上述引脚延长芯片与重布线层之间的传导路径，并且大于一般导线线径的接触面积、截面积，其在电源通过重布线层输入到芯片时可达到电性缓冲的效果，避免芯片受到损害。
附图说明
图1是本发明一实施例的半导体封装构造的结构示意图。
图2是本发明另一实施例的半导体封装构造的结构示意图。
图3是本发明又一实施例的半导体封装构造的结构示意图。
图4是本发明又一实施例的半导体封装构造的结构示意图。
图5是本发明又一实施例的半导体封装构造的结构示意图。
图6是本发明又一实施例的半导体封装构造的结构示意图。
图7A～图7G是本发明一实施例的半导体封装构造的制造流程示意图。
具体实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1所示，图1是本发明一实施例的半导体封装构造的结构示意图。在图1中，本发明所揭示的半导体封装构造包含一重布线层1、至少一芯片2以及至少一引脚3。
所述重布线层1包含一图案化的线路层10及一图案化的绝缘层11，所述绝缘层11局部裸露所述线路层10，以定义所述线路层10至少包含有一电源输入端12与一电源输出端13，所述电源输入端12与电源输出端13之间不具有线路连接彼此，亦即电源输入端12与电源输出端13彼此为电性独立。本实施例中，所述重布线层1的一下表面设有数个电性连接所述线路层10的导电连接件100，例如铜凸块或锡球，且与电源输出端13连接的导电连接件100可以浮接，亦即不与任何外部电源电性连接。
所述至少一第一芯片2配置于所述重布线层1上并具有一有源表面20，所述有源表面20面向所述重布线层1而电性连接所述重布线层1的线路层10。所述第一芯片2的有源表面20包含一电源输入垫21，其对应电性连接所述重布线层1的线路层的电源输出端13。
所述至少一引脚3是配置于所述重布线层1上，其中所述引脚3可以是一金属支架，呈U形或是F形而具有一第一凸部30、一第二凸部31及一连接部32，所述第一凸部30对应电性连接所述重布线层1的电源输入端12，所述第二凸部31对应电性连接所述重布线层1的电源输出端13，进而电性连接至所述第一芯片2的有源表面20的电源输入垫21；所述连接部32连接所述第一凸部30与所述第二凸部31。本实施例中，所述引脚3是呈F形，因此所述连接部32进一步具有一尾部33，所述尾部33从所述连接部32与第一凸部30的连接处凸伸出，以进一步提供一弹性的连接端口。
如图1所示，本实施例中，所述半导体封装构造还包含一封装胶材200，用以包覆所述第一芯片2与所述引脚3，其中所述引脚3的一顶面可以裸露于所述封装胶材200的一上表面；且所述尾部33可以裸露于所述封装胶材200的一侧面；另一实施例中，所述引脚的3的顶面亦可被封装胶材所包覆，仅所述尾部33裸露于所述封装胶材200的侧面。
上述引脚3可延长第一芯片2与重布线层1之间的传导路径，其具有大于一般导线线径的接触面积、截面积，当电源通过重布线层1输入到第一芯片2时可达到电性缓冲的效果，避免过大的电流伤害所述第一芯片2，因此，上述引脚3可作为电源输入/输出端口之间的缓冲元件。然而，视实际电路设计需求，上述引脚3也可以作为其他讯号的端口，例如：上述引脚3可作为接地讯号的端口，使第一芯片2的有源表面20通过重布线层1上的所述引脚3接地。由于上述引脚3可局部外露于封装胶材200，例如其连接部32的尾部33，因此所述引脚3可以提供作为所述半导体封装构造的电性测试的端口。再者，由于所述引脚3不只包含第一凸部30、第二凸部31及连接部32而具有较大的导热面积，还局部外露于所述封装胶材200外，因此其亦有助于提供一定程度的散热效果。
请参考图2所示，为了更进一步提高散热效果，所述半导体封装构造还包含一散热片4，其中所述散热片4通过导热材料40贴附于所述第一芯片2的一背面与所述引脚3的顶面，使得所述半导体封装构造具有更好的散热条件。
请参考图3所示，图3是示意所述第一芯片2通过上述引脚3与另一芯片相互连接的一实施例。在图3实施例中，所述半导体封装构造包含两第一芯片2a、2b及至少一第二芯片2c，所述两第一芯片2a、2b有源表面面向所述重布线层1而电性连接所述重布线层1的线路层10，且并排配置于所述重布线层1上；所述第二芯片2c堆迭于所述两第一芯片2a、2b的上方，所述第二芯片2c具有一背对所述重布线层1的有源表面，所述第二芯片2c的有源表面通过导线201电性连接至所述引脚3，因此所述第一芯片2亦可通过上述引脚3与另一芯片或封装体相互连接。
如图3所示，本实施例中，所述半导体封装构造还包含一封装胶材200，用以包覆所述两第一芯片2a、2b、所述第二芯片2c与所述引脚3，其中所述引脚3的连接部32可以裸露于所述封装胶材200的一侧面。
请参考图4所示，图4是示意所述两第一芯片2a、2b通过上述引脚3与另一封装体相互连接的一实施例。在图4实施例中，所述半导体封装构造包含两第一芯片2a、2b及至少一第二封装体2d，所述两第一芯片2a、2b并排配置于所述重布线层1上，所述两第一芯片2a、2b的一背面分别设有电性连接至所述引脚3顶面的一导电层203；所述第二封装体2d堆迭于所述两第一芯片2a、2b的上方，所述第二封装体2d通过数个导电连接件204(例如铜凸块)电性连接并固定于所述两第一芯片2a、2b的背面上的导电层203，进而通过所述导电层203电性连接至所述引脚3。
请参考图5所示，图5是示意所述半导体封装构造包含一第一封装体51与一第二封装体52。所述第一封装体51包含一第一重布线层1a、至少一第一芯片2a以及至少一第一引脚3a；所述第一重布线层1a具有一电源输入端与一电源输出端；所述第一芯片2a配置于所述第一重布线层1a上并具有一有源表面20a，所述有源表面20a朝下面向所述第一重布线层1a而电性连接所述第一重布线层1a，所述第一芯片2a的有源表面20a的一电源输入垫对应连接所述第一重布线层1a的电源输出端；所述第一引脚3a配置于所述第一重布线层1a上，其中所述第一引脚3a具有一第一凸部30a、一第二凸部31a与一连接部32a，所述第一凸部30a对应电性连接所述第一重布线层1a的电源输入端，所述第二凸部31a对应电性连接所述第一重布线层1a的电源输出端；所述连接部32a连接所述第一凸部30a与所述第二凸部31a，视不同需求，所述半导体封装构造亦可与另一同样具有相同引脚的半导体封装构造进行堆迭。
所述第二封装体52堆迭于所述第一封装体51上，并且包含一第二重布线层1b、至少一第二芯片2b以及至少一第二引脚3b；所述第二芯片2b配置于所述第二重布线层1b上并具有一有源表面20b，所述有源表面20b朝上背对所述第一芯片2a而电性连接所述第二重布线层1b；所述第二引脚3b配置于所述第二重布线层1b上而电性连接所述第二重布线层1b并且对应直接接触而电性连接所述第一引脚3a，使得所述第二重布线层1b从通过所述第二引脚3b与第一引脚3a电性连接至所述第一重布线层1a。更详细地，所述第二重布线层1b具有一电源输入端12b与一电源输出端13b；所述第二芯片2b的有源表面20b的一电源输入垫21b对应连接所述第二重布线层1b的电源输出端13b；所述第二引脚3b具有一第三凸部30b与一第四凸部31b，所述第三凸部30b对应电性连接所述第二重布线层1b的电源输入端12b，所述第四凸部31b对应电性连接所述第二重布线层1b的电源输出端13b。
请参考图6所示的实施例，与图5实施例不同之处在于，所述第一封装体51是通过多个导电连接件101与所述第二封装体52进行堆迭。因此，在本实施例中，所述第一封装体51包含一第一重布线层1a、至少一第一芯片2a、至少一第一引脚3a以及一第二重布线层1b；所述第一重布线层1a具有一电源输入端与一电源输出端；所述第一芯片2a配置于所述第一重布线层1a上并具有一有源表面20a，所述有源表面20a朝下面向所述第一重布线层1a而电性连接所述第一重布线层1a，所述第一芯片2a的有源表面20a的一电源输入垫对应连接所述第一重布线层1a的电源输出端；所述第一引脚3a配置于所述第一重布线层1a上，其中所述第一引脚3a具有一第一凸部30a、一第二凸部31a与一连接部32a，所述第一凸部30a对应电性连接所述第一重布线层1a的电源输入端，所述第二凸部31a对应电性连接所述第一重布线层1a的电源输出端；所述连接部32a连接所述第一凸部30a与所述第二凸部31a；所述第二重布线层1b形成于所述第一芯片2a的背面与所述第一引脚3a的顶面，进而电性连接所述第一芯片2a与所述第一引脚3a。
所述第二封装体52包含一第三重布线层1c、至少一第二芯片2b以及至少一第二引脚3b；所述第三重布线层1c电性连接所述第一封装体51的第二重布线层1b，其可以是例如通过数个导电连接件101(例如锡球)电性连接所述第一封装体51的第二重布线层1b；所述第二芯片2b配置于所述第三重布线层1c上并具有一有源表面20b，所述有源表面20b面向所述第一芯片2a并且电性连接第三重布线层1c；所述第二引脚3b配置于所述第三重布线层1c上而电性连接所述第三重布线层1c。其中，第三重布线层1c具有一电源输入端与一电源输出端；所述第二芯片2b的有源表面20b的一电源输入垫对应连接所述第三重布线层1c的电源输出端；所述第二引脚3b具有一第三凸部30b、一第四凸部31b与一连接部32b，所述第三凸部30b对应电性连接所述第三重布线层1c的电源输入端，所述第四凸部31b对应电性连接所述第三重布线层1c的电源输出端；所述连接部32b连接所述第三凸部30b与所述第四凸部31b；由于所述第三重布线层1c通过所述导电连接件101电性连接所述第一封装体51的第二重布线层1b，因此所述第二引脚3b可通过所述导电连接件101对应电性连接所述第一引脚3a。
本发明半导体封装构造详细的制造方法请进一步参考图7A～图7G所示，图7A～图7G是制造如图1所示的半导体封装构造的制造流程示意图。所述制造方法包含步骤如下：
如图7A所示，于一第一载体80上配置数个呈F形的引脚3，所述引脚3可以是一导线架条的一部分，其中每一引脚3具有一第一凸部30、一第二凸部31及一连接部32，所述第一凸部30与第二凸部31是设置在所述第一载体80上。
如图7B所示，接着于所述第一载体80上配置数个第一芯片2，使得每一所述第一芯片2配置于至少两个引脚3之间，且让所述第一芯片2的一有源表面20朝下贴附在所述第一载体80上，使得所述有源表面20与所述引脚3的第一凸部30与第二凸部31共平面。
如图7C所示，接着于所述芯片2与引脚3上形成封装胶材200，以包覆所述芯片2与所述引脚3，并且可选择性通过薄化工艺使所述芯片2的背面与所述引脚3的顶面裸露于所述封装胶材200的表面，亦即使所述引脚3的连接部32上表面裸露于所述封装胶材200的表面。
如图7D所示，接着将所述第一载体80翻转，使所述芯片2的背面与所述引脚3的顶面贴附另一第二载体81，接着再移除所述第一载体80，使得所述芯片2的有源表面20跟所述引脚3的第一凸部30与第二凸部31裸露出，并且形成一金属导电层10’于所述芯片2的有源表面20跟所述引脚3的第一凸部30与第二凸部31。
如图7E所示，对所述金属导电层10’进行曝光显影的图案化工艺，以形成一图案化的线路层10，其中所述线路层10至少包含有一电源输入端与一电源输出端；所述线路层10的电源输入端对应连接所述引脚3的第一凸部30；所述线路层10的电源输出端对应同时连接所述引脚3的第二凸部31与所述第一芯片2的有源表面20的一电源输入垫。
如图7F所示，于所述线路层10上进一步形成图案化的绝缘层11，仅裸露所述线路层10的数个连接端，完成重布线层1的制作；
如图7G所示，接着再于所述线路层10裸露的连接端上对应设置导电连接件100，例如铜凸块或锡球。最后，只要再经过切割工艺，即可大致完成如图1所示的本发明的半导体封装构造的制作。
综上所述，相较于现有的半导体封装构造，本发明的半导体封装构造通过具有特定形状且大于一般导线线径的接触面积、截面积的引脚来延长芯片与重布线层之间的传导路径，可在电源通过重布线层输入到芯片时达到电性缓冲的效果，避免芯片受到损害。视实际电路设计需求，所述引脚还可以作为讯号接地或电性测试的端口，也可使堆迭的芯片构成相互连接，甚至还可以提供一定程度的散热效果。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (11)

1.一种半导体封装构造，其特征在于：其包含：
一重布线层，具有一电源输入端与一电源输出端；
至少一第一芯片，配置于所述重布线层上并具有一有源表面，所述有源表面面向所述重布线层而电性连接所述重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述重布线层的电源输出端；以及
至少一引脚，配置于所述重布线层上，其中所述引脚具有一第一凸部、一第二凸部与一连接部，其中所述第一凸部对应电性连接所述重布线层的电源输入端，所述第二凸部对应电性连接所述重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部。
2.如权利要求1所述的半导体封装构造，其特征在于：所述半导体封装构造还包含一封装胶材，包覆所述第一芯片与所述引脚。
3.如权利要求2所述的半导体封装构造，其特征在于：所述引脚呈U形，其一顶面裸露于所述封装胶材的一上表面。
4.如权利要求2所述的半导体封装构造，其特征在于：所述引脚呈F形，所述连接部具有一尾部从所述连接部与第一凸部的连接处凸伸出；所述引脚的一顶面裸露于所述封装胶材的一上表面；所述尾部裸露于所述封装胶材的一侧面。
5.如权利要求3或4所述的半导体封装构造，其特征在于：所述半导体封装构造还包含一散热片，所述散热片通过导热材料贴附于所述第一芯片的一背面与所述引脚的顶面。
6.如权利要求1所述的半导体封装构造，其特征在于：所述半导体封装构造包含两第一芯片及至少一第二芯片，所述两第一芯片并排配置于所述重布线层上；所述第二芯片堆迭于所述两第一芯片的上方，所述第二芯片具有一背对所述重布线层的有源表面，所述第二芯片的有源表面通过数条导线电性连接至所述引脚。
7.如权利要求1所述的半导体封装构造，其特征在于：所述半导体封装构造包含两第一芯片及至少一第二封装体，所述两第一芯片并排配置于所述重布线层上，所述两第一芯片的一背面分别设有电性连接至所述引脚顶面的一导电层；所述第二封装体堆迭于所述两第一芯片的上方，所述第二封装体通过数个导电连接件电性连接并固定于所述两第一芯片的背面上的导电层，进而通过所述导电层电性连接至所述引脚。
8.一种半导体封装构造，其特征在于：所述半导体封装构造包含：
一第一封装体，包含：
一第一重布线层，具有一电源输入端与一电源输出端；
至少一第一芯片，配置于所述第一重布线层上并具有一有源表面，所述有源表面面向所述第一重布线层而电性连接所述第一重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述第一重布线层的电源输出端；以及
至少一第一引脚，配置于所述第一重布线层上，其中所述第一引脚具有一第一凸部、一第二凸部与一连接部，所述第一凸部对应电性连接所述第一重布线层的电源输入端，所述第二凸部对应电性连接所述第一重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部；以及
一第二封装体，堆迭于所述第一封装体上并包含：
一第二重布线层；
至少一第二芯片，配置于所述第二重布线层下并具有一有源表面，所述有源表面朝上背对所述第一芯片并电性连接所述第二重布线层；以及
至少一第二引脚，配置于所述第二重布线层下而电性连接所述第二重布线层，并且对应直接接触而电性连接所述第一引脚，使得所述第二重布线层从通过所述第二引脚与第一引脚电性连接至所述第一重布线层。
9.如权利要求8所述的半导体封装构造，其特征在于：所述第二重布线层具有一电源输出端与一电源输入端；所述第二芯片的有源表面的一电源输入垫对应连接所述第二重布线层的电源输出端；所述第二引脚具有一第三凸部与一第四凸部，所述第三凸部对应电性连接所述第二重布线层的电源输入端，所述第四凸部对应电性连接所述第二重布线层的电源输出端。
10.一种半导体封装构造，其特征在于：所述半导体封装构造包含：
一第一封装体，包含：
一第一重布线层，具有一电源输入端与一电源输出端；
至少一第一芯片，配置于所述第一重布线层上并具有一有源表面，所述有源表面面向所述第一重布线层而电性连接所述第一重布线层，所述第一芯片的有源表面的一电源输入垫对应连接所述第一重布线层的电源输出端；
至少一第一引脚，配置于所述第一重布线层上，其中所述第一引脚具有一第一凸部、一第二凸部与一连接部，所述第一凸部对应电性连接所述第一重布线层的电源输入端，所述第二凸部对应电性连接所述第一重布线层的电源输出端，所述连接部连接所述第一凸部与所述第二凸部；以及
一第二重布线层，所述第二重布线层形成于所述第一芯片的一背面与所述第一引脚的顶面，进而电性连接所述第一芯片与所述第一引脚；以及
一第二封装体，堆迭于所述第一封装体上并包含：
一第三重布线层，电性连接所述第一封装体的第二重布线层；
至少一第二芯片，配置于所述第三重布线层上并具有一有源表面，所述有源表面电性连接所述第三重布线层；以及
至少一第二引脚；配置于所述第三重布线层上而电性连接所述第三重布线层。
11.如权利要求10所述的半导体封装构造，其特征在于：所述第三重布线层具有一电源输出端与一电源输入端；所述第二芯片的有源表面的一电源输入垫对应连接所述第三重布线层的电源输出端；所述第二引脚具有一第三凸部与一第四凸部，所述第三凸部对应电性连接所述第三重布线层的一电源输入端，所述第四凸部对应电性连接所述第三重布线层的电源输出端；所述第三重布线层通过多个导电连接件电性连接所述第一封装体的第二重布线层，使得所述第二引脚通过所述导电连接件对应电性连接所述第一引脚。
CN201310214068.5A 2013-05-31 2013-05-31 半导体封装构造及其制造方法 Active CN103337486B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310214068.5A CN103337486B (zh) 2013-05-31 2013-05-31 半导体封装构造及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310214068.5A CN103337486B (zh) 2013-05-31 2013-05-31 半导体封装构造及其制造方法

Publications (2)

Publication Number Publication Date
CN103337486A CN103337486A (zh) 2013-10-02
CN103337486B true CN103337486B (zh) 2015-10-28

Family

ID=49245623

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310214068.5A Active CN103337486B (zh) 2013-05-31 2013-05-31 半导体封装构造及其制造方法

Country Status (1)

Country Link
CN (1) CN103337486B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332452B (zh) 2014-08-20 2017-04-19 深圳市汇顶科技股份有限公司 芯片封装模组
CN105550432A (zh) * 2015-12-11 2016-05-04 格科微电子（上海）有限公司 三维集成电路芯片及其电源网络布局方法
CN110729257A (zh) * 2019-03-11 2020-01-24 Pep创新私人有限公司 芯片封装方法及芯片结构
US20230139843A1 (en) * 2021-11-03 2023-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593734A (zh) * 2008-05-27 2009-12-02 联发科技股份有限公司 倒装芯片封装及半导体芯片封装
CN101930971A (zh) * 2009-06-17 2010-12-29 联发科技股份有限公司 多芯片封装结构以及形成多芯片封装结构的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005015036B4 (de) * 2004-07-19 2008-08-28 Qimonda Ag Verfahren zur Montage eines Chips auf einer Unterlage
US8362606B2 (en) * 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
US8716830B2 (en) * 2011-11-23 2014-05-06 Texas Instruments Incorporated Thermally efficient integrated circuit package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593734A (zh) * 2008-05-27 2009-12-02 联发科技股份有限公司 倒装芯片封装及半导体芯片封装
CN101930971A (zh) * 2009-06-17 2010-12-29 联发科技股份有限公司 多芯片封装结构以及形成多芯片封装结构的方法

Also Published As

Publication number Publication date
CN103337486A (zh) 2013-10-02

Similar Documents

Publication Publication Date Title
JP5763121B2 (ja) シリコン貫通ビアのブリッジする相互接続
US20140131854A1 (en) Multi-chip module connection by way of bridging blocks
CN104868004A (zh) 太阳能电池模块
CN101232004A (zh) 芯片堆叠封装结构
TWI481001B (zh) 晶片封裝結構及其製造方法
CN101266932A (zh) 芯片封装结构及其制作方法
CN103337486B (zh) 半导体封装构造及其制造方法
CN102842557A (zh) 一种封装结构及其制造方法
CN102693965B (zh) 封装堆迭结构
CN109801894A (zh) 芯片封装结构和封装方法
CN104350586A (zh) 半导体装置
CN103250246A (zh) 具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统
CN103199075A (zh) 具堆叠芯片的晶圆级半导体封装构造及其制造方法
US20110241206A1 (en) Semiconductor device
US7615487B2 (en) Power delivery package having through wafer vias
CN101131978A (zh) 集成电路封装构造及其使用的多层导线架
WO2014203739A1 (ja) 半導体装置及びその製造方法
CN218730939U (zh) 晶圆组件和层叠封装结构
CN104167403B (zh) 多脚封装的引线框架
CN102412241B (zh) 半导体芯片封装件及其制造方法
US8084847B2 (en) Prefabricated lead frame and bonding method using the same
CN104952736A (zh) 四方平面无引脚的封装结构及其方法
CN219937034U (zh) 半导体封装件
JP2002170920A (ja) フリップチップ装置
US9289846B2 (en) Method for fabricating wire bonding structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant