CN104952736A - 四方平面无引脚的封装结构及其方法 - Google Patents

四方平面无引脚的封装结构及其方法 Download PDF

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CN104952736A
CN104952736A CN201410219198.2A CN201410219198A CN104952736A CN 104952736 A CN104952736 A CN 104952736A CN 201410219198 A CN201410219198 A CN 201410219198A CN 104952736 A CN104952736 A CN 104952736A
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thin layer
hole
crystal grain
conducting circuit
conducting
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杜明德
林静邑
许嘉仁
林圣仁
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Lingsen Precision Industries Ltd
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Abstract

本发明公开了一种四方平面无引脚封装结构的方法，该方法先将传导层形成于薄膜层的表面，并通过电路布局手段使传导层形成多个导通线路，接着将晶粒的各接触垫分别电性连接各导通线路的前端，再通过钻孔手段使薄膜层形成多个通孔，且让各导通线路的末端分别暴露于各通孔中，最后将多个金属凸块分别设置在各通孔，使晶粒的信号通过各导通线路被传导出至薄膜层的底面。据此，本发明不仅可应用于晶圆级芯片尺寸封装(Wafer Level Chip Size Package)，还可应用于胶膜四方平面无引脚(Tape Quad Flat Non-lead Package)的延伸，故能将封装工艺简单化，以降低成本及提升良率。

Description

四方平面无引脚的封装结构及其方法
技术领域
本发明涉及一种封装结构及其方法，特别是一种四方平面无引脚的封装结构及该结构的制作方法。
背景技术
随着科技日新月异，高科技电子工业快速地发表各种包含多功能、更人性化的电子产品，因此，半导体封装在尺寸缩小工艺上也有着快速的发展，例如四方无引脚封装(Quad Flat Non-lead Package，QFN)或是晶圆级芯片尺寸封装(Wafer Level Chip Size Package，WLCSP)，其目的除了减少元件体积外，还能有效降低生产成本，并得到较佳的电性。
而在牵涉到将晶粒直接形成于基底上表面的技术上，目前业界是利用重布(Re-Distribution Layer，RDL)技术应用在四方无引脚封装(QFN)的产品上，首先先以铜箔层(Cu foil layer)做为基底，并运用RDL技术进行重新布线，接着再将其与晶圆(Wafer)做黏合。然而，重布在进行再分布时，重布层被形成于一区域中多个金属接垫上，如此增层将会导致封装尺寸变大以及工艺的困难度增加，进而影响生产良率及成本。
综上所陈，现有的四方无引脚封装结构及方法仍具上述的不足而有待改进。
发明内容
本发明的主要目的在于提供一种四方平面无引脚的封装结构及其方法，其应用于WLCSP及Tape QFN的延伸，据此不仅可将封装工艺简单化，还能降低生产成本及提升良率。
为了达成上述目的，本发明所提供一种四方平面无引脚封装结构的方法，包括下列步骤：
提供一薄膜层；
提供一传导层于该薄膜层的表面；
通过电路布局手段使该传导层形成多个导通线路；
提供一晶粒，具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端；
通过钻孔手段使该薄膜层形成多个通孔，且让各该导通线路的末端分别暴露于各该通孔中；以及
将多个金属凸块分别设置在各该通孔，使该晶粒的信号通过各该导通线路被传导出至该薄膜层的底面。
其中该薄膜层包括在表面形成一胶体的步骤。
其中还包括研磨该晶粒的步骤。
其中该薄膜层的各通孔以激光钻孔的方式所形成。
为了达成上述目的，本发明另提供一种四方平面无引脚封装结构的方法，包括有下列步骤：
提供一薄膜层；
提供一传导层于该薄膜层的上表面；
通过电路布局手段使该传导层形成多个导通线路；
设置一包括有多个晶粒的晶圆于该传导层的上表面，而各该晶粒彼此相邻排列且分别具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端；
通过钻孔手段使该薄膜层形成多个通孔，且各该导通线路的末端分别暴露于各该通孔中；
形成多个金属凸块于各该通孔，使该晶圆的各晶粒的信号通过各该导通线路被传导出至该薄膜层的底面；以及
利用一切割手段沿着各该晶粒间的切割路径进行切割。
其中该薄膜层包括在表面形成一胶体的步骤。
其中还包括研磨该晶粒的步骤。
其中该薄膜层的各通孔以激光钻孔的方式所形成。
为了达成上述目的，本发明所提供一种四方平面无引脚的封装结构，包括有一薄膜层、多个导通线路、一晶粒以及多个金属凸块，其中该薄膜层具有多个通孔，各该导通线路分别铺设于该薄膜层的表面，且各该导通线路的末端分别暴露于各该通孔中，该晶粒具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端，以及各该金属凸块分别位于各该通孔且一端连接于各该导通线路的末端，另一端突出于该薄膜层的底面。
其中该薄膜层朝各该导通线路的表面具有一黏性胶体。
据此，本发明的四方平面无引脚的封装结构不仅应用于WLCSP，还能应用于Tape QFN的延伸，故能将封装工艺简单化，以降低生产成本及提升良率。
附图说明
以下将通过所列举的实施例，配合附图，详细说明本发明的技术内容及特征，其中：
图1为本发明第一优选实施例所提供的四方平面无引脚应用晶圆级芯片尺寸封装的结构的剖面图；
图2a至图2i为该第一优选实施例所提供的四方平面无引脚应用晶圆级芯片尺寸封装的结构及该结构的制作方法的流程图；
图3a至图3g为第二优选实施例所提供的四方平面无引脚应用晶圆级芯片尺寸封装的结构及该结构的制作方法的流程图。
10封装结构
20薄膜层
21通孔      23胶体
30导通层    31导通线路
4晶圆
40晶粒
41接触垫
50金属凸块
P切割路径
具体实施方式
为使所属技术领域的技术人员能进一步了解本发明的构成、特征及其目的，以下特举本发明的若干实施例，并配合附图详细说明如后，同时让本领域技术人员能够具体实施。只不过以下所述的仅是为了说明本发明的技术内容及特征而提供的实施方式，凡为所属技术领域的技术人员，在了解本发明的技术内容及特征之后，以不违背本发明的精神下，所为的种种简单的修饰、替换或构件的省略，皆应属于本发明所要求保护的范围。
为了详细说明本发明的结构、特征及有益效果，兹列举第一优选实施例并配合下列附图说明如后，其中：
请参阅图1，其为本发明的该第一优选实施例所提供的一种四方平面无引脚的封装结构10，其包括有一薄膜层20、多个导通线路30、一晶粒40以及多个金属凸块50。
该薄膜层20具有多个通孔21以及朝各该导通线路30的表面具有一黏性胶体23。
各该导通线路31分别铺设于该薄膜层20的表面，且各该导通线路31的末端分别暴露于各该通孔21中。
该晶粒40具有多个接触垫41，各该接触垫41分别电性连接各该导通线路31的前端。
各该金属凸块50分别位于各该通孔21且一端连接于各该导通线路31的末端，另一端突出于该薄膜层20的底面。
请参阅图2a至图2i，图2a至图2i显示了本发明该第一优选实施例所提供的一种四方平面无引脚封装结构10的方法的工艺流程，包括下列步骤：
步骤A：如图2a所示，首先在该薄膜层20的上表面形成一传导层30，在本实施例中，该传导层30即为铜箔(Cu foil)，其中该薄膜层20还包括预先于该薄膜层20的上表面上形成一胶体23，使该薄膜层20如同胶带般的型态，又因该薄膜层20是如同具有该胶体23的胶带，故该传导层30即可轻易地与该薄膜层20作相互的黏合，据以降低工艺的困难度。
步骤B：如图2b-2c所示，通过电路布局手段使该传导层30形成各该导通线路31，在本实施例中，该电路布局手段是利用重布(Re-Distribution)技术使该传导层30形成预定的导通线路31，即为业界所称的重布层(Re-Distribution Layer，RDL)。
步骤C：如图2d-2e所示，提供一晶粒40，其具有多个接触垫41，各该接触垫41分别电性连接各该导通线路30的前端。
步骤D：如图2f-2g所示，通过钻孔手段使该薄膜层20形成多个通孔21，且让各该导通线路31的末端分别暴露于各该通孔21中，其中该薄膜层20的各通孔21以激光钻孔的方式所形成。
步骤E：如图2h-2i所示，将多个金属凸块50分别设置在各该通孔21，使该晶粒40的信号通过各该导通线路31被传导出至该薄膜层20的底面，并由各该金属凸块50传递出去，在此值得一提的是，各该金属凸块50是以植球(Ball Mounting)方式形成于各该通孔21，据以提升生产的质量及效率。
其中在步骤C与步骤D之间还包括研磨该晶粒40的步骤，使得该晶粒40的厚度符合预设的需求。
为了详细说明本发明的结构、特征及有益效果，下面列举第二优选实施例并配合附图说明如后，其中部分的技术特征已于上述所揭露，故此不再赘述。
请参阅图3a至图3g，其为本发明该第二优选实施例所另提供的一种四方平面无引脚封装结构10′的方法，包括有下列步骤：
步骤A：如图3a所示，在该薄膜层20的上表面形成该传导层30，而实际实施中，该薄膜层20的表面与前述相同，具有胶体21，通过该胶体21使得该传导层30可轻易地黏合于该薄膜层20。
步骤B：如图3b所示，通过电路布局手段使该传导层30形成各该导通线路31。
步骤C：如图3c所示，设置一包括有各该晶粒40的晶圆4于该传导层30的上表面，而各该晶粒40彼此相邻排列且分别具有各该接触垫41，又将各该接触垫41分别电性连接各该导通线路31的前端。
步骤D：如图3d所示，在该晶圆4的上表面进行研磨工艺，使得该晶圆4的厚度符合预设的需求。
步骤E：如图3e所示，通过钻孔手段使该薄膜层20形成多个通孔21，且各该导通线路31的末端分别暴露于各该通孔21中，其中该薄膜层20的各通孔21以激光钻孔的方式所形成。
步骤F：如图3f所示，形成多个金属凸块50于各该通孔21，使该晶圆4的各晶粒40的信号通过各该导通线路31被传导出至该薄膜层20的底面。
步骤G：如图3g所示，利用一切割手段沿着各该晶粒40间的切割路径P进行切割，经切割完成后即会等同上述该第一优选实施例的四方平面无引脚的封装结构10。
综上所陈，本发明的四方平面无引脚的封装结构10、10′及其制作方法不仅可应用于晶圆级芯片尺寸封装(Wafer Level Chip Size Package，WLCSP)，还可应用于胶膜四方平面无引脚(Tape Quad Flat Non-leadPackage，Tape QFN)的延伸，更重要的是，本发明让复杂的封装工艺简单化，据以降低生产成本并改善其良率。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种四方平面无引脚封装结构的方法，包括下列步骤：
提供一薄膜层；
提供一传导层于该薄膜层的表面；
通过电路布局手段使该传导层形成多个导通线路；
提供一晶粒，其具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端；
通过钻孔手段使该薄膜层形成多个通孔，且让各该导通线路的末端分别暴露于各该通孔中；以及
将多个金属凸块分别设置在各该通孔，使该晶粒的信号通过各该导通线路被传导出至该薄膜层的底面。
2.如权利要求1所述的四方平面无引脚封装结构的方法，其特征在于，该薄膜层包括在表面形成一胶体的步骤。
3.如权利要求1所述的四方平面无引脚封装结构的方法，其特征在于，还包括研磨该晶粒的步骤。
4.如权利要求1所述的四方平面无引脚封装结构的方法，其特征在于，该薄膜层的各通孔以激光钻孔的方式所形成。
5.一种四方平面无引脚封装结构的方法，包括下列步骤：
提供一薄膜层；
提供一传导层于该薄膜层的上表面；
通过电路布局手段使该传导层形成多个导通线路；
设置一包括有多个晶粒的晶圆于该传导层的上表面，而各该晶粒彼此相邻排列且分别具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端；
通过钻孔手段使该薄膜层形成多个通孔，且各该导通线路的末端分别暴露于各该通孔中；
形成多个金属凸块于各该通孔，使该晶圆的各晶粒的信号通过各该导通线路被传导出至该薄膜层的底面；以及
利用一切割手段沿着各该晶粒间的切割路径进行切割。
6.如权利要求5所述的四方平面无引脚封装结构的方法，其特征在于，该薄膜层包括在表面形成一胶体的步骤。
7.如权利要求5所述的四方平面无引脚封装结构的方法，其特征在于，还包括研磨该晶粒的步骤。
8.如权利要求5所述的四方平面无引脚封装结构的方法，其特征在于，该薄膜层的各通孔以激光钻孔的方式所形成。
9.一种四方平面无引脚的封装结构，包括：
一薄膜层，具有多个通孔；
多个导通线路，分别铺设于该薄膜层的表面，且各该导通线路的末端分别暴露于各该通孔中；
一晶粒，具有多个接触垫，各该接触垫分别电性连接各该导通线路的前端；以及
多个金属凸块，分别位于各该通孔且一端连接于各该导通线路的末端，另一端突出于该薄膜层的底面。
10.如权利要求9所述的四方平面无引脚的封装结构，其特征在于，该薄膜层朝各该导通线路的表面具有一黏性胶体。
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