CN104600056B - 一种多芯片三维混合封装结构及其制备方法 - Google Patents

一种多芯片三维混合封装结构及其制备方法 Download PDF

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CN104600056B
CN104600056B CN201410843215.XA CN201410843215A CN104600056B CN 104600056 B CN104600056 B CN 104600056B CN 201410843215 A CN201410843215 A CN 201410843215A CN 104600056 B CN104600056 B CN 104600056B
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马利
王虎
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Huatian Technology Xian Co Ltd
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Abstract

本发明公开了一种多芯片三维混合封装结构及其制备方法，主要由下层芯片、芯片凸点、下层塑封体、电路层、粘片胶、上层芯片、焊线、上层塑封体和电极组成；所述下层塑封体包封下层芯片，下层芯片正面朝上，下层芯片带有的芯片凸点露出下层塑封体的表面；下层塑封体表面布线形成有电路层，电路层的走线区域通过粘片胶粘贴有上层芯片，焊线连接上层芯片与电路层，上层塑封体包封上层芯片、电路层和焊线；下层塑封体有通孔，通孔上部是电路层的电极金属，通孔填充有金属，形成电极。本发明工艺简单，封装集成度高，高可靠性，上下塑封体的结构可有效改善产品翘曲，可以大幅度提升了表面贴装良率。

Description

一种多芯片三维混合封装结构及其制备方法
技术领域
本发明涉及集成电路封装领域，具体是一种多芯片三维混合封装结构及其制备方法。
背景技术
随着IC封装集成度越来越高，多芯片混合封装是提高IC封装高密度化的主要途径之一。目前主流的FC+WB及POP等封装，由于塑封料、树脂基板、芯片的热膨胀系数的不匹配，会存在封装体的翘曲及可靠性不足的问题。
发明内容
对于上述现有技术存在的问题，本发明提供了一种多芯片三维混合封装结构及其制备方法，其包括上下两次塑封的塑封体及中间电路层，实现了多芯片三维混合封装，实现工艺简单，封装集成度高，高可靠性，上下塑封体的结构可有效改善产品翘曲，可以大幅度提升了表面贴装良率。
一种多芯片三维混合封装结构，主要由下层芯片、芯片凸点、下层塑封体、电路层、粘片胶、上层芯片、焊线、上层塑封体和电极组成；所述下层塑封体包封下层芯片，下层芯片正面朝上，下层芯片带有的芯片凸点露出下层塑封体的表面；下层塑封体表面布线形成有电路层，电路层的走线区域通过粘片胶粘贴有上层芯片，焊线连接上层芯片与电路层，上层塑封体包封上层芯片、电路层和焊线；下层塑封体有通孔，通孔上部是电路层的电极金属，通孔填充有金属，形成电极。
下层芯片的上表面和芯片凸点之间由下层塑封体包封，芯片凸点通过贴膜塑封的方式露出下层塑封体表面10um。
下层芯片可以是一个或多个相同厚度的芯片。
上层芯片可以是一个或多个正装打线焊接，也可以是倒装热压焊键合或倒装回流焊键合。
一种多芯片三维混合封装结构的制备方法，其按照以下步骤进行：
步骤一：在载具上涂贴片胶层，将带有芯片凸点的下层芯片正面朝上贴于载具上；
载具可以是长方形，也可以是圆形，在结膜后可以加研磨工艺，进一步减小塑封体厚度；载具材质可以为玻璃、有机胶膜(不需要粘片胶)、硅片或金属片(二次塑封后不剔除，切割后可以直接做散热片)。
步骤二：将下层芯片塑封于下层塑封体中，下层芯片的芯片凸点露出下层塑封体表面；
步骤三：在下层塑封体表面布线，可以选用电镀、溅射或直接印刷铜箔等方式形成中间电路层；
步骤四：在电路层的走线区域涂粘片胶，将上层芯片贴于粘片胶上，通过焊线完成上层芯片与电路层的电气连接；
上层芯片也可以是倒装芯片键合。
步骤五：将上层芯片、电路层及焊线包封于上层塑封体中，同时通过研磨或蚀刻方式去除下层载具和贴片胶层；
若载具为金属，也可以作为散热片保留。
步骤六：在下层塑封体的相应位置开通孔，露出中间电路层的电极金属区域；
开孔方式可以为机械开孔或激光开孔。
步骤七：在通孔通过注入金属，引出相应电极；
通过植球、锡膏印刷、电镀、化学镀或溅射铜等方式引出电极。
附图说明
图1为载具贴片图；
图2为一次塑封图；
图3为塑封体表面布线图；
图4为上层芯片键合图；
图5为二次塑封并去除载具图；
图6为激光开孔图；
图7为引出电极图；
1—载具，2—贴片胶层，3—下层芯片，4—芯片凸点(Bump)，5—下层塑封体，6—电路层，7—粘片胶，8—上层芯片，9—焊线，10—上层塑封体，11—通孔，12—电极。
具体实施方式
下面结合附图对本发明做一详细描述。
一种多芯片三维混合封装结构，主要由下层芯片3、芯片凸点4、下层塑封体5、电路层6、粘片胶7、上层芯片8、焊线9、上层塑封体10和电极12组成；所述下层塑封体5包封下层芯片3，下层芯片3正面朝上，下层芯片3带有的芯片凸点4露出下层塑封体5的表面；下层塑封体5表面布线形成有电路层6，电路层6的走线区域通过粘片胶7粘贴有上层芯片8，焊线9连接上层芯片8与电路层6，上层塑封体10包封上层芯片8、电路层6和焊线9；下层塑封体5有通孔11，通孔11上部是电路层6的电极金属，通孔11填充有金属，形成电极12。
下层芯片3的上表面和芯片凸点4之间由下层塑封体5包封，芯片凸点4通过贴膜塑封的方式露出下层塑封体5表面10um。
下层芯片3可以是一个或多个相同厚度的芯片。
上层芯片8可以是一个或多个正装芯片打线焊接，也可以是倒装芯片热压焊键合或倒装回流焊键合。
一种多芯片三维混合封装结构的制备方法，其按照以下步骤进行：
步骤一：在载具1上涂贴片胶层2，将带有芯片凸点4的下层芯片3正面朝上贴于载具1上，如图1所示；
载具1可以是长方形，也可以是圆形，在结膜后可以加研磨工艺，进一步减小塑封体厚度；载具1材质可以为玻璃、有机胶膜(不需要粘片胶)、硅片或金属片(二次塑封后不剔除，切割后可以直接做散热片)。
步骤二：将下层芯片3塑封于下层塑封体5中，下层芯片3的芯片凸点4露出下层塑封体5表面，如图2所示；
步骤三：在下层塑封体5表面布线，可以选用电镀、溅射或直接印刷铜箔等方式形成中间电路层6，如图3所示；
步骤四：在电路层6的走线区域涂粘片胶7，将上层芯片8贴于粘片胶7上，通过焊线9完成上层芯片8与电路层6的电气连接，如图4所示；
上层芯片也可以是倒装芯片键合。
步骤五：将上层芯片8、电路层6及焊线9包封于上层塑封体10中，同时通过研磨或蚀刻方式去除下层载具1和贴片胶层2，如图5所示；
若载具1为金属，也可以作为散热片保留。
步骤六：在下层塑封体5的相应位置开通孔11，露出中间电路层6的电极金属区域，如6所示；
开孔方式可以为机械开孔或激光开孔。
步骤七：在通孔11通过注入金属，引出相应电极12，如图7所示；
通过植球、锡膏印刷、电镀、化学镀或溅射铜等方式引出电极。

Claims (9)

1.一种多芯片三维混合封装结构，其特征在于，主要由下层芯片(3)、芯片凸点(4)、下层塑封体(5)、电路层(6)、粘片胶(7)、上层芯片(8)、焊线(9)、上层塑封体(10)和电极(12)组成；所述下层塑封体(5)包封下层芯片(3)，下层芯片(3)正面朝上，下层芯片(3)带有的芯片凸点(4)露出下层塑封体(5)的表面；下层塑封体(5)表面布线形成有电路层(6)，电路层(6)的走线区域通过粘片胶(7)粘贴有上层芯片(8)，焊线(9)连接上层芯片(8)与电路层(6)，上层塑封体(10)包封上层芯片(8)、电路层(6)和焊线(9)；下层塑封体(5)有通孔(11)，通孔(11)上部是电路层(6)的电极金属，通孔(11)填充有金属，形成电极(12)。
2.根据权利要求1所述的一种多芯片三维混合封装结构，其特征在于，下层芯片(3)的上表面和芯片凸点(4)之间由下层塑封体(5)包封，芯片凸点(4)通过贴膜塑封的方式露出下层塑封体(5)表面10um。
3.根据权利要求1所述的一种多芯片三维混合封装结构，其特征在于，下层芯片(3)是一个或多个相同厚度的芯片。
4.根据权利要求1所述的一种多芯片三维混合封装结构，其特征在于，上层芯片(8)是一个或多个正装芯片打线焊接。
5.一种多芯片三维混合封装结构的制备方法，其特征在于，其按照以下步骤进行：
步骤一：在载具(1)上涂贴片胶层(2)，将带有芯片凸点(4)的下层芯片(3)正面朝上贴于载具(1)上；
步骤二：将下层芯片(3)塑封于下层塑封体(5)中，下层芯片(3)的芯片凸点(4)露出下层塑封体(5)表面；
步骤三：在下层塑封体(5)表面布线，可以选用电镀、溅射或直接印刷铜箔方式形成中间电路层(6)；
步骤四：在电路层(6)的走线区域涂粘片胶(7)，将上层芯片(8)贴于粘片胶(7)上，通过焊线(9)完成上层芯片(8)与电路层(6)的电气连接；
步骤五：将上层芯片(8)、电路层(6)及焊线(9)包封于上层塑封体(10)中，同时通过研磨或蚀刻方式去除下层载具(1)和贴片胶层(2)；
步骤六：在下层塑封体(5)的相应位置开通孔(11)，露出中间电路层(6)的电极金属区域；
步骤七：在通孔(11)通过注入金属，引出相应电极(12)。
6.根据权利要求5所述的一种多芯片三维混合封装结构的制备方法，其特征在于，所述步骤一的载具(1)是长方形或者圆形；载具(1)材质为玻璃、有机胶膜、硅片或金属。
7.根据权利要求5或者6所述的一种多芯片三维混合封装结构的制备方法，其特征在于，所述步骤五的载具(1)若选用金属，载具(1)可作为散热片保留。
8.根据权利要求5所述的一种多芯片三维混合封装结构的制备方法，其特征在于，所述步骤六的开通孔(11)方式为机械开孔或激光开孔。
9.根据权利要求5所述的一种多芯片三维混合封装结构的制备方法，其特征在于，所述步骤七通过植球、锡膏印刷、电镀、化学镀或溅射铜方式引出电极(12)。
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