JP2015198241A - クワッドフラットノーリードパッケージ装置及びその製造方法 - Google Patents
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Abstract
Description
以下に、本発明の装置、特徴及び効果を詳細に説明するため、第1実施形態を挙げると共に添付図面に基づいて説明する。
以下、本発明の装置、特徴及び効果を説明するため、第2実施形態を次の図面に基づいて説明する。一部の技術的特徴は、上述で開示されたため、ここでの詳細な説明は省略する。
20 薄膜層、
21 スルーホール、
23 コロイド、
30 導通層、
31 導体線路、
4 ウェハ、
40 チップ、
41 コンタクトパッド、
50 金属バンプ、
P 切断経路。
Claims (10)
- 薄膜層を提供するステップと、
前記薄膜層の表面に伝導層を提供するステップと、
電子回路配置手段により前記伝導層に複数の導体線路を形成するステップと、
複数のコンタクトパッドを有し、各前記コンタクトパッドを各前記導体線路の先端に電気的に接続するチップを提供するステップと、
ドリル手段により前記薄膜層に複数のスルーホールを形成し、且つ、各前記導体線路の末端を各前記スルーホール内にそれぞれ露出させるステップと、
複数の金属バンプを各前記スルーホールにそれぞれ設け、各前記導体線路を経由して前記チップの信号を前記薄膜層の裏面まで伝達するステップと、
を含むことを特徴とするクワッドフラットノーリードパッケージ装置の製造方法。 - 前記薄膜層の表面にコロイドを形成するステップをさらに含むことを特徴とする請求項1に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 前記チップを研磨するステップを更に含むことを特徴とする請求項1に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 前記薄膜層の各前記スルーホールは、レーザードリル方式で形成されることを特徴とする請求項1に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 薄膜層を提供するステップと、
前記薄膜層の上表面に伝導層を提供するステップと、
電子回路配置手段により前記伝導層に複数の導体線路を形成するステップと、
複数のチップを包括するウェハを前記伝導層の上表面に設け、各前記チップが互いに隣接して配列されており複数のコンタクトパッドを有し、各前記コンタクトパッドが各前記導体線路の先端に電気的に接続するステップと、
ドリル手段により前記薄膜層に複数のスルーホールを形成し、且つ、各前記導体線路の末端が各前記スルーホール内にそれぞれ露出するステップと、
複数の金属バンプを各前記スルーホールに形成し、前記ウェハの各前記チップの信号が各前記導体線路により前記薄膜層の裏面まで伝達されるステップと、
切断手段を利用して各前記チップ間の切断経路に沿って切断するステップと、
を含むことを特徴とするクワッドフラットノーリードパッケージ装置の製造方法。 - 前記薄膜層の表面にコロイドを形成するステップをさらに含むことを特徴とする請求項5に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 前記ウェハを研磨するステップを更に含むことを特徴とする請求項5に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 前記薄膜層の各前記スルーホールは、レーザードリル方式で形成されることを特徴とする請求項5に記載のクワッドフラットノーリードパッケージ装置の製造方法。
- 複数のスルーホールを有する薄膜層と、
前記薄膜層の表面に敷設されており、且つ、末端が前記スルーホール内に露出する複数の導体線路と、
各前記導体線路の先端に電気的に接続する複数のコンタクトパッドを有するチップと、
各前記スルーホールにそれぞれ位置し、且つ、一端が各前記導体線路の末端に接続されており、他端が前記薄膜層の裏面から突出する複数の金属バンプと、
を備えることを特徴とするクワッドフラットノーリードパッケージ装置。 - 前記薄膜層の各前記導体線路に向かう表面は、接着性のあるコロイドを有することを特徴とする請求項9に記載のクワッドフラットノーリードパッケージ装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW103112028A TWI539562B (zh) | 2014-03-31 | 2014-03-31 | Quaternary planar pinless package structure and its manufacturing method |
TW103112028 | 2014-03-31 |
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JP2015198241A true JP2015198241A (ja) | 2015-11-09 |
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JP2014131490A Pending JP2015198241A (ja) | 2014-03-31 | 2014-06-26 | クワッドフラットノーリードパッケージ装置及びその製造方法 |
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US (1) | US20150279796A1 (ja) |
JP (1) | JP2015198241A (ja) |
CN (1) | CN104952736A (ja) |
TW (1) | TWI539562B (ja) |
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US10566309B2 (en) * | 2016-10-04 | 2020-02-18 | Infineon Technologies Ag | Multi-purpose non-linear semiconductor package assembly line |
US11315453B1 (en) * | 2020-11-08 | 2022-04-26 | Innolux Corporation | Tiled display device with a test circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321157A (ja) * | 1994-05-25 | 1995-12-08 | Nec Corp | フレキシブルフィルム及びこれを有する半導体装置 |
JP2000036518A (ja) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | ウェハスケールパッケージ構造およびこれに用いる回路基板 |
JP2001057404A (ja) * | 1999-06-07 | 2001-02-27 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2007150374A (ja) * | 1997-03-21 | 2007-06-14 | Seiko Epson Corp | 半導体装置及びフィルムキャリアテープ並びにこれらの製造方法 |
JP2008066685A (ja) * | 2005-10-17 | 2008-03-21 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5719354A (en) * | 1994-09-16 | 1998-02-17 | Hoechst Celanese Corp. | Monolithic LCP polymer microelectronic wiring modules |
US6812048B1 (en) * | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6867072B1 (en) * | 2004-01-07 | 2005-03-15 | Freescale Semiconductor, Inc. | Flipchip QFN package and method therefor |
JP2008042063A (ja) * | 2006-08-09 | 2008-02-21 | Renesas Technology Corp | 半導体装置 |
US8642385B2 (en) * | 2011-08-09 | 2014-02-04 | Alpha & Omega Semiconductor, Inc. | Wafer level package structure and the fabrication method thereof |
US8524577B2 (en) * | 2011-10-06 | 2013-09-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure |
CN103035545B (zh) * | 2011-10-10 | 2017-10-17 | 马克西姆综合产品公司 | 使用引线框架的晶圆级封装方法 |
CN103681377B (zh) * | 2012-09-01 | 2016-09-14 | 万国半导体股份有限公司 | 带有底部金属基座的半导体器件及其制备方法 |
-
2014
- 2014-03-31 TW TW103112028A patent/TWI539562B/zh active
- 2014-05-22 CN CN201410219198.2A patent/CN104952736A/zh active Pending
- 2014-06-17 US US14/306,905 patent/US20150279796A1/en not_active Abandoned
- 2014-06-26 JP JP2014131490A patent/JP2015198241A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321157A (ja) * | 1994-05-25 | 1995-12-08 | Nec Corp | フレキシブルフィルム及びこれを有する半導体装置 |
JP2007150374A (ja) * | 1997-03-21 | 2007-06-14 | Seiko Epson Corp | 半導体装置及びフィルムキャリアテープ並びにこれらの製造方法 |
JP2000036518A (ja) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | ウェハスケールパッケージ構造およびこれに用いる回路基板 |
JP2001057404A (ja) * | 1999-06-07 | 2001-02-27 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2008066685A (ja) * | 2005-10-17 | 2008-03-21 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
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TW201537699A (zh) | 2015-10-01 |
US20150279796A1 (en) | 2015-10-01 |
TWI539562B (zh) | 2016-06-21 |
CN104952736A (zh) | 2015-09-30 |
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