1358807 ID-200711001 26537twf.doc/n 九、發明說明： 【發明所屬之技術頜域】 本發明是有關於一種封叢製程與封裝結構，且特別是 有關於一種覆晶式四方扁平無引腳型態封裝結構及其封裝 製程。 ^ 【先前技術】 在半導體產業中’積體電路(integrated circuits，IC)的 生產主要可分為三個階段：積體電路的設計(IC design)、 積體電路的製作（IC process)及積體電路的封裝（IC package)。其中，封裝的目的在於，防止晶片受到外界溫 度、濕氣的影響以及雜塵污染，並提供晶片與外部電路之 間電性連接的媒介。 在半導體封裝製程當中，包含有許多種封裝形態。目 前’以四方扁平無引腳((5皿(^以]^〇11-1^(^(1，（^：^)封裝 結構因具有|父短之訊號傳遞路徑’且具有較快之訊號傳遞 速度等優點’因此一直是低腳位構裝型態的主流之—，適 用於高頻傳輸(例如射頻頻帶)之晶片封裝結構之中。 但疋’現行的四方扁平無引腳封裝結構，大多是採用 打線接合(wire bonding)的方式，以使晶片電性連接至承載 器上，而承載器例如為一導線架(lead frame)或一封裝基板 (package substrate)。然而，此種封裝結構形態的缺點在於 衣作成本較局與體積較大。此外，目前一般覆晶形式之 QFN封裝體，晶片焊塾都藉由凸塊而直接與引腳電性接 5 1358807 ID-200711001 26537twf.doc/n QFN封$體之晶#尺寸的大彳、就必定得跟 =、_，架引腳的尺寸大小相同，而無法使則、尺寸晶 本'然而’目前晶片尺寸已經朝向微小化，因 技術中，如何利用小尺寸晶片形成_ 實;：=方扁平無接腳封裝結構更為小型化， 【發明内容】 有鐘於此，本發明的目的就是在提供一種 扇平無引腳型態封裝製程，能夠更為降低封裝體;Ϊ = 可提高製程便利性。 打裝體各度，且 本發明的另-目的是提供一種覆 腳型態封裝結構，能夠藉由介電層金重配平無引 而可應用於具有不同焊塾排列型態之晶片：:層= 能使用更微小尺寸之晶片形成Q=’更因為 封裝成本。 因而得以降低 基於上述目的，本發明提出一種 先，提供-包含多=:=引 然後，在導、絲上形成—介電層，介 η導線架 :上表面與下表面。之後’在介電層上；成 層，而重配置線路層包含多個焊墊 ^置線路 和這些引腳的上表面的導線。接著，形2連，這些焊墊 重配置線路層、介電層與這些㈣，^層，覆蓋</ RTI> <RTIgt; State package structure and its packaging process. ^ [Prior Art] In the semiconductor industry, the production of integrated circuits (ICs) can be divided into three stages: IC design, IC process, and product. The package of the body circuit (IC package). Among them, the purpose of the package is to prevent the wafer from being affected by external temperature, moisture, and dust pollution, and to provide a medium for electrically connecting the wafer to an external circuit. In the semiconductor packaging process, there are many package types. At present, 'four-square flat no-pin ((5) (^^^^11-1^(^(1,(^:^)) package structure has a signal transmission path with a parent short and has a faster signal The advantages of transfer speed, etc., have therefore been the mainstream of low-pin configuration types, and are suitable for high-frequency transmission (such as RF band) chip package structure. However, the current quad flat no-lead package structure, Most of them use wire bonding to electrically connect the chip to the carrier, and the carrier is, for example, a lead frame or a package substrate. However, the package structure The disadvantage of the form is that the cost of the clothing is relatively large and bulky. In addition, the current flip-chip QFN package, the wafer soldering is directly connected to the lead by bumps. 5 1358807 ID-200711001 26537twf.doc /n QFN seals the size of the body. The size of the big 彳, it must be the same as the size of the =, _, the size of the pins, but can not make the size of the crystal size 'however' the current chip size has become miniaturized, because In technology, how to use small size wafers to form _ real;: The flat-paneled pinless package structure is further miniaturized, and the object of the present invention is to provide a fan-flat leadless package process, which can further reduce the package; Improve the convenience of the process. The body is of various degrees, and another object of the present invention is to provide a foot-type package structure, which can be applied to different types of soldering arrangements by the gold layer of the dielectric layer. Wafer:: layer = can use a smaller size of the wafer to form Q = 'more because of the packaging cost. Thus reduced based on the above purpose, the present invention proposes a first, provide - contain more =: = lead then, on the guide, wire Forming a dielectric layer, interposing the η leadframe: the upper surface and the lower surface. Then 'on the dielectric layer; layering, and the reconfigured wiring layer includes a plurality of pads and wires for the upper surface of the pins. Then, in the shape of 2, these pads reconfigure the circuit layer, the dielectric layer and these (4), layer, covering
焊塾的表面。繼之’在防焊層上形成1著i=這I 6 1358807 ID-200711001 26537twf.doc/n 供一晶片，晶片上具有多個凸塊，而且藉 貼附於防㈣上，以使各凸塊分別與其層使晶片 接。 個焊墊電性連 依照本發明的實施例所述之覆晶式 型態封裝製程，更包括形成—封裝频，^ 7無引腳 焊層與介電層，以及填滿晶片與防焊層1㈤片、防 間，且封鄉體裸露出該些引賴下表面。成之空 還可進—步包括，在介電層中形成至施例中， 配置線路相這些料形成於貫通開口 ^ ^ ’而重 中暴露出貫通開口。另外，在貫通開口=^^焊廣 裝膠體。 ^更包括填充有封 型能發㈣實施例所述之覆晶“方扁平益引腳 ^封裝衣程’其中形成重配置線路層的方法例如域鑛 型態：ίΓΛ，灿 電層的材質例如是環氧樹脂。 型態封ί ί程x明Γ中實"I之/晶式四方爲平無引腳 階斷i;性;y是環氧_或具雙 依照本發明的實施例所述之覆 =封;!::其中介電層的厚度小於或等== μ如*例中，封裝膠體包覆這些引腳之侧邊。 别^照本發明的實施例所述之覆晶式四方扁平I引腳 封裝製程，其中形成防焊層的方法例如是塗佈製程。 7 1358807 ID-200711001 26537twf.doc/n 依照本發明的實施例所述之覆晶式四方扁平無引腳 型態封裝製程，其令導線架更包含一框架，而這些引腳與 框架連接且沿框架中心延伸而呈陣列排列或呈單列排列。 基於上述目的，本發明另提出一種覆晶式四方扁平無 引腳型態封裝結構，包括··一介電層、多個引腳、一重西^ 置線路層、一防焊層、一黏著層以及晶片。其中，多個引 腳配置在介電層中，且暴露出其上表面與下表面。重配置 線路層配置在介電層上，而重配置線路層包含多個焊墊以 及^條連接這些焊墊和這些引腳的上表面的導線。防焊層 $蓋重配置線路層、介電層與這些引腳，且防焊層暴露^ 這二4墊的表面。另外，黏著層配置在防焊層上。晶片上 具有多個凸塊，且藉由黏著層以貼附於防焊層上，而各凸 塊分別與其中一個焊墊電性連接。 △依照本發明的實施例所述之覆晶式四方扁平無引腳 型2封裝結構，更包括一封裝膠體，以包覆晶片、防焊層 與’丨電層，以及配置於晶片與防焊層所包圍形成之空間， 且封裝膠體裸露出這些引腳的下表面。在一實施例中，介 =層中具有至少一貫通開口，且在防焊層中暴露出貫通開 而且’在貫通開口内還可更包括配置有封裝膠體。 依照本發明的實施例所述之覆晶式四方扁平無引腳 赢恶封裝結構’其中介電層的表面與這些引腳的上表面切 二且介電層的厚度小於或等於這些引腳的高度。在—實 ^例中’封裝膠體包覆這些引腳之側邊。 依照本發明的實施例所述之覆晶式四方扁平無引聊 8 丄358807 ^-200711〇〇Ι 26537tw£doc/n 型態封裝結構，其中介電層的材質例如是環氧樹脂。 依照本發明的實施例所述之覆晶式四方扁平無引腳 型態封裝結構，更包括一框架，而這些引腳與框架連接且 沿框架中心延伸而呈陣列排列或呈單列排列。 依照本發明的實施例所述之覆晶式四方扁平盔引 型態封裝結構，其中黏著層的材質例如是魏樹脂或罝錐 階特性之熱固性膠材。 一又 本發明可藉由形成有介電層，而在其上方可形成重配 ^線路層，因此可具備有與習知聰製程中縣板之 作用，使晶片可電性連接重配置線路層與弓丨腳。另 = 具有貫通.’其可使魄膠體^均 勻刀佈而填滿所有的空隙，以提高封裳 層具有更佳的結合力。而且，本發明是利用^曰片、介電 程上具有較大的制性，_可降低成本裝製 效地製造封裝舰構。此外，本發暇=也且有 術來代替f知的打線接合技術，因此 ^式封裝技 體積較為料，即可降低财度。錢封紐的 為讓本發明之上述和其他目的、特徵和優點 易懂’下域舉較佳實施例，並g合 ‘，％更I頁 明如下^ 式’作詳細說 【實施方式】 覆 曰a 圖1Α至圖1F為依照本發明之—無 R _例所誇示的 9 1358807 ID-200711001 26537twf.doc/n 式四方扁平無引腳(Quad Flat N〇n_Leaded，qf 製程的剖面示意圖。 〜、、裝 百先，請參照圖1A，本實施例之封裳製程包括 步驟。首先，提供-導線架106，其具有多個引腳1〇2。在 本實施例中’導線架廳還可包括有一框架1G〇 ^線架 106上的這些引腳102可與框架1〇4連接，且沿框架刚 中心延伸而呈陣列排列或者是單列排列(未綠示），其例如The surface of the soldering iron. Following the formation of i on the solder mask, i = 1 6 1358807 ID-200711001 26537twf.doc / n for a wafer, the wafer has a plurality of bumps, and attached to the anti- (four), so that each convex The blocks are individually connected to their layers. The solder pads are electrically connected to the flip-chip type packaging process according to the embodiment of the present invention, and further include forming a package frequency, a solderless layer and a dielectric layer, and filling the wafer and the solder resist layer. 1 (five) film, anti-room, and the sealed home body barely exposed the lower surface. The formation may also include, in the formation of the dielectric layer to the embodiment, the arrangement of the lines of the material formed in the through opening ^^' to expose the through opening. In addition, the colloid is welded at the through opening = ^^. ^ Further includes a method of filling a flip-chip capable of emitting (4) the flip-chip described in the embodiment, wherein the method of forming a reconfigured wiring layer, such as a domain ore type: It is an epoxy resin. The type seal ί x Γ Γ Γ & & I I I I I 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The thickness of the dielectric layer is less than or equal to == μ. For example, the encapsulant covers the sides of the leads. A quad flat I-pack process, wherein the method of forming the solder resist layer is, for example, a coating process. 7 1358807 ID-200711001 26537twf.doc/n A flip-chip quad flat no-lead type according to an embodiment of the invention The package process further comprises a frame, and the pins are connected to the frame and extend along the center of the frame to be arranged in an array or in a single column. Based on the above object, the present invention further provides a flip-chip quad flat no reference. Foot type package structure, including · a dielectric layer, multiple pins, a heavy west ^ a wiring layer, a solder resist layer, an adhesive layer, and a wafer, wherein a plurality of pins are disposed in the dielectric layer and exposed the upper surface and the lower surface thereof. The reconfigured wiring layer is disposed on the dielectric layer, and the heavy The configuration wiring layer includes a plurality of pads and wires connecting the pads and the upper surfaces of the pins. The solder resist layer $ covers the wiring layer, the dielectric layer and the pins, and the solder resist layer is exposed. In addition, the adhesive layer is disposed on the solder resist layer. The wafer has a plurality of bumps, and is adhered to the solder resist layer by an adhesive layer, and each bump is electrically connected to one of the pads. The flip-chip quad flat no-lead 2 package structure according to the embodiment of the present invention further includes an encapsulant for coating the wafer, the solder resist layer and the germanium layer, and the chip. a space formed by the solder mask layer, and the encapsulant exposes the lower surface of the pins. In one embodiment, the dielectric layer has at least one through opening and is exposed in the solder resist layer and Also included in the through opening may be provided with a package The flip-chip quad flat no-lead escaping package structure according to the embodiment of the present invention, wherein the surface of the dielectric layer is cut with the upper surface of the pins and the thickness of the dielectric layer is less than or equal to the reference The height of the foot. In the actual case, the 'package colloid covers the sides of these pins. The flip-chip quad flat is not mentioned in the embodiment of the present invention. 8 丄 358807 ^-200711〇〇Ι 26537tw The doc/n type package structure, wherein the material of the dielectric layer is, for example, an epoxy resin. The flip-chip quad flat no-lead package structure according to the embodiment of the invention further includes a frame, and the The foot is connected to the frame and extends along the center of the frame to be arranged in an array or in a single column. According to the embodiment of the present invention, the flip-chip quad flat-top helmet type package structure, wherein the material of the adhesive layer is, for example, Wei resin or enamel A thermosetting adhesive with tapered characteristics. The invention can be formed by forming a dielectric layer, and a re-wiring circuit layer can be formed thereon, so that it can be provided with the function of the county plate of the Xi Cong process, so that the wafer can be electrically connected to the reconfigurable circuit layer and the bow. Lame. In addition, it has a through. It allows the 魄 colloid to be evenly knurled to fill all the voids to improve the sealing layer. Moreover, the present invention utilizes a cymbal sheet, has a large systemic property in the dielectric, and can be used to manufacture a package hull with reduced cost. In addition, this hairpin = also has the skill to replace the wire bonding technology of the knowing, so the size of the ^ package technology is relatively good, which can reduce the financial value. The above and other objects, features and advantages of the present invention are readily understood by the following description of the preferred embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are schematic cross-sectional views of a quasi-squared leadless (Quad Flat N〇n_Leaded, qf process) in accordance with the present invention without the R_example. 9 1358807 ID-200711001 26537 twf.doc/n. Referring to FIG. 1A, the sealing process of the present embodiment includes the steps. First, a lead frame 106 is provided, which has a plurality of pins 1〇2. In this embodiment, the lead frame hall can also be used. The pins 102 including a frame 1G 线 线 106 can be connected to the frame 1 〇 4 and arranged in an array along the center of the frame or in a single column arrangement (not shown in green), for example
可以排列於框架104的兩側或者是環狀排列於框架1〇 四邊。 ‘線架106的材質例如是銅、銅合金、錄鐵合金等金 屬材料。導線架1G6的形成方法例如是，先提供一金屬材 料層然後對此金屬材料層進行圖案化製程、一次性地完 成微影、蝕刻等步驟而形成所需的圖案。 然後’請參照圖1B，在導線架1〇6上形成一介電層 ⑽。介電層⑽的材質例如是環氧樹脂或其他合適之介電It may be arranged on both sides of the frame 104 or in a ring shape on the four sides of the frame. The material of the wire frame 106 is, for example, a metal material such as copper, a copper alloy, or a ferrous alloy. The lead frame 1G6 is formed by, for example, providing a metal material layer and then patterning the metal material layer, performing lithography, etching, and the like at a time to form a desired pattern. Then, referring to Fig. 1B, a dielectric layer (10) is formed on the lead frame 1〇6. The material of the dielectric layer (10) is, for example, epoxy or other suitable dielectric.
材料。而且，如圖2所示，其綠示圖m之結構沿著線π 的剖面示意圖。此介電層觸則是會暴露出這些引腳1〇2 的亡表面與下表面。介電層刚的厚度為小於這些引腳102 的=度’而介電層108的厚度亦可以是等於這些引腳1〇2 。另外’在一實施例中，於介電層1〇8 +可形成至 丨)貝通開口 U〇，其可例如是位於這些引腳102所圍繞 之區域内。為了便於說明，此實施例的貫通開口 11〇僅繪 示一個。material. Moreover, as shown in FIG. 2, the structure of the green diagram m is a schematic cross-sectional view along the line π. This dielectric layer contact exposes the dead and lower surfaces of these pins 1〇2. The thickness of the dielectric layer is less than the = degree of these pins 102 and the thickness of the dielectric layer 108 can also be equal to the pins 1〇2. Further, in an embodiment, the dielectric layer 1 〇 8 + may be formed to a 贝) beacon opening U 〇 , which may be, for example, located in a region surrounded by the pins 102 . For the convenience of explanation, only one of the through openings 11A of this embodiment is shown.
接著，請參照圖1C ’在介電層108上形成一重配置 1358807 ID-200711001 26537twf.doc/n 線路層116’以改變晶片上對外電性連 配置線路層116包含多個焊塾m以及多條。重 導線114為連接焊墊112與引腳1〇2声、線’而 ^層二的形成方法可例如是利用魏製程。 例二重配置線路層116的材質例如是_衫；^2 金屬材料。在—實施财，重配置線路層U6的這 112可以是形成於貫通開口 11〇的周圍。 此亦不限制重配置線路層116上焊塾工 列方式或分佈位置。 命、深114之排 值得注意的是，本實施例之介電層1〇8及其上 =重配置線路層116,即可具備有與習知封裝製程中的 基板之相同作用，使後續所貼附的晶片可萨由々 層116與導線架106之引腳1〇2電性連接。g 之後’請參照請，形成一防焊層(邊咖如)118， 以，盍住重配置線路層116、介電層舰以及引腳102，且 m暴露出重配置線路層116之焊塾112的表面。 施例中，於防焊層118中亦可暴露出貫通開口 110。 =層118的材質例如是以環氧樹脂，且其形成方法例如 疋利用塗佈製程。 /然後’請參照圖1Ε’在形成防焊層118之後，接著在 ^層118上形成一黏著層120。黏著層120的材質例如 是其他黏著材質。隨後，提供-晶請二3所示U 上之焊塾Π3的分布可例如是周圍分布型(㈣^㈣ 1358807 ID-200711001 26537twf.doc/nNext, referring to FIG. 1C', a reconfiguration 1358807 ID-200711001 26537 twf.doc/n circuit layer 116' is formed on the dielectric layer 108 to change the external electrical connection on the wafer. The wiring layer 116 includes a plurality of solder bumps m and a plurality of strips. . The re-wire 114 is formed by connecting the pads 112 to the pins 1 and 2, and the formation of the layer 2 can be performed, for example, by using a process. For example, the material of the wiring layer 116 is, for example, a metal material. In the implementation, the 112 of the reconfiguration circuit layer U6 may be formed around the through opening 11A. This also does not limit the way or the location of the soldering process on the reconfigured circuit layer 116. It is worth noting that the dielectric layer 1 〇 8 and the upper re-arrangement circuit layer 116 of the present embodiment can have the same function as the substrate in the conventional packaging process, so that the subsequent The attached wafer is electrically connected to the leads 1〇2 of the lead frame 106 by the germanium layer 116. After g 'Please refer to please form a solder mask (edge) 118 to hold the reconfigurable circuit layer 116, the dielectric layer ship and the pin 102, and m expose the solder wire of the reconfiguration circuit layer 116 The surface of 112. In the embodiment, the through opening 110 may also be exposed in the solder resist layer 118. The material of the layer 118 is, for example, an epoxy resin, and its formation method is, for example, a coating process. / Then, please refer to FIG. 1A. After the solder resist layer 118 is formed, an adhesive layer 120 is formed on the layer 118. The material of the adhesive layer 120 is, for example, another adhesive material. Subsequently, the distribution of the solder bumps 3 on the U shown in Fig. 2 can be, for example, a surrounding distribution type ((4)^(4) 1358807 ID-200711001 26537twf.doc/n
或中央分布型(centralpad)等。在本實施例中，則是以繪示 焊墊的分布為中央分布型來做說明。在晶片122之主動表 面上具有多個凸塊124，且每一個凸塊124則是形成於晶 片122的焊塾123之上，這些凸塊材質例如是金、銅、錄、 鋁、錫、鉛或者為上述其一金屬所組合而成之合金。而且， ，再次參照+1E’將晶片122翻覆，讀絲表面朝下，而 晶片122可藉由黏著層120而貼附於防焊層118上，晶片 122上之各凸塊124則分別與重配置線路層116之1 個焊墊122電性連接。 〃 說明的是，在本實施例中，藉由形成於防焊層 上之4耆屬’例如’具有雙階特性之熱固性膠材，可使晶 包含防焊層、重配置線路層、介電層與導線架: 更能夠方便於各製程站別之輸送過程，並容易 ^且有舰製造縣齡構 重配置線路層116,而使本發明可以仙其他卜= 塾排列型態之W。 4，、有不冋知Or central distribution type (centralpad) and the like. In the present embodiment, the description will be made by showing that the distribution of the pads is a central distribution type. A plurality of bumps 124 are formed on the active surface of the wafer 122, and each bump 124 is formed on the solder bumps 123 of the wafer 122. The bump materials are, for example, gold, copper, aluminum, tin, lead. Or an alloy formed by combining one of the above metals. Moreover, the wafer 122 is flipped over with reference to +1E', the surface of the read wire is facing downward, and the wafer 122 can be attached to the solder resist layer 118 by the adhesive layer 120, and the bumps 124 on the wafer 122 are respectively heavy and heavy. One of the pads 122 of the wiring layer 116 is electrically connected. 〃 Illustratively, in the present embodiment, by using a thermosetting adhesive material having a double-order property formed on the solder resist layer, the crystal may include a solder resist layer, a reconfigurable wiring layer, and a dielectric. Layer and lead frame: It is more convenient to facilitate the transportation process of each process station, and it is easy to have a ship-made age-receiving circuit layer 116, so that the present invention can be used for other types. 4, I don’t know
古色… 疋刑用覆晶式封裝技術，代替習知四 方扁+無㈣型態輯的打線接合，因此可進—步 後的體積:料料’即可降低縣财度。,'、 接著，請參照圖1F與圖4，圖4為洛 沿著線11-11，的叫面干土闰芍、，日不圖if之結構 m-44Γ ° 圖。本實施例之封装製程還可自括 防焊層m與介電層10^車=^；直包=曰片⑵、 與防焊層m所包圍形成之填充於晶片⑵ 裸露出導線㈣6之、而且’封裝膠體126 料獅之境些引腳102的下表面，另外封裝膠 12 丄 ID-200711001 26537twf.doc/n 開Π 1;〇: 2入介電層108與防焊層118情形成的 的命隙m，、可使封膠材料能夠均勻分佈而填滿所有 ^隙’而使仔封褒膠體126與晶片122、介電層1〇8且 合適之高分子材料 6 為環氧樹脂或其他 开βίΐί 1F與圖4說明利用上述之封裝製程所 ΐ封梦心Β Ϊ覆晶式四方扁平無引腳型態封裝結構，其 细： '二μ構件的材料及其形成方法已於上述中做詳 、.·田說明，故於此不再贅述。 ^實施例的封裝結構包括介電層1〇 =置=丨6、防厚層118、黏著層12〇以及二2。 圖所不，引腳1〇2例如是與一框架104連接 ==r°6,腳-為卿二 其上ί二4:::ί配二：1::且暴露* 面盥、上μ· ζ所不’介電層108的表 面與延些引腳102的上表面切齊，介麻加广 於或等於引腳1〇2的高度。在Ϊ實二，⑽的厚度小 具有至少-貫通開^例中，介電層⑽中 2外，重配置線路層116配置在介 包含多個焊墊112以及多條導線η: 腳102，且防焊層118暴露出重配Ϊ線路層 12的表面。在一實施例中，在防焊層m中亦暴露出 13 1358807 ID-200711001 26537twf.doc/n 貫通開〇 110。黏著層120配置在防焊層 所使用之黏著層m例如是具有雙階特;性::明 得以使封裳過.程更具便利性。晶片i /、膠材， 且藉由黏著層12G 附於防焊層118上， 分別與重配置線路層m的其中一個焊塾112電=鬼以 此外，本實施例的封裝結構 連接 126,其包覆晶片122、防焊層==有8封= ^可以填充於晶片122與防焊層118所包日 : 另外封裝膠體126還可包覆這些引腳102 =側邊。在-實施例中’封裝踢體126亦可填滿 與防焊層118中所形成的貫通開口 11〇。 a 8 =所述’在本發明之封裝製程與封裝 -介電層’其可與引戦合，且在其上可形缝 败有 而可適用於具有不同形式焊墊之晶片。另外，声1 亦可取代習知封裝製程中的二反？ 置線路層與引腳電性連接。而且，介雷 4 贿歸魏朗衫佈㈣滿所有的 二裝膠體與晶片、介電層具有更佳的結合力， 本發明可以使用更小尺寸晶片，所以更可以降低 雖然本發明已以較佳實施例揭露如上 ，=發明’任何„此技#者，在不脫離本發^:二 内’畲可作些許之更動與獨飾，因此本發明之保護 乾圍备視後附之申請專利範圍所界定者為準。 14 1358807 ID-200711001 26537twf.doc/n 【圖式簡單說明】 圖1A至圖IF為依照本發明之一實施例所繪示的覆晶 式四方爲平無引腳型態封裝製程的剖面示意圖。 圖2為繪示圖1B之結構沿著線Ι-Γ的剖面示意圖。 圖3為繪示本發明之一實施例的晶片的示意圖。 圖4為繪示圖1F之結構沿著線ΙΙ-ΙΓ的剖面示意圖。 【主要元件符號說明】 102 :.引腳 104 :框架 106 :導線架 108 :介電層 110 :貫通開口 112、123 :焊墊 114 :導線 116 :重配置線路層 118 :防焊層 120 :黏著層 122 :晶片 124 :凸塊 126 :封裝膠體 128 :空間 15The patina... The sputum is covered by a flip-chip package technology, which replaces the conventional four-square flat + no (four) type of wire bonding, so the volume after the step: material can reduce the county's fiscal. , ', then, please refer to Fig. 1F and Fig. 4, Fig. 4 is the structure of the dry soil along the line 11-11, and the structure of the day is not m-44Γ °. The packaging process of this embodiment may also include a solder resist layer m and a dielectric layer 10^^; a straight package = a ruthenium sheet (2), and a solder fillet m surrounded by the pad (2) bare exposed wire (4) 6 Moreover, the encapsulation colloid 126 is the lower surface of the pin 102 of the lion, and the encapsulant 12 丄ID-200711001 26537twf.doc/n opening 1; 〇: 2 into the dielectric layer 108 and the solder resist layer 118 The gap m, the sealing material can be evenly distributed to fill all the gaps, and the encapsulant 126 and the wafer 122, the dielectric layer 1 〇 8 and the suitable polymer material 6 are epoxy resin or The other open βίΐί 1F and FIG. 4 illustrate the use of the above-mentioned packaging process to seal the dream core Ϊ flip-chip quad flat no-lead type package structure, which is fine: 'the material of the two μ member and its forming method are in the above Do detailed, .. Tian description, so I will not repeat them here. The package structure of the embodiment includes a dielectric layer 1 置 = set = 丨 6, an anti-thickness layer 118, an adhesive layer 12 〇, and two. If the figure is not, the pin 1〇2 is connected to a frame 104, for example, ==r°6, and the foot-for the second is on the ί2:::ί with two: 1:: and exposed * face 盥, upper μ The surface of the dielectric layer 108 is aligned with the upper surface of the extended pins 102, and the dielectric is broadened or equal to the height of the pins 1〇2. In the case of tamping two, (10) has a small thickness and at least a through-opening, in the dielectric layer (10), the reconfigurable wiring layer 116 is disposed to include a plurality of pads 112 and a plurality of wires η: feet 102, and The solder resist layer 118 exposes the surface of the re-wiring circuit layer 12. In one embodiment, 13 1358807 ID-200711001 26537 twf.doc/n through opening 110 is also exposed in the solder mask m. The adhesive layer m disposed in the solder resist layer 120 has, for example, a double-order property; the property is more convenient. The wafer i /, the adhesive material, is attached to the solder resist layer 118 by the adhesive layer 12G, and is respectively electrically connected to one of the solder pads 112 of the reconfigurable wiring layer m. Further, the package structure of the embodiment is connected 126, The coated wafer 122, the solder mask layer == there are 8 seals = ^ can be filled in the wafer 122 and the solder resist layer 118. In addition, the encapsulant 126 can also cover these pins 102 = side. In the embodiment, the package kicking body 126 may also fill the through opening 11〇 formed in the solder resist layer 118. a 8 = said 'in the encapsulation process and package-dielectric layer of the present invention' which can be combined with the lead and can be formally sewn on the wafer and can be applied to wafers having different types of pads. In addition, the sound 1 can also replace the second counter in the conventional packaging process? The circuit layer is electrically connected to the pin. Moreover, Jielei 4 bribes Weilang shirt (four) full of all two colloids have better bonding force with the wafer and dielectric layer, the invention can use smaller size wafers, so it can be reduced although the invention has been The preferred embodiment discloses the above, if the invention is 'any „this technology#, the invention can be modified and decorated without departing from the present invention. 14 1358807 ID-200711001 26537twf.doc/n [Simplified Schematic Description] FIG. 1A to FIG. 1A are diagrams showing a flip-chip type quad flat no-lead type according to an embodiment of the present invention. 2 is a schematic cross-sectional view of the structure of FIG. 1B along the line Γ-Γ. FIG. 3 is a schematic view of a wafer according to an embodiment of the present invention. FIG. 4 is a schematic view of the wafer of FIG. Schematic diagram of the structure along the line ΙΙ-ΙΓ. [Main component symbol description] 102:. Pin 104: frame 106: lead frame 108: dielectric layer 110: through opening 112, 123: pad 114: wire 116: heavy Configuring the wiring layer 118: solder resist layer 120: adhesive layer 122: wafer 12 4: Bump 126 : Encapsulant 128 : Space 15