CN110648991A - 一种用于框架封装芯片的转接板键合结构及其加工方法 - Google Patents

一种用于框架封装芯片的转接板键合结构及其加工方法 Download PDF

Info

Publication number
CN110648991A
CN110648991A CN201910943260.5A CN201910943260A CN110648991A CN 110648991 A CN110648991 A CN 110648991A CN 201910943260 A CN201910943260 A CN 201910943260A CN 110648991 A CN110648991 A CN 110648991A
Authority
CN
China
Prior art keywords
chip
frame
adapter plate
chips
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910943260.5A
Other languages
English (en)
Other versions
CN110648991B (zh
Inventor
张婕
马晓建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Nanjing Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN201910943260.5A priority Critical patent/CN110648991B/zh
Publication of CN110648991A publication Critical patent/CN110648991A/zh
Application granted granted Critical
Publication of CN110648991B publication Critical patent/CN110648991B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • H01L2224/48106Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

一种用于框架封装芯片的转接板键合结构及其加工方法,转接板键合结构包括设置在塑封体当中的框架、芯片、转接板和键合线;芯片固定在框架上,芯片上贴装有转接板,转接板上依据芯片的焊盘位置和芯片尺寸设置基板走线,键合线连接在芯片和转接板之间以及转接板和框架之间,通过键合线及基板走线实现框架、转接板、芯片的电性连接。芯片可以是若干个,多个芯片安装时由下至上依次分层叠加固定在框架上,转接板贴装在最上层芯片上。通过本发明使本身超封装制程的打线工艺变成常规的Wire Bond键合工艺就能够实现,同时缩小了封装尺寸,并使产品可以继续沿用框架类封装,降低了产品的可靠性失效风险。

Description

一种用于框架封装芯片的转接板键合结构及其加工方法
技术领域
本发明属于芯片封装领域,涉及一种用于框架封装芯片的转接板键合结构及其加工方法。
背景技术
对于LeadFrame封装芯片,框架是模塑封装的骨架,一方面起到了封装器件的支撑作用,另一方面也提供了芯片到线路板的电及热通道。框架主要由两部分组成:芯片焊盘(die paddle)和引脚(lead finger),其中芯片焊盘在封装过程中为芯片提供机械支撑,引脚则是连接芯片到封装结构外的电学通路。每一个引脚末端都与芯片上的一个焊盘通过引线相连,该端称为内引脚,引脚的另一端就是所谓的管脚,用于提供与基板或PC板的连接。传统的LeadFrame封装产品中,经常由于芯片尺寸过大或芯片焊盘位置设置不合理,而且框架类本身走线能力有限,经常会出现无法通过正常封装工艺打线键合,因此不得不更改为基板类封装或者增大封装尺寸。针对这一问题,亟需设计一种新的结构来使产品能够继续沿用框架类封装。
发明内容
本发明的目的在于针对现有技术中框架封装芯片某些场合打线键合困难的问题,提供一种用于框架封装芯片的转接板键合结构及其加工方法,降低打线过程风险,缩减封装尺寸。
为了实现上述目的,本发明有如下的技术方案:
一种用于框架封装芯片的转接板键合结构,包括设置在塑封体当中的框架、芯片、转接板和键合线;所述的芯片固定在框架上,芯片上贴装有转接板,转接板上依据芯片的焊盘位置和芯片尺寸设置基板走线,键合线连接在芯片和转接板之间以及转接板和框架之间,通过键合线及基板走线实现框架、转接板、芯片的电性连接。
作为优选,本发明转接板键合结构的一种实施例中,所述的芯片可以为若干个,并由下至上依次分层叠加固定在框架上,转接板贴装在最上层芯片上。
作为优选,本发明转接板键合结构的一种实施例中,所述相邻两层的芯片之间以及芯片与转接板之间呈梯度倾斜布置。
作为优选,本发明转接板键合结构的一种实施例中,所述芯片与框架之间、相邻两层的芯片之间以及芯片与转接板之间由粘合层贴装。
作为优选,本发明转接板键合结构的一种实施例中,粘合层为DAF固型膜或胶水层。
作为优选,本发明转接板键合结构的一种实施例中,所述的基板走线用Wire Bond键合工艺在转接板上焊接成型。
本发明还提供了所述转接板键合结构的加工方法,包括以下步骤:
——制作带有基板走线的转接板,基板走线根据依据芯片的焊盘位置和芯片尺寸设置,通过基板走线能够将芯片的两侧实现连接;
——将芯片安装在框架上,再将转接板贴装在芯片上;
——取键合线分别连接在芯片和转接板之间以及转接板和框架之间,通过键合线及基板走线实现框架、转接板、芯片的电性连接;
——采用塑封体将框架、芯片、转接板和键合线进行封装。
相较于现有技术,本发明转接板键合结构具有如下的有益效果:针对本身走线能力有限的框架类封装芯片,通过芯片上贴装转接板,转接板上依据芯片的焊盘位置和芯片尺寸设置基板走线,键合线经过基板走线即能够实现芯片与两侧框架的电性连接,通过本发明使本身超封装制程的打线工艺变成常规的Wire Bond键合工艺就能够实现,同时缩小了封装尺寸,并使产品可以继续沿用框架类封装,降低了产品的可靠性失效风险。
进一步的,本发明的芯片可以是一个或者多个,当需要多个芯片时,使其由下至上依次分层叠加,转接板贴装在最上层芯片上即可。相邻两层的芯片之间以及芯片与转接板之间呈梯度倾斜布置,预留了键合线的连接位置,便于进行连接安装。
相较于现有技术,本发明转接板键合结构的加工方法,操作简单,实施容易,能够在继续沿用框架类封装的基础上,实现芯片与两侧框架的电性连接,应对芯片尺寸过大或芯片焊盘位置设置不合理的问题,降低本身走线能力有限的框架类封装芯可靠性失效风险。
附图说明
为了更清楚地说明本发明的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1本发明转接板的侧视示意图;
图2本发明两层芯片堆叠的结构示意图;
图3本发明转接板贴装的结构示意图;
图4本发明键合线的连接示意图;
图5本发明整体装配成型示意图;
附图中:1-框架;2-粘合层;3-芯片;4-键合线;5-转接板;6-基板走线;7-塑封体。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明的一部分实施例,而不是全部的实施例。
基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下,所获得的所有其他实施例,也都属于本发明保护的范围。
参见图5,本发明在结构上包括设置在塑封体7当中的框架1、芯片3、转接板5和键合线4,芯片3固定在框架1上,芯片3可以是若干个,多个芯片3组合时由下至上依次分层叠加固定在框架1上,最上层的芯片3上贴装有转接板5。转接板5上依据芯片3的焊盘位置和芯片尺寸设置基板走线6,键合线4连接在芯片3和转接板5之间以及转接板5和框架1之间,通过键合线4及基板走线6实现框架1、转接板5、芯片3的电性连接。相邻两层的芯片3之间以及芯片3与转接板5之间呈梯度倾斜布置,预留了键合线4的连接位置。
芯片3与框架1之间、相邻两层芯片3之间、芯片3与转接板5之间由粘合层2贴装。粘合层2可以采用DAF固型膜或胶水层。基板走线6为转接板5上的焊线。
参见图1-5,本发明所述转接板键合结构的加工方法,包括以下步骤:
——制作带有基板走线6的转接板5,基板走线6根据依据芯片3的焊盘位置和芯片尺寸设置,通过基板走线6能够将芯片3的两侧连接;
——将芯片3安装在框架1上,再将转接板5贴装在芯片3上;
——取键合线4分别连接在芯片3和转接板5之间以及转接板5和框架1之间,通过键合线4及基板走线6实现框架1、转接板5、芯片3的电性连接;
——采用塑封体7将框架1、芯片3、转接板5和键合线4整体进行封装。
本发明通过增加转接板结构,降低了Wire Bond键合工艺打线过程的风险,进而,缩减了封装尺寸,提高了封装成品的可靠性等级,使现有封装工艺不能实现的封装产品通过增加转接板变为常规打线工艺就能实现,无需更改封装类型或者增大封装尺寸,降低成本。
以上所述仅仅是本发明的较佳实施例,并不用以对本发明的技术方案进行任何限制,本领域技术人员应当理解的是,在不脱离本发明精神和原则的前提下,该技术方案还可以进行若干简单的修改和替换,这些修改和替换也均属于本发明权利要求书确定的保护范围之内。

Claims (7)

1.一种用于框架封装芯片的转接板键合结构,其特征在于:包括设置在塑封体(7)当中的框架(1)、芯片(3)、转接板(5)和键合线(4);所述的芯片(3)固定在框架(1)上,芯片(3)上贴装有转接板(5),转接板(5)上依据芯片(3)的焊盘位置和芯片尺寸设置基板走线(6),键合线(4)连接在芯片(3)和转接板(5)之间以及转接板(5)和框架(1)之间,通过键合线(4)及基板走线(6)实现框架(1)、转接板(5)、芯片(3)的电性连接。
2.根据权利要求1所述用于框架封装芯片的转接板键合结构,其特征在于:芯片(3)为若干个,由下至上依次分层叠加固定在框架(1)上,转接板(5)贴装在最上层芯片(3)上。
3.根据权利要求2所述用于框架封装芯片的转接板键合结构,其特征在于:所述相邻两层的芯片(3)之间以及芯片(3)与转接板(5)之间呈梯度倾斜布置。
4.根据权利要求2所述用于框架封装芯片的转接板键合结构,其特征在于:芯片(3)与框架(1)之间、相邻两层芯片(3)之间、芯片(3)与转接板(5)之间由粘合层(2)贴装。
5.根据权利要求3所述用于框架封装芯片的转接板键合结构,其特征在于:
所述的粘合层(2)采用DAF固型膜或胶水层。
6.根据权利要求1所述用于框架封装芯片的转接板键合结构,其特征在于:所述的基板走线(6)采用Wire Bond键合工艺在转接板(5)上焊接成型。
7.一种如权利要求1-6中任意一项所述用于框架封装芯片的转接板键合结构的加工方法,其特征在于,包括以下步骤:
——制作带有基板走线(6)的转接板(5),基板走线(6)根据依据芯片(3)的焊盘位置和芯片尺寸设置,通过基板走线(6)能够将芯片(3)的两侧连接;
——将芯片(3)安装在框架(1)上,再将转接板(5)贴装在芯片(3)上;
——取键合线(4)分别连接在芯片(3)和转接板(5)之间以及转接板(5)和框架(1)之间,通过键合线(4)及基板走线(6)实现框架(1)、转接板(5)、芯片(3)的电性连接;
——采用塑封体(7)将框架(1)、芯片(3)、转接板(5)和键合线(4)进行封装。
CN201910943260.5A 2019-09-30 2019-09-30 一种用于框架封装芯片的转接板键合结构及其加工方法 Active CN110648991B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910943260.5A CN110648991B (zh) 2019-09-30 2019-09-30 一种用于框架封装芯片的转接板键合结构及其加工方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910943260.5A CN110648991B (zh) 2019-09-30 2019-09-30 一种用于框架封装芯片的转接板键合结构及其加工方法

Publications (2)

Publication Number Publication Date
CN110648991A true CN110648991A (zh) 2020-01-03
CN110648991B CN110648991B (zh) 2021-08-31

Family

ID=69012107

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910943260.5A Active CN110648991B (zh) 2019-09-30 2019-09-30 一种用于框架封装芯片的转接板键合结构及其加工方法

Country Status (1)

Country Link
CN (1) CN110648991B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112989744A (zh) * 2021-02-08 2021-06-18 泰凌微电子(上海)股份有限公司 一种半导体芯片的封装设计方法以及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110049693A1 (en) * 2009-09-02 2011-03-03 Renesas Electronics Corporation Semiconductor device, method of manufacturing semiconductor device, and lead frame thereof
CN102376670A (zh) * 2010-08-12 2012-03-14 三星电子株式会社 半导体封装件
CN102769009A (zh) * 2011-05-04 2012-11-07 三星半导体(中国)研究开发有限公司 半导体封装件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110049693A1 (en) * 2009-09-02 2011-03-03 Renesas Electronics Corporation Semiconductor device, method of manufacturing semiconductor device, and lead frame thereof
CN102376670A (zh) * 2010-08-12 2012-03-14 三星电子株式会社 半导体封装件
CN102769009A (zh) * 2011-05-04 2012-11-07 三星半导体(中国)研究开发有限公司 半导体封装件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112989744A (zh) * 2021-02-08 2021-06-18 泰凌微电子(上海)股份有限公司 一种半导体芯片的封装设计方法以及装置
CN112989744B (zh) * 2021-02-08 2023-11-17 泰凌微电子(上海)股份有限公司 一种半导体芯片的封装设计方法以及装置

Also Published As

Publication number Publication date
CN110648991B (zh) 2021-08-31

Similar Documents

Publication Publication Date Title
JP4195804B2 (ja) デュアルダイパッケージ
JP4489100B2 (ja) 半導体パッケージ
US20080150100A1 (en) Ic package encapsulating a chip under asymmetric single-side leads
JP2009099697A (ja) 半導体装置及びその製造方法
KR101563630B1 (ko) 반도체 패키지
CN206282838U (zh) 无源器件与有源器件的集成封装结构
TW201312723A (zh) 晶片封裝結構及其製造方法
TWI406376B (zh) 晶片封裝構造
CN102693965B (zh) 封装堆迭结构
JP2005209882A (ja) 半導体パッケージ及び半導体装置
CN110648991B (zh) 一种用于框架封装芯片的转接板键合结构及其加工方法
US8143707B2 (en) Semiconductor device
KR100788341B1 (ko) 칩 적층형 반도체 패키지
CN208460754U (zh) 一种多芯片pqfn封装结构
CN102751203A (zh) 半导体封装结构及其制作方法
US20070267756A1 (en) Integrated circuit package and multi-layer lead frame utilized
KR100447894B1 (ko) 듀얼 적층패키지 및 그 제조방법
CN201732781U (zh) 一种引线框架
KR20080067891A (ko) 멀티 칩 패키지
CN110600447A (zh) 一种新型引线框架结构及封装结构
CN218160365U (zh) 封装结构
CN217983333U (zh) 一种贴片式so23c半导体分立器件的封装结构
CN212182316U (zh) 一种无载体的半导体叠层封装结构
CN209199908U (zh) 一种倒装芯片封装结构
CN219958992U (zh) 混合互联的qfn封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20210802

Address after: 211805 No. 16, Dingxiang Road, Qiaolin street, Pukou District, Nanjing, Jiangsu Province

Applicant after: Huatian Science and Technology (Nanjing) Co.,Ltd.

Address before: 710018 No. 105 Fengcheng Five Road, Xi'an Economic and Technological Development Zone, Xi'an City, Shaanxi Province

Applicant before: HUATIAN TECHNOLOGY (XI'AN) Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant