CN104779220A - 一种芯片封装结构及其制造方法 - Google Patents

一种芯片封装结构及其制造方法 Download PDF

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Publication number
CN104779220A
CN104779220A CN201510137676.XA CN201510137676A CN104779220A CN 104779220 A CN104779220 A CN 104779220A CN 201510137676 A CN201510137676 A CN 201510137676A CN 104779220 A CN104779220 A CN 104779220A
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pin
chip
electrically connected
plastic
carrier
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CN201510137676.XA
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Inventor
谭小春
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Hefei silicon microelectronics technology Co., Ltd.
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Hangzhou Silergy Semiconductor Technology Ltd
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Priority to CN201510137676.XA priority Critical patent/CN104779220A/zh
Publication of CN104779220A publication Critical patent/CN104779220A/zh
Priority to TW105101561A priority patent/TWI697086B/zh
Priority to US15/051,432 priority patent/US9780081B2/en
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Abstract

本申请提供一种芯片封装结构及其制造方法，在所述芯片封装结构包括第一引脚、位于第一引脚之上的第一导电柱，位于第二导电柱之上且与所述第二导电柱以及芯片有源面上的第一电连接体均电连接的第二引脚，所述芯片有源面上的电极焊盘通过由第一电连接体、第二引脚、第一导电柱以及第一引脚构成导电路径引出，最终由第一引脚实现芯片与外部电路之间的电连接。这种引出电极的方式，可有效的降低封装电阻，且无需采用焊料焊接，可避免虚焊现象，提高芯片封装的可靠性以及有效的降低了芯片的封装厚度。

Description

一种芯片封装结构及其制造方法
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片的封装结构及其制造方法。
背景技术
在传统的芯片正装封装结构中，芯片的非有源面粘附于引线框架的芯片承载盘上，芯片的有源面上的电极通过金属引线电连接到承载盘周围的引脚上，从而将芯片有源面上的电极引出与外部电路连接。
这种传统的引线键合的封装方式，虽然工艺较成熟，产量大，但是由于其需要用细长的金属引线来引出芯片表面上的电极，必然会导致较大封装电阻，此外，金属引线与芯片的焊盘之间容易出现虚焊的现象，不利于保障芯片封装的可靠性。近年来，随着电子器件朝着薄型化的趋势发展，传统的引线键合封装方式，由于封装厚度较厚，已经越来越不能满足人们的要求。
发明内容
有鉴于此，本发明的目的是提供了一种芯片封装结构及其制造方法，以提高封装可靠性、降低封装电阻以及减小封装厚度。
一种芯片封装结构，包括：
引线框架，具有承载盘和位于所述承载盘周围的第一引脚；
位于所述第一引脚上且与所述第一引脚电连接的第一导电柱；
第一芯片，具有有源面和与所述有源面相对的背表面，所述背表面贴装于所述承载盘上，所述有源面的电极焊盘上设置有第一电连接体；
第一塑封体，用于包封所述第一芯片和囊封所述引线框架，且具有第一表面和与所述第一表面相对的第二表面，其中，所述第一表面裸露出所述第一导电柱和所述第一电连接体，所述第二表面裸露出所述第一引脚，
位于所述第一表面上的第二引脚，用于将所述第一电连接体和所述第一导电柱电连接。
优选的，所述芯片封装结构，还包括用于包封所述第二引脚的第二塑封体。
优选的，所述第二表面上还裸露出所述承载盘。
优选的，所述背表面具有背面电极焊盘，所述背面电极焊盘通过焊料或导电胶贴装于所述承载盘上。
优选的，所述承载盘与一个所述第一引脚电连接。
优选的，所述第一引脚、第一导电柱、第一电连接体、第二引脚的形成材料相同。
优选的，所述引线框架还具有位于所述承载盘周围的第三引脚，所述芯片封装结构还包括：
位于所述第三引脚上且与所述第三引脚电连接的第二导电柱，所述第一表面还裸露出所述第二导电柱；
位于所述第一表面上且与所述第二导电柱电连接的第四引脚；
位于所述第一表面上方，且有源面上的电极焊盘通过第二电连接体电连接到所述第四引脚上的第二芯片；
所述第二塑封体还用于包括所述第四引脚、第二芯片；
所述第二表面上还裸露出所述第三引脚。
优选的，所述第二芯片的有源面上的电极焊盘通过第二电连接体与所述第二引脚电连接。
优选的，所述第二电连接体为导电凸块、焊料、金属引线中的一种。
一种芯片封装结构的制造方法，包括：
提供具有承载盘和第一引脚的引线框架，所述第一引脚位于所述承载盘周围，在所述第一引脚上形成与所述第一引脚电连接的第一导电柱；
将第一芯片的背表面贴装于所述承载盘上，所述背表面为与所述第一芯片的有源面相对的一面，所述有源面的电极焊盘上设置有第一电连接体；
进行第一次塑封工艺，以形成包封第一芯片和囊封所述引线框架的第一塑封体，且使所述第一塑封体的第一表面裸露出所述第一导电柱和第一电连接体，第二表面裸露出所述第一引脚，所述第二表面为与所述第一表面相对的一面；
在所述第一表面上形成将所述第一导电柱和第一电连接体电连接的第二引脚。
优选的，所述制造方法还包括进行第二次塑封工艺，以形成包封所述第二引脚的第二塑封体。
优选的，在所述第一引脚上形成与所述第一引脚电连接的第一导电柱之前，还包括在封装基板上形成所述引线框架。
优选的，在封装基板上形成所述引线框架的步骤包括：
在所述封装基板上形成第一导电层；
图案化所述第一导电层，以形成所述引线框架。
优选的，形成所述引线框架时，使所述承载盘与一个所述第一引脚一体成型，以实现所述承载盘和第一引脚直接的电连接。
优选的，进行第二次塑封工艺之后还包括去除所述封装基板的步骤，以使所述第二表面裸露出所述第一引脚和所述承载盘。
优选的，采用电镀工艺，在所述第一引脚上形成所述第一导电柱。
优选的，形成所述第二引脚的步骤包括：
在所述第一表面上形成第二导电层；
图案化所述第二导电层，以形成所述第二引脚。
优选的，所述制造方法还包括在所述第一芯片的有源面的电极焊盘上形成金属层或导电凸块作为所述第一电连体。
优选的，所述背表面上具有背面电极焊盘，所述背面电极焊盘通过焊料或导电胶贴装于所述承载盘上。
优选的，在所述封装基板上形成的所述引线框架还包括位于所述承载盘周围的第三引脚，
所述制造方法还包括：
在将第一芯片的背表面贴装于所述承载盘上之前，在所述第三引脚上形成第二导电柱，在形成所述第一塑封体时，使所述第一表面裸露出所述第二导电柱；
在形成所述第一塑封体之后，在所述第一表面上形成与所述第二导电柱电连接的第四引脚；
将第二芯片的有源面上的电极焊盘通过第二电连接体电连接到所述第四引脚上；
在形成所述第二塑封体时，使所述第二塑封体还包封所述第四引脚、第二芯片；
在形成所述第一塑封体时，使所述第二表面还裸露出所述第三引脚。
优选的，在将所述第二芯片的有源面上的电极焊盘通过所述第二电连接体电连接到所述第四引脚上时，还使所述第二芯片上的有源面上的电极焊盘通过第二电连接体与所述第二引脚电连接。
由上可见，在本发明提供的芯片封装结构中，芯片有源面上的电极焊盘通过由第一电连接体、第二引脚、第一导电柱以及第一引脚构成导电路径引出，最终由第一引脚实现芯片与外部电路之间的电连接。这种引出电极的方式，由于第二引脚和第一导电柱的截面(与电流流向垂直方向的截面)面积与导电路径的长度之比远大于引线键合的截面与导电路径的长度之比。因此，本发明的这种引出电极的方式，相比引线键合的方式，可有效的降低封装电阻，且由于本发明的这种方式无需采用焊料焊接，可避免虚焊现象，可提高芯片封装的可靠性。此外，由于第二引脚的厚度可以做得比较薄，使得芯片的封装厚度更加接近裸芯片的厚度，可更好的迎合人们对器件薄型化的需求。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为根据本发明实施例提供的一种芯片封装结构的剖面结构示意图；
图2为根据本发明实施例提供的另一种芯片封装结构的剖面结构示意图。
图3a-图3f为根据本发明实施例的一种芯片封装结构的制造工艺流程中各个工艺步骤形成结构的剖面示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的组成部分采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节，例如每个组成部分的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
图1为根据本发明实施例提供的一种芯片封装结构的剖面结构示意图。
如图1所示，在本实施例中，所述芯片封装结构包括引线框架01、第一导电柱02、第一芯片03、第一电连接体04、第一塑封体05、第二引脚06、第二塑封体07。
在本实施例中，引线框架01包括承载盘011和位于承载盘周围的第一引脚012，第一引脚012的个数可以为一个也可以为多个，其可根据第一芯片03的有源面上电极焊盘的个数以及第一芯片03的有源面上的电路来设定。形成引线框架01的材料可以为铜等导电材料，则第一引脚和承载盘均可导电，当然，在形成所述引线框架时，若芯片与所述承载盘相接触的一面上没有电极，则承载盘不要求一定为导电材质，只要第一引脚确保为导电材料即可。
第一导电柱02位于第一引脚012上，且与第一引脚012电连接，其形成材料可以与所述第一引脚的材料相同，例如二者可均为铜材料。第一导电柱02具有一定的高度，该高度一般只要确保第一导电柱02与第一引脚012的叠加高度，后续安装与承载盘011上的芯片和承载盘011的叠加厚度即可。
第一芯片03具有有源面和与有源面相对的背表面，所述背表面贴装于承载盘011上。所述背表面也可以设置有电极焊盘，可称为被表面电极焊盘。若第一芯片03的背表面上具有背表面电极焊盘时，该背表面电极焊盘可通过焊料或导电胶贴装于承载盘011上，则通过承载盘011引出背表面电极。当然第一芯片03的背表面贴装于承载盘011上的方式不限定于此。此外，在一些应用中，若希望承载盘011所引出的电极与一个第一引脚012引出的电极电连接，可以通过使承载盘011与一个第一引脚012电连接来实现，例如使承载盘011与第一引脚012相连接，或者使承载盘011具有一个延伸部分，且该延伸部分作为一个第一引脚012，以与第一芯片03的有源面上电极焊盘电连接。在第一芯片03的有源面的电极焊盘上设置有第一电连接体04，其形成材料可以与所述第一导电柱02的相同，例如也可以为铜，其用于将第一芯片03有源面上的电极焊盘与外部组件(例如引脚)电连接。
第一塑封体05，用于包封(全部封住)第一芯片03和囊封(不完全封住)所述引线框架01，以防止外部水汽或其它污染物损坏第一芯片03中的有源器件。通常情况下，引线框架01、第一导电柱02以及第一电连接体4也会被第一塑封体05囊封(不完全包封)，但是，第一导电柱02和第一电连接体04必须得裸露在第一塑封体05的第一表面，以与其它组件(如引脚)电连接，而第一引脚012必须的裸露于第一塑封体05的第二表面，以与其它组件电连接。其中，第一塑封体05的第一表面为其第二表面相对一面。若承载盘011不与芯片03的电极焊盘电连接，其可不裸露于所述第二表面，否则，也需要裸露于所述第二表面，以与其它组件电连接。
第二引脚06位于第一塑封体05的第一表面上，且将第一导电柱02和第一电连接体04电连接。第二引脚06的个数可以为一个或多个，一般根据第一引脚012的数目来确定，其形成材料可与第一导电柱02以及第一电连接体04均相同，例如也可以为铜。每一个第二引脚06将一个第一电连接体04与一个第二导电柱02电连接。
继续参考图1所示，本实施例提供的芯片封装结构，还包括第二塑封体07，其位于第一塑封体05的第一表面之上，以用于包封所述第二引脚06。第一塑封体05与第二塑封体07的形成材料可相同，例如二者均可为环氧树脂模塑料、环氧塑封料等。
由上可见，在本发明提供的芯片封装结构中，芯片有源面上的电极焊盘通过由第一电连接体、第二引脚、第一导电柱以及第一引脚构成导电路径引出，最终由第一引脚实现芯片与外部电路之间的电连接。这种引出电极的方式，由于第二引脚和第一导电柱的截面(与电流流向垂直方向的截面)面积与导电路径的长度之比远大于引线键合的截面与导电路径的长度之比。因此，本发明的这种引出电极的方式，相比引线键合的方式，可有效的降低封装电阻，且由于本发明的这种方式无需采用焊料焊接，可避免虚焊现象，可提高芯片封装的可靠性。此外，由于第二引脚的厚度可以做得比较薄，使得芯片的封装厚度更加接近裸芯片的厚度，可更好的迎合人们对器件薄型化的需求。
图2为根据本发明实施例提供的另一种芯片封装结构的剖面结构示意图。
请参考图2，本实施例所提供的芯片封装结构相对于图1所示的芯片封装结构来说，引线框架01还包括同样位于承载盘011周围的第三引脚013，其形成材料可与第一引脚012相同，所述芯片封装结构还包括第二导电柱08、第四引脚09、第二芯片10、第二电连接体11。
第二导电柱08形成于第三引脚013之上，且与第三引脚电连接，其形成材料可于第三引脚013相同，例如金属铜。同样第二导电柱08也具有一定的高度，其可以与第一导电柱02的高度相同，且第二导电柱08也位于第一塑封体05之中，且其裸露于第一塑封体05的第一表面上。
第四引脚09位于第一塑封体05的第一表面上，且与第二导电柱08电连接，其与第三引脚处于同一平面，且二者可采用相同的材料形成，例如金属铜。第四引脚09的个数可以为一个或多个，一般由第二芯片10的有源面上的电极或电路来决定。
第二芯片10的有源面朝向第一塑封体05的第一表面，且位于该有源面的电极焊盘通过第二电连接体11与第四引脚09电连接，第二芯片10的有源面的电极焊盘也可通过第二电连接体11与第二引脚06电连接，第二电连接体11可以为导电凸块或者焊料。在其它实施例中，第二芯片10的有源面也可背向第一塑封体05的第一表面，即第二芯片10与其有源面相对的一面(背表面)放置于所述第一表面之上，第二芯片10的有源面上的电极焊盘通过第二电连接体11电连接到所述第四引脚09或第二引脚06上，第二电连接体可以为金属引线。
此外，第四引脚09和第二芯片10也被所述第二塑封体07包封，
由此可见，在本实施例的芯片封装结构中，第二芯片上电极可通过第二电连接体、第四引脚以及第三引脚组成的路径引出，最终通过第三引脚实现与第二芯片与外部电路之间的电连接，此外，第二芯片上的电极还可先通过第二电连接体、第二引脚、第一电连接体组成的导电路径与第一芯片的电极电连接后，再通过第一电连接体、第二引脚、第一导电柱以及第一引脚组成的导电路径引出，最终通过第一引脚实现与外部电路的电连接。因此，本发明所提供的芯片封装结构还可实现多芯片的叠层封装，且在多芯片的封装组件中，由于导电路径的电流处理能力较强，且无需使用引线键合，可有效的提高了芯片封装的可靠性，降低了封装电阻和厚度。
本申请还提供了一种芯片封装结构的制造方法，下面将以具体实施例来进一步详细的阐述本发明提供的芯片封装结构的制造方法。
图3a-图3f为根据本发明实施例的一种芯片封装结构的制造工艺流程中各个工艺步骤形成结构的剖面示意图。
参考图3a所示，在封装基板00上形成具有承载盘011和第一引脚012的引线框架01，第一引脚012位于承载盘011周围。形成引线框架01的方法可具体包括：现在封装基板00上形成一层第一导电层，例如铜层，然后图案化(利用掩模进行蚀刻工艺来实现)第一导电层，使得第一导电层形成具有位于中间的承载盘和位于周围的第一引脚的引线框架10。当然，具有这样特征的引线框架10也可以直接提供，或者通过其它方式来制备。此外，在形成引线框架01时，也可使形成的承载盘011具有一个延伸部分，且使该延伸部分作为一个第一引脚012，以实现承载盘011与一个第一引脚012的电连接，即在制作所述引线框架01时，使承载盘011和一个第一引脚012一体成型。
参考图3b所示，在第一引脚012上形成第一导电柱02，第一导电柱02与第一引脚012电连接，且具有一定的高度，该高度根据后续需要封装的芯片的厚度来决定。可以采用电镀的方式在第一引脚012上形成第一导电柱02，第电镀材料可以选用与第一引脚012相同的材料，例如金属铜。
参考图3c所示，将第一芯片03的背表面贴装于承载盘011上，所述背表面为与第一芯片03的有源面相对的一面，第一芯片03的有源面的电极焊盘上设置有第一电连接体04，可通过在第一芯片03的有源面的电极焊盘上形成金属层或导电凸块形成第一电连接体04。若所述背表面上具有背表面电极，则可使背表面电极通过焊料或导电胶贴装于承载盘011上，以与承载盘011电连接。若承载盘011的延伸部分作为一个第一引脚012，则实现了该第一引脚所引出的电极与承载盘011所引出电极电连接。
参考图3d所示，采用塑封料，进行第一塑封工艺，使塑封料覆盖于封装基板之上，用于包封(包封指全部封住，即第一芯片没有被第一塑封体裸露在外的部分)第一芯片03和囊封(囊封指不完全封住，即引线框架还有一部分裸露在第一塑封体之外)所述引线框架01，以形成具有第一表面和与第一表面相对的第二表面的第一塑封体05，其中，使第一导电柱02和第一电连接体04均裸露于所述第一表面上。为实现具有这样特性的第一塑封体05，在完成第一次塑封工艺后，塑封料可能会覆盖在第一导电柱02和第一电连接体04之上，因此，还需要研磨塑封体05的第一表面，直到所述第一表面裸露出所述第一导电柱02和第一电连接体04为止。
参考图3e所示，在第一塑封体05的第一表面上形成将所述第一导电柱02和第一电连接体04实现电连接的第二引脚06。形成第二引脚06的具体方法可以包括：在所述第一表面上形成第二导电层，图案化第二导电层，以形成第二引脚。第二引脚的数量可以为一个或多个，其由第一芯片03的有源面上的电极或电路来决定。每一个第二引脚06将一个第一导电柱02和之上一个第一电连接体04电连接。
继续参考图3f所示，进一步的，还可在所述第一表面上利用塑封料，进行第二次塑封工艺，使塑封料包封第二引脚06，以形成第二塑封体07。在形成第二塑封体07后，去除封装基板00，使所述第一引脚012和承载盘011均裸露于所述第一塑封体05的第二表面上，便可获得如图1所示的芯片封装结构，所述第二表面为与所述第一表面相对的一面。
由上可见，在本发明提供的芯片封装结构的制造方法中，使芯片有源面上的电极焊盘通过由第一电连接体、第二引脚、第一导电柱以及第一引脚构成导电路径引出，最终由第一引脚实现芯片与外部电路之间的电连接。这种引出电极的方式，第二引脚和第一导电柱的截面(与电流流向垂直方向的截面)面积与导电路径的长度之比远大于引线键合的截面与导电路径的长度之比。因此，本发明的这种引出电极的方式，相比引线键合的方式，可有效的降低封装电阻，且由于本发明的这种方式无需采用焊料焊接，可避免虚焊现象，可提高芯片封装的可靠性。此外，由于第二引脚的厚度可以做得比较薄，使得芯片的封装厚度更加接近裸芯片的厚度，可更好的迎合人们对器件薄型化的需求。
进一步的，在上述工艺过程中，还可加入下列过程，在所述封装基板上形成述引线框架01时，还可使形成的引线框架01还包括同样位于所述承载盘011周围的第三引脚013。
在将第一芯片03的背表面贴装于所述承载盘011上之前，在所述第三引脚上形成第二导电柱08，在形成所述第一塑封体05时，使所述第一表面裸露还出所述第二导电柱08。第二导电柱08的形成方法与在第一引脚012上形成第一导电柱02的方法可相同，二者可在同一个工艺步骤中形成。
在形成所述第一塑封体05之后，在所述第一表面上形成与所述第二导电柱08电连接的第四引脚09，第四引脚09可与第三引脚06在同一个工艺步骤中形成。
将第二芯片10的有源面朝向第一塑封体05的第一表面，将其上的电极焊盘通过第二电连接体11电连接到所述第四引脚上，以使第二芯片10上电极通过与第四引脚09电连接的第三引脚08引出，以与外部电路电连接，其中第二电连接体11可以为导电凸块或者焊料。此外，在其它实施例中，还可使第二芯片10的有源面背向第一塑封体05的第一表面，即将第二芯片10的背表面放置于第一塑封体05的第一表面之上，再将有源面的电极焊盘通过第二电连接体11与第四引脚09或第二引脚06电连接。其中，第二芯片10的背表面为与有源面相对的一面，第二电连接体11可以为金属引线。
更进一步的，在进行该步骤的同时，还可使第二芯片10的有源面上的电极焊盘通过第二电连接体11电连接到所述第二引脚06上，以先实现第二芯片10与第一芯03片之间的电连接，然后再将二者连接的节点引出与外部电路连接。
在形成第二塑封体07时，使所述第二塑封体07还包封所述第四引脚09、第二芯片10。此外，在在形成第一塑封体05时，使所述第二表面还裸露出所述第三引脚08，以使第三引脚可与外部电路电连接。
由此可见，本发明提供的芯片封装结构的制造方法还可实现多芯片层的封装，使第二芯片上电极可通过第二电连接体、第四引脚以及第三引脚组成的路径引出，最终通过第三引脚实现与第二芯片与外部电路之间的电连接，此外，第二芯片上的电极还可先通过第二电连接体、第二引脚、第一电连接体组成的导电路径与第一芯片的电极电连接后，再通过第一电连接体、第二引脚、第一导电柱以及第一引脚组成的导电路径引出，最终通过第一引脚实现与外部电路的电连接。因此，通过本发明所提供的芯片封装结构的制造方法形成的芯片封装结构由于导电路径的电流处理能力较强，且无需使用引线键合，可有效的提高了芯片封装的可靠性，降低了封装电阻和厚度。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (21)

1.一种芯片封装结构，包括：
引线框架，具有承载盘和位于所述承载盘周围的第一引脚；
位于所述第一引脚上且与所述第一引脚电连接的第一导电柱；
第一芯片，具有有源面和与所述有源面相对的背表面，所述背表面贴装于所述承载盘上，所述有源面的电极焊盘上设置有第一电连接体；
第一塑封体，用于包封所述第一芯片和囊封所述引线框架，且具有第一表面和与所述第一表面相对的第二表面，其中，所述第一表面裸露出所述第一导电柱和所述第一电连接体，所述第二表面裸露出所述第一引脚，
位于所述第一表面上的第二引脚，用于将所述第一电连接体和所述第一导电柱电连接。
2.根据权利要求1所述的芯片封装结构，其特征在于，还包括用于包封所述第二引脚的第二塑封体。
3.根据权利要求2所述的芯片封装结构，其特征在于，所述第二表面上还裸露出所述承载盘。
4.根据权利要求3所述的芯片封装结构，其特征在于，所述背表面具有背面电极焊盘，所述背面电极焊盘通过焊料或导电胶贴装于所述承载盘上。
5.根据权利要求4所述的芯片封装结构，其特征在于，所述承载盘与一个所述第一引脚电连接。
6.根据权利要求3所述的芯片封装结构，其特征在于，所述第一引脚、第一导电柱、第一电连接体、第二引脚的形成材料相同。
7.根据权利要求2所述的芯片封装结构，其特征在于，所述引线框架还具有位于所述承载盘周围的第三引脚，所述芯片封装结构还包括：
位于所述第三引脚上且与所述第三引脚电连接的第二导电柱，所述第一表面还裸露出所述第二导电柱；
位于所述第一表面上且与所述第二导电柱电连接的第四引脚；
位于所述第一表面上方，且有源面上的电极焊盘通过第二电连接体电连接到所述第四引脚上的第二芯片；
所述第二塑封体还用于包括所述第四引脚、第二芯片；
所述第二表面上还裸露出所述第三引脚。
8.根据权利要求7所述的芯片封装结构，其特征在于，所述第二芯片的有源面上的电极焊盘通过第二电连接体与所述第二引脚电连接。
9.根据权利要求8所述的芯片封装结构，其特征在于，所述第二电连接体为导电凸块、焊料、金属引线中的一种。
10.一种芯片封装结构的制造方法，包括：
提供具有承载盘和第一引脚的引线框架，所述第一引脚位于所述承载盘周围，在所述第一引脚上形成与所述第一引脚电连接的第一导电柱；
将第一芯片的背表面贴装于所述承载盘上，所述背表面为与所述第一芯片的有源面相对的一面，所述有源面的电极焊盘上设置有第一电连接体；
进行第一次塑封工艺，以形成包封所述第一芯片和囊封所述引线框架的第一塑封体，且使所述第一塑封体的第一表面裸露出所述第一导电柱和第一电连接体，第二表面裸露出所述第一引脚，所述第二表面为与所述第一表面相对的一面；
在所述第一表面上形成将所述第一导电柱和第一电连接体电连接的第二引脚。
11.根据权利要求10所述的制造方法，其特征在于，还包括进行第二次塑封工艺，以形成包封所述第二引脚的第二塑封体。
12.根据权利要求11所述的制造方法，其特征在于，在所述第一引脚上形成与所述第一引脚电连接的第一导电柱之前，还包括在封装基板上形成所述引线框架。
13.根据权利要求12述的制造方法，其特征在于，在封装基板上形成所述引线框架的步骤包括：
在所述封装基板上形成第一导电层；
图案化所述第一导电层，以形成所述引线框架。
14.根据权利要求13述的制造方法，其特征在于，形成所述引线框架时，使所述承载盘与一个所述第一引脚一体成型，以实现所述承载盘和第一引脚直接的电连接。
15.根据权利要求13所述的制造方法，其特征在于，进行第二次塑封工艺之后还包括去除所述封装基板的步骤，以使所述第二表面裸露出所述第一引脚和所述承载盘。
16.根据权利要求15所述的制造方法，其特征在于，采用电镀工艺，在所述第一引脚上形成所述第一导电柱。
17.根据权利要求15所述的制造方法，其特征在于，形成所述第二引脚的步骤包括：
在所述第一表面上形成第二导电层；
图案化所述第二导电层，以形成所述第二引脚。
18.根据权利要求12所述的制造方法，其特征在于，还包括在所述第一芯片的有源面的电极焊盘上形成金属层或导电凸块作为所述第一电连体。
19.根据权利要求18所述的制造方法，其特征在于，所述背表面电极焊盘，所述背面电极焊盘通过焊料或导电胶贴装于所述承载盘上。
20.根据权利要求12所述的制造方法，其特征在于，在所述封装基板上形成的所述引线框架还包括位于所述承载盘周围的第三引脚，
所述制造方法还包括：
在将第一芯片的背表面贴装于所述承载盘上之前，在所述第三引脚上形成第二导电柱，在形成所述第一塑封体时，使所述第一表面裸露出所述第二导电柱；
在形成所述第一塑封体之后，在所述第一表面上形成与所述第二导电柱电连接的第四引脚；
将第二芯片的有源面上的电极焊盘通过第二电连接体电连接到所述第四引脚上；
在形成所述第二塑封体时，使所述第二塑封体还包封所述第四引脚、第二芯片；
在形成所述第一塑封体时，使所述第二表面还裸露出所述第三引脚。
21.根据权利要求20所述的制造方法，其特征在于，在将所述第二芯片的有源面上的电极焊盘通过所述第二电连接体电连接到所述第四引脚上时，还使所述第二芯片上的有源面上的电极焊盘通过第二电连接体与所述第二引脚电连接。
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