CN105990329A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN105990329A
CN105990329A CN201510096632.7A CN201510096632A CN105990329A CN 105990329 A CN105990329 A CN 105990329A CN 201510096632 A CN201510096632 A CN 201510096632A CN 105990329 A CN105990329 A CN 105990329A
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semiconductor device
substrate
semiconductor chip
terminal
opening
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松浦永悟
竹本康男
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明的实施方式涉及一种半导体装置及其制造方法，可实现在衬底上设置有多个半导体芯片的半导体装置的薄型化。根据一实施方式，半导体装置包括衬底，该衬底具有第一面、及与所述第一面为相反侧的第二面。进而，所述装置包括：第一半导体芯片，设置在所述衬底的所述第一面；及第二半导体芯片，设置在所述衬底的所述第二面，且覆盖贯通所述衬底的开口的至少一部分。进而，所述装置包括第三半导体芯片，该第三半导体芯片在所述开口内，经由接着剂而设置在所述第二半导体芯片的所述衬底侧的面。

Description

半导体装置及其制造方法
[相关申请案]
本申请案以日本专利申请案2014-188272号(申请日：2014年9月16日)为基础申请案并享有其优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
于在半导体装置的电路衬底搭载多个存储器芯片、及控制该等存储器芯片的动作的控制芯片的情况下，存在难以实现半导体装置的薄型化的问题。
例如，于在电路衬底的上表面搭载第一存储器芯片，且在第一存储器芯片的上表面搭载第二存储器芯片的情况下，第二存储器芯片的上表面的高度较邻接搭载该等存储器芯片的情况变高。另外，于在第一存储器芯片的上表面搭载第二存储器芯片的情况下，连接在第二存储器芯片的上表面的键合导线的最上部的高度较第二存储器芯片的上表面变得更高。因此，覆盖电路衬底的密封树脂的厚度对应于该键合导线的最上部的高度而变厚。因此，键合导线成为半导体装置的薄型化的障碍。
另外，控制芯片一般具有与存储器芯片相同程度的厚度。因此，于在电路衬底的上表面搭载第一存储器芯片与控制芯片，且在电路衬底的下表面搭载第二存储器芯片的情况下，连接在控制芯片的上表面的键合导线的最上部的高度较第一存储器芯片的上表面或控制芯片的上表面变高。因此，覆盖电路衬底的密封树脂的厚度对应于控制芯片用的键合导线的高度而变厚。因此，该键合导线成为半导体装置的薄型化的障碍。
发明内容
本发明的实施方式可实现在衬底上设置有多个半导体芯片的半导体装置的薄型化。
根据一实施方式，半导体装置包括衬底，该衬底具有第一面、及与所述第一面为相反侧的第二面。进而，所述装置包括：第一半导体芯片，设置在所述衬底的所述第一面；及第二半导体芯片，设置在所述衬底的所述第二面，且覆盖所述开口的至少一部分。进而，所述装置包括第三半导体芯片，该第三半导体芯片在所述开口内，经由接着剂而设置在所述第二半导体芯片的所述衬底侧的面。
附图说明
图1是表示第一实施方式的半导体装置的构造的剖视图。
图2(a)及(b)是表示第一实施方式的半导体装置的构造的俯视图及仰视图。
图3是表示第一实施方式的比较例的半导体装置的构造的剖视图。
图4(a)及(b)是表示第一实施方式的半导体装置的制造方法的剖视图(1/4)。
图5(a)及(b)是表示第一实施方式的半导体装置的制造方法的剖视图(2/4)。
图6(a)及(b)是表示第一实施方式的半导体装置的制造方法的剖视图(3/4)。
图7(a)及(b)是表示第一实施方式的半导体装置的制造方法的剖视图(4/4)。
图8是表示第二实施方式的半导体装置的构造的剖视图。
图9是表示第三实施方式的半导体装置的构造的剖视图。
图10是表示第四实施方式的半导体装置的构造的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
(第一实施方式)
图1是表示第一实施方式的半导体装置的构造的剖视图。图2(a)及图2(b)分别为表示第一实施方式的半导体装置的构造的俯视图及仰视图。
以下，主要参照图1对本实施方式的半导体装置的构造进行说明。在该说明中，也适当参照图2(a)及图2(b)。
本实施方式的半导体装置包括作为衬底的一例的电路衬底1、作为第一半导体芯片的一例的第一存储器芯片2、作为第二半导体芯片的一例的第二存储器芯片3、作为第三半导体芯片的一例的控制芯片4、及密封树脂5。
[电路衬底1]
电路衬底1具有第一面S1、与第一面S1为相反侧的第二面S2、连结第一面S1与第二面S2的第一开口部H1、及连结第一面S1与第二面S2的第二开口部H2。符号σ1表示第一开口部H1的侧面。符号σ2表示第二开口部H2的侧面。符号T1表示电路衬底1的厚度。厚度T1例如为50μm～150μm。
图1表示与第一面S1或第二面S2平行、且相互垂直的X方向及Y方向、及与第一面S1或第二面S2垂直的Z方向。在本说明书中，将+Z方向视为上方向，将-Z方向视为下方向。例如，图1的第一面S1与第二面S2的位置关系表现为第一面S1位于第二面S2的上方。此外，-Z方向可与重力方向一致，也可与重力方向不一致。
电路衬底1包括绝缘衬底11、第一及第二配线层12a、12b、第一及第二绝缘层13a、13b、作为第一端子的一例的多个第一连接端子14、作为第二端子的一例的多个第二连接端子15、作为第三端子的一例的多个第三连接端子16、及多个第四连接端子17。
第一配线层12a与第一绝缘层13a依序形成在电路衬底1的上表面(第一面S1侧的面)。第一及第三连接端子14、16设置在电路衬底1的第一面S1，且电连接于第一配线层12a。第一及第三连接端子14、16配置在第二开口部H2附近(参照图2(a))。
第二配线层12b与第二绝缘层13b依序形成在电路衬底1的下表面(第二面S2侧的面)。第二及第四连接端子15、17设置在电路衬底1的第二面S2，且电连接于第二配线层12b。第二连接端子15配置在第一开口部H1附近(参照图2(b))。第四连接端子17作为用以将本实施方式的半导体装置与外部连接的外部连接端子而使用。
此外，电路衬底1也可包括导电层，该导电层在贯通绝缘衬底11、第一及第二配线层12a、12b、第一及第二绝缘层13a、13b的一个以上的贯通孔内，将第一配线层12a与第二配线层12b电连接。
[第一存储器芯片2]
第一存储器芯片2搭载在电路衬底1的第一面S1，且利用接着剂6而接着于电路衬底1。接着剂6为第一接着剂的一例。第一存储器芯片2是经由接着剂6而设置在电路衬底1的第一面S1。符号T2表示第一存储器芯片2的厚度。厚度T2例如为80μm以下。
第一存储器芯片2包括面向第一开口部H1的多个第一连接垫21。第一连接垫21为第一垫的一例。各第一连接垫21通过设置在第一开口部H1内的第一键合导线51而电连接于第二连接端子15。第一键合导线51为第一导线的一例。
[第二存储器芯片3]
第二存储器芯片3搭载在电路衬底1的第二面S2，利用接着剂7而接着于电路衬底1。接着剂7为第二接着剂的一例。第二存储器芯片3经由接着剂7而设置在电路衬底1的第二面S2。符号T3表示第二存储器芯片3的厚度。厚度T3例如为80μm以下。
第二存储器芯片3包括面向第二开口部H2的多个第二连接垫31。第二连接垫31为第二垫的一例。各第二连接垫31通过设置在第二开口部H2内的第二键合导线52而电连接于第一连接端子14。第二键合导线52为第二导线的一例。
[控制芯片4]
控制芯片4在第二开口部H2内搭载在第二存储器芯片3的上表面(电路衬底1侧的面)，且利用接着剂7而接着于第二存储器芯片3。控制芯片4经由接着剂7而设置在第二存储器芯片3的上表面。符号T4表示控制芯片4的厚度。厚度T4例如为80μm以下。本实施方式的厚度T4设定为与厚度T2、T3相同的程度(T4≒T2、T3)。另外，本实施方式的厚度T4可小于厚度T1，也可大于厚度T1。控制芯片4控制第一及第二存储器芯片2、3的动作。
控制芯片4在上表面包括多个第三连接垫41、及多个第四连接垫42。第三及第四连接垫41、42分别为第三及第四垫的一例。各第三连接垫41通过第三键合导线53而与第三连接端子16电连接。各第四连接垫42通过第四键合导线54而与第二连接垫31电连接。第三及第四键合导线53、54分别为第三及第四导线的一例。
如上所述，控制芯片4配置在第二开口部H2内。因此，本实施方式的第二开口部H2的XY平面内的面积设定为大于第一开口部H1的XY平面内的面积。此外，在本实施方式中，控制芯片4是与第二键合导线52配置在同一开口部(第二开口部H2)内，但也可与第二键合导线52配置在不同开口部内。
[密封树脂5]
密封树脂5覆盖电路衬底1的第一面S1与第二面S2。第一至第四键合导线51～54或控制芯片4被密封树脂5完全覆盖。另一方面，第一存储器芯片2的侧面被密封树脂5覆盖，且其上表面从密封树脂5露出。同样地，第二存储器芯片3的侧面被密封树脂5覆盖，且其下表面从密封树脂5露出。因此，本实施方式的密封树脂5的厚度大致为T1+T2+T3。
本实施方式的半导体装置还包括多个第一焊料球55。第一焊料球55用以将本实施方式的半导体装置与外部连接。各第一焊料球55电连接于第四连接端子17。各第一焊料球55的侧面被密封树脂5覆盖，且其等的下表面从密封树脂5露出。各第一焊料球55的下表面可与密封树脂5的下表面位于相同高度，也可位于低于密封树脂5的下表面的高度。即，各第一焊料球55的下表面可从密封树脂5的下表面露出，也可不从密封树脂5的下表面露出。
(1)第一实施方式的比较例
图3是表示第一实施方式的比较例的半导体装置的构造的剖视图。
本比较例的半导体装置包括：第一存储器芯片2，搭载在电路衬底1的第一面S1；及第二存储器芯片3，搭载在第一存储器芯片2上。本比较例的半导体装置还包括控制芯片4，该控制芯片4搭载在电路衬底1的第一面S1，且利用接着剂8而接着于电路衬底1。在本比较例中，第一至第三连接端子14～16设置在电路衬底1的第一面S1，且第四连接端子17设置在电路衬底1的第二面S2。
在本比较例中，连接在第二存储器芯片3的上表面的第二键合导线52的最上部的高度高于第二存储器芯片3的上表面。因此，密封树脂5的厚度T5大于第一及第二存储器芯片2、3的厚度的和(T5＞T2+T3)。
本比较例的半导体装置的厚度大致为电路衬底1的厚度T1、密封树脂5的厚度T5、及第一焊料球55的厚度的和。因此，本比较例的半导体装置的厚度大于T1+T2+T3。另一方面，第一实施方式的半导体装置的厚度大致为T1+T2+T3。因此，第一实施方式的半导体装置的厚度薄于本比较例的半导体装置的厚度。
如上所述，根据本实施方式，通过将第一及第二存储器芯片2、3分别搭载在电路衬底1的第一面S1与第二面S2，而可使半导体装置的厚度较图3的比较例更薄。具体而言，根据本实施方式，与比较例相比可使半导体装置的厚度变薄值T5－T2－T3及第一焊料球55的厚度的量。
另外，在将比较例的第二存储器芯片3从第一面S1转移至第二面S2的情况下，比较例的半导体装置的厚度成为大致电路衬底1的厚度T1、控制芯片4的第三键合导线53的最上部的高度、及第二存储器芯片3的厚度T3的和。此处，第三键合导线53的最上部的高度大于控制芯片4的厚度T4，控制芯片4的厚度T4与第一存储器芯片2的厚度T2为相同程度。因此，该情况下的半导体装置的厚度大于T1+T2+T3。
另一方面，由于控制芯片4配置在第二开口部H2内，因此本实施方式的半导体装置的厚度为大致T1+T2+T3。如此一来，根据本实施方式，与将控制芯片2搭载在第一面S1或第二面S2的情况相比可使半导体装置的厚度变薄。
(2)第一半导体装置的半导体装置的制造方法
图4～图7是表示第一实施方式的半导体装置的制造方法的剖视图。
首先，准备图1的电路衬底1(图4(a))。其次，在电路衬底1的第一面S1搭载第一存储器芯片2(图4(a))。第一存储器芯片2是利用涂布在第一存储器芯片2的接着剂6而接着于电路衬底1。另外，第一存储器芯片2是以第一连接垫21面向第一开口部H1的方式搭载。
继而，使电路衬底1上下翻转(图4(b))。其次，在第一开口部H1内插入第一键合导线51，通过该导线51而将第一连接垫21与第二连接端子15电连接(图4(b))。
其次，在电路衬底1的第二面S2搭载第二存储器芯片3(图5(a))。第二存储器芯片3通过涂布在第二存储器芯片3上的接着剂7而接着于电路衬底1。另外，第二存储器芯片3以第二连接垫31面向第二开口部H2的方式搭载。
其次，使电路衬底1上下翻转(图5(b))。其次，在第二开口部H2内，在第二存储器芯片3的上表面搭载控制芯片4(图5(b))。控制芯片4利用涂布在第二存储器芯片3的接着剂7而接着于第二存储器芯片3。
其次，在第二开口部H2内插入第二键合导线52，通过该导线52而将第二连接垫31与第一连接端子14电连接(图6(a))。其次，在第二开口部H2内插入第三键合导线53，通过该导线53而将第三连接垫41与第三连接端子16电连接(图6(a))。其次，在第二开口部H2内插入第四键合导线54，通过该导线54而将第四连接垫42与第二连接垫31电连接(图6(a))。
继而，形成覆盖电路衬底1的第一面S1与第二面S2的密封树脂5(图6(b))。本实施方式的密封树脂5通过例如使用模具的转移成型(transfer molding)、或使用粉末树脂的压缩成型而形成。
其次，在电路衬底1的第二面S2侧的密封树脂5，利用激光而形成多个开口部5a(图7(a))。其结果，第四连接端子17在开口部5a内露出。
其次，在开口部5a内填充焊料(图7(b))。其结果，在开口部5a内形成第一焊料球55。
此外，图4(a)～图6(a)的步骤例如也能以图4(a)、图5(a)、图5(b)、图4(b)、图6(a)的步骤的顺序进行。即，也可在搭载第一存储器芯片2、第二存储器芯片3、及控制芯片4后，键合第一至第四键合导线51～54。在该情况下，电路衬底1的翻转次数从2次增加至四次。另外，在例如以图4(a)、图5(a)、图5(b)、图6(a)、图4(b)的步骤的顺序进行图4(a)～图6(a)的步骤的情况下，电路衬底1的翻转次数成为三次。
如上所述，在本实施方式中，将第一及第二存储器芯片2、3分别搭载在电路衬底1的第一面S1与第二面S2，并将控制芯片4搭载在第二开口部H2内。因此，根据本实施方式，可实现在衬底1设置有多个半导体芯片2、3、4的半导体装置的薄型化。
(第二至第四实施方式)
图8是表示第二实施方式的半导体装置的构造的剖视图。
第一实施方式的第一焊料球55被密封树脂5覆盖。另一方面，本实施方式的第一焊料球55从密封树脂5露出。根据本实施方式，在图7(a)的步骤中不在密封树脂5形成开口部5a便可形成第一焊料球55。
图9是表示第三实施方式的半导体装置的构造的剖视图。
第一实施方式的第一存储器芯片2的侧面被密封树脂5覆盖，且其上表面从密封树脂5露出。另一方面，本实施方式的第一存储器芯片2的侧面与上表面被密封树脂5覆盖。同样地，本实施方式的第二存储器芯片3的侧面与下表面被密封树脂5覆盖。
本实施方式的构造采用于例如第一及第二存储器芯片的厚度T2、T3较薄的情况。在该情况下，存在第一键合导线51的最下部低于第二存储器芯片3的下表面的情况、或第二键合导线52的最上部高于第一存储器芯片2的上表面的情况。在该等情况下，通过采用本实施方式的构造，而可利用密封树脂5覆盖第一及第二键合导线51、52。
另外，本实施方式的构造采用于例如欲提高半导体装置的可靠性的情况。根据本实施方式，可降低在第一及第二存储器芯片2、3的角部附近作用于密封树脂5的应力。因此，在本实施方式中，即使密封树脂5的温度变化，也可降低密封树脂5从第一及第二存储器芯片2、3剥离的可能性。
图10是表示第四实施方式的半导体装置的构造的剖视图。本实施方式的半导体装置包括第一半导体装置101、及第二半导体装置102。
第一半导体装置101具有与图1的半导体装置相同的构造。但是，第一半导体装置101除包括图1所示的构成要素以外，还包括多个第五连接端子18、及多个第二焊料球56。
第五连接端子18设置在电路衬底1的第一面S1，且电连接于第一配线层12a。第五连接端子18与第四连接端子17同样地作为用以将第一半导体装置101与外部连接的外部连接端子而使用。
各第二焊料球56电连接于第五连接端子18。各第二焊料球56的侧面被密封树脂5覆盖，且其等的上表面从密封树脂5露出。各第二焊料球56的上表面可位于与密封树脂5的上表面相同的高度，也可位于高于密封树脂5的上表面的高度。即，各第二焊料球56的上表面可从密封树脂5的上表面露出，也可不从密封树脂5的上表面露出。
第二半导体装置102具有与第一半导体装置101相同的构造。即，第二半导体装置102除包括图1的构成要素以外，还包括多个第五连接端子18、及多个第二焊料球56。
在本实施方式中，以使第一半导体装置101的第一焊料球55、与第二半导体装置102的第二焊料球56相互接触的方式，将第一半导体装置101积载在第二半导体装置102上。其结果，该等焊料球55、56电连接，而使第一及第二半导体装置101、102可相互交换信号。
此外，如果第一半导体装置101的第一焊料球55与第二半导体装置102的第二焊料球56电连接，则第一半导体装置101的下表面与第二半导体装置102的上表面可相互接触，也可相互分开。
另外，本实施方式的半导体装置也可积层具有与第一及第二半导体装置101、102相同构造的三个以上的半导体装置而构成。
如上所述，在第二至第四实施方式中，将第一及第二存储器芯片2、3分别搭载在电路衬底1的第一面S1与第二面S2，并将控制芯片4搭载在第二开口部H2内。因此，根据该等实施方式，可与第一实施方式同样地，实现在衬底1设置有多个半导体芯片2、3、4的半导体装置的薄型化。
以上，对若干个实施方式进行了说明，但该等实施方式仅仅是作为例子而提出者，并未意图限定发明的范围。本说明书中说明的新颖的装置及方法能够以其他各种形态实施。另外，对于本说明书中说明的装置及方法的形态，可在不脱离发明的主旨的范围内进行各种省略、置换、变更。随附的权利要求及与其均等的范围意图包含发明的范围或主旨中包含的此种形态或变化例。
[符号的说明]
1 电路衬底
2 第一存储器芯片
3 第二存储器芯片
4 控制芯片
5 密封树脂
5a 开口部
6、7、8 接着剂
11 绝缘衬底
12a 第一配线层
12b 第二配线层
13a 第一绝缘层
13b 第二绝缘层
14 第一连接端子
15 第二连接端子
16 第三连接端子
17 第四连接端子
18 第五连接端子
21 第一连接垫
31 第二连接垫
41 第三连接垫
42 第四连接垫
51 第一键合导线
52 第二键合导线
53 第三键合导线
54 第四键合导线
55 第一焊料球
56 第二焊料球
101 第一半导体装置
102 第二半导体装置

Claims (6)

1.一种半导体装置，其特征在于包括：
衬底，包含第一面、及与所述第一面为相反侧的第二面；
第一半导体芯片，设置在所述衬底的所述第一面；
第二半导体芯片，设置在所述衬底的所述第二面，且覆盖贯通所述衬底的开口的至少一部分；以及
第三半导体芯片，在所述开口内，经由接着剂而设置在所述第二半导体芯片的所述衬底侧的面。
2.根据权利要求1所述的半导体装置，其特征在于：所述衬底包括设置在所述第一面的第一端子、以及设置在所述第二面的第二端子，
所述第一半导体芯片包括面向第一开口的第一垫，所述第一垫通过设置在所述第一开口内的第一导线而与所述第二端子电连接，且
所述第二半导体芯片包括面向第二开口的第二垫，所述第二垫通过设置在所述第二开口内的第二导线与所述第一端子电连接。
3.根据权利要求2所述的半导体装置，其特征在于：所述第二半导体芯片经由所述接着剂而设置在所述衬底的所述第二面，且
所述第三半导体芯片设置在所述第二开口内。
4.根据权利要求2或3所述的半导体装置，其特征在于：所述衬底包括设置在所述第一面的第三端子，且
所述第三半导体芯片包括：第三垫，通过第三导线而与所述第三端子电连接；及第四垫，通过第四导线而与所述第二半导体芯片的所述第二垫电连接。
5.一种半导体装置的制造方法，其特征在于包含：
在包括第一面、及与所述第一面为相反侧的第二面的衬底的所述第一面，经由第一接着剂而搭载第一半导体芯片，
在所述衬底的所述第二面，以覆盖贯通所述衬底的开口的至少一部分的方式经由第二接着剂而搭载第二半导体芯片，且
在所述开口内，在所述第二半导体芯片的所述衬底侧的面经由所述第二接着剂而搭载第三半导体芯片。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于：所述第一半导体芯片以第一垫面向第一开口的方式搭载在所述衬底的所述第一面，
所述第二半导体芯片以第二垫面向第二开口的方式搭载在所述衬底的所述第二面，进而，
通过插入至所述第一开口内的第一导线，而将所述第一半导体芯片的所述第一垫、与设置在所述衬底的所述第二面的第二端子电连接，且
通过插入至所述第二开口内的第二导线，而将所述第二半导体芯片的所述第二垫、与设置在所述衬底的所述第一面的第一端子电连接。
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