CN103650131B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103650131B
CN103650131B CN201280033910.9A CN201280033910A CN103650131B CN 103650131 B CN103650131 B CN 103650131B CN 201280033910 A CN201280033910 A CN 201280033910A CN 103650131 B CN103650131 B CN 103650131B
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Prior art keywords
electrode
extension
semiconductor device
wiring
insulating barrier
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CN201280033910.9A
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CN103650131A (zh
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岩濑铁平
油井隆
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供一种半导体装置,具有:第1半导体芯片;其侧面的扩展部以及其上的连接端子;在半导体芯片及扩展部上包括与连接端子接合的布线和其上的绝缘层的再布线部;在扩展部上位于再布线部的表面的绝缘层的开口部与布线接合的电极。电极主要由弹性模量高于布线的材料构成,具有在开口部与布线接合的接合区域以及靠近扩展部的端部的外方区域。布线连续延伸到外方区域的跟前为止。据此,在形成于由树脂等弹性体构成的扩展部上的再布线层上的电极进行引线键合的情况下,也能将电极正下方以及其周围的物理损伤抑制到最小限度,能提供可靠性高的半导体装置。

Description

半导体装置
技术领域
本公开涉及半导体装置,特别涉及伴随引线键合安装的半导体装置。
背景技术
在数字电视、录像机等的系统中,伴随高功能化,处置的数据飞跃性地增加。其结果,在搭载于系统的半导体存储器中,要求容量的增加以及高的数据传输速率。
作为搭载这样的半导体存储器的半导体装置,有将安装存储器控制器的半导体逻辑电路芯片和存储器集成在1个芯片中的系统级芯片(SoC)、以及将安装有存储器控制器的半导体逻辑电路芯片和存储器芯片进行层叠来收纳在1个封装中的系统级封装(SiP)。
当前,使用了制造成本比较低的SiP的系统有增加的倾向。
在这样的半导体装置中,在电连接所搭载的半导体逻辑电路芯片和存储器芯片间的方法中,能举出使用叠层芯片(CoC)技术的方法。根据该方法,使半导体逻辑电路芯片的电路形成面、与存储器芯片的电路形成面面相面对,介由由焊料、金或铜等构成的金属突起来将各自的电极彼此直接连接。该方法在使数据传输速率较高的目的下被广泛利用。
专利文献1记载的半导体装置是将前述的半导体逻辑电路芯片的功能引出到封装的外部端子的构成的示例。这时在逻辑电路芯片的外周的不与存储器芯片对置的区域形成电极,使用引线键合法等,介由金、铝或铜等金属细线与周围的基板上的电极连接的构成。
现有技术文献
专利文献
专利文献1:JP特开2010-141080号公报
发明的概要
发明要解决的课题
在专利文献1的半导体装置中,在存储器芯片上层叠比存储器芯片小型的半导体逻辑电路芯片。但是,在半导体逻辑电路芯片与存储器芯片的大小关系因产品不同而存在各种变种。
在存储器容量较大的情况下,存储器芯片一方比逻辑电路芯片更大。这种情况下,需要准备大于存储器芯片的尺寸的逻辑电路芯片,作为结果,由于能减少每1个晶片的芯片数,因此会变为高成本。另外,还考虑使存储器芯片和逻辑电路芯片上下颠倒来在存储器芯片形成引线键合用的电极。但是,这种情况下,变得需要在存储器芯片的布线内形成引线键合用的特别的电路,因此作为半导体装置的通用性变低。
关于这一点,考虑使用图1(a)所示那样的从成为层叠构造的下侧的逻辑电路芯片1的外周侧壁起通过扩展部2进行扩展的扩展型芯片3的半导体装置100。在半导体装置100中,在与存储器芯片(未图示)对置的面,从逻辑电路芯片101跨到树脂制的扩展部102来形成包含从逻辑电路芯片101的连接端子104引出功能的布线151的再布线层(RDL、Re-Distribustion Layer)150。在扩展部102上的区域,在再布线层150的表面形成与布线151连接的引线键合用的电极106。如此,通过扩展下侧芯片的尺寸,即使是尺寸大的存储器芯片,也能以低成本来形成通用性高的封装件。
另一方面,在上述的构造中,由于电极106以及布线151的下部全部由绝缘层152、扩展部102等弹性体构成,因此,存在因引线键合时的热、荷重或超声波振动而使弹性模量显著降低,有极端变形的可能性。在出现这样的变形的情况下,由于荷重或振动未充分地传递给电极106,因此,比起与逻辑电路芯片101上的连接端子104进行键合的情况,更需要使键合时的荷重和振幅变大来确保对于电极106的接合性。但是,在高负荷的引线键合条件下,在电极106的正下方以及其周边的构造中易于出现变形和剥离。
除了绝缘层152、扩展部102等弹性体的变形以外,布线151的材料(例如铜、铝等)相对于荷重和振动也同样具有易于变形的性质。因此,关于布线151,也要考虑较大地变形、在这些材料间产生大量翘曲的情况。
进一步而言,形成于布线151的绝缘层152,在布线工艺上通过旋涂法等涂敷形成。其结果,认为绝缘层152与其它界面相比紧贴力较低,在高温环境下紧贴力更加降低。特别是在布线151和绝缘层152的界面附近,存在发生剥离裂纹等物理损伤这样的课题。
另外,在上述那样的电极106中,如图1(b)所示,开口部107的宽度d1,需要相对于引线键合用所需的区域108的宽度d2具有针对接合偏离的余量来进行設定。进而,需要相对于开口部107的宽度d1确保考虑了布线时的偏离的余量,来设定布线151以及电极106的宽度d3。其结果,需要将开口部107的宽度d1和电极106的宽度d3形成得大于引线(未图示)与布线151的接合区域108的宽度d2。由此,还存在相邻的电极106彼此的间距变宽,用于配置所要求的数量的端子的扩展部102的尺寸会变大这样其它课题。
发明内容
相对于以上,本公开的半导体装置具有:第1半导体芯片;扩展部,其从第1半导体芯片的侧面起形成于外方;连接端子,其形成于第1半导体芯片上;再布线部,其配置为从第1半导体芯片上跨到扩展部上,且由与连接端子连接的布线以及覆盖布线的绝缘层构成;和电极,其位于扩展部的正上方且在再布线部的表面与从设于绝缘层的开口部露出的布线接合,电极形成为以弹性模量高于再布线部的布线的材料为主,电极具有:在绝缘层的开口部与布线接合的接合区域、和比接合区域更靠近扩展部的端部的外方区域,再布线部的布线形成为避免连续延伸到电极的外方区域的正下方。
发明的效果
根据本公开的技术,在形成于由树脂等弹性体构成的扩展部上的再布线层上的电极进行引线键合的情况下,也能将电极正下方以及其周围的物理损伤抑制到最小限度,能提供可靠性高的半导体装置。另外,能提供在确保连接可靠性的同时、将电极配置所需的空间抑制到最小限度的半导体装置。
附图说明
图1(a)以及(b)示意地表示背景技术的半导体装置,图1(a)是截面图,图1(b)是从图1(a)中的A一侧看到的俯视图。
图2(a)~(c)示意地表示本公开的1个实施方式的例示的半导体装置,图2(a)是表示整体的俯瞰图,图2(b)是表示图2(a)中的B-B′线下的截面图,图2(c)是从图2(b)中的A一侧看到的俯视图。
图3(a)以及(b)表示图1(a)~(c)的半导体装置的变形例,图3(a)是截面图、图3(b)是从图3(a)中的A一侧看到的俯视图。
图4(a)以及(b)表示图1(a)~(c)的半导体装置的其它的变形例,图4(a)是截面图,图4(b)是从图4(a)中的A一侧看到的俯视图。
具体实施方式
下面,使用附图来说明本公开的1个实施方式的半导体装置。在全部附图中,对公共的构成要素赋予相同的符号。
(第1实施方式)
图2(a)~(c)是示意地表示本实施方式的例示的半导体装置200的构成的图。特别地,图2(a)是表示整体的俯瞰图,图2(b)是图2(a)中的B-B′线下的截面图,图2(c)是从图2(b)中的A的一侧看到的俯视图。
图2(a)所示的半导体装置200具有:成为层叠构造的下侧的第1半导体芯片1、和从半导体芯片1的外周侧壁(侧面)起向外方延伸而形成的扩展部2。在半导体芯片1的上表面的周缘部设置连接端子4,包含从该连接端子4引出功能的布线51的再布线层50从半导体芯片1跨到扩展部2而形成。在扩展部2上的区域,在再布线层50的表面设置开口部541,在该开口部541形成与布线51连接的引线键合用的电极16。更详细地,采用以下的构成。
以硅为材料的半导体芯片1在与层叠于半导体芯片上的层叠第2半导体芯片(未图示)相面对的面上具有在硅上构成电特性功能的电路。而且,具有多个第1连接端子4、和用于CoC连接到第2半导体芯片的第2连接端子5。连接端子4以及连接端子5的材料为铝、铜等金属材料。另外,连接端子4由于是用于再布线层50进行的引出,因此其连接盘尺寸形成为宽度约30~100μm。另一方面,关于连接端子5,为了能以窄间距进行接合,其宽度比连接端子4要窄,形成为约10~30μm。在此,所谓连接端子4的连接盘的宽度,设为与再布线层50从连接端子4向电极16延伸的方向大致正交的连接盘的边的宽度。
扩展部2覆盖半导体芯片1的侧面,使半导体芯片1向外侧扩展地形成,其材料为树脂等弹性体。半导体芯片1的上表面与扩展部2的上表面大致齐平,从半导体芯片1跨到扩展部2形成包含用于引出连接端子4的布线51的再布线层50。
再布线层50如图2(b)所示那样具有:第1绝缘层53、形成于第1绝缘层53上的布线51、和将布线51夹在与第1绝缘层53间地形成于第1绝缘层53上的第2绝缘层54。在第1绝缘层53以及第2绝缘层54,使用聚酰亚胺、PBO(poly benzoxazole:聚苯并噁唑)等,在布线51,使用铜、铝等金属材料。
如图2(b)以及(c)所示,在第1绝缘层53,使半导体芯片1的连接端子4从绝缘层53露出地设置开口部531。布线51形成为覆盖开口部531。连接端子4与布线51在该开口部53连接,布线51将半导体芯片1的电路引出。由连接端子4引出的布线51在绝缘层53上从半导体芯片1跨到扩展部2,横穿半导体芯片1与扩展部2的边界地形成,延伸到扩展部2的外缘附近为止。
在第2绝缘层54,在位于扩展部2的正上方的部分设置使布线51从第2绝缘层54露出的开口部541。电极16以覆盖开口部541的方式形成,布线51与电极16在该开口部541连接。
电极16以镍等金属材料为基底,在最表面使用金、钯等材料。电极16的尺寸只要是一般的引线键合方法所需要的宽度即可,宽度为约30~100μm。作为电极16的形成方法,一般为电解镀法。在第2绝缘层54以及开口部541中的布线51、与电极16的界面,设置钛、钨、铜等的晶种层(未图示)。
电极16以覆盖开口部541的形式形成,但还从该开口部541起向扩展部2的端部方向延伸,在第2绝缘层54上平坦形成,以使确保能键合程度的一定面积。更详细地,电极16具有:开口部541中的电极16与布线51的接合部附近的接合区域r1;和比接合区域r1更靠近扩展部2的端部且包含引线键合用所需的区域8的外方区域r2。在外方区域r2进行引线键合。此时,布线51形成为:虽连续延伸到外方区域r2的跟前为止,但避免延伸到外方区域r2的正下方。换言之,布线51未连续延伸到外方区域r2的正下方。另外,其它的金属材料也未被配置在外方区域r2的正下方,成为仅配置了第1绝缘层53、第2绝缘层54以及扩展部2等弹性体的构成。
在本实施方式中,半导体装置200构成为:能实现在半导体芯片1的区域的与第2半导体芯片(存储器芯片)的40μm间距以下的窄间距的CoC连接,另外能在扩展部2上进行基于引线键合连接的引出。由此,在第2半导体芯片为大于第1半导体芯片1的尺寸的情况下,也是仅变更扩展部2的尺寸就能使用现有的通用的引线键合条件以及内插板的间距规则,能实现廉价的封装化。
进而,在半导体装置200中,在进行电极16的引线键合的外方区域r2的正下方,布线51未延伸过来,且第1绝缘层53以及第2绝缘层54、与树脂制的扩展部2的机械性质比较类似。由此,能使因引线键合时的热、荷重、振动等而产生的变形所引起的界面的翘曲较小。
另外,在键合点的正下方,由于存在紧贴力低的布线51与第1绝缘层53以及第2绝缘层54的界面,因此即使键合的冲击传递过来,也能使该界面的物理损伤较小。特别在使用弹性模量高的含镍的金属来形成电极16的情况下,由于形成于电极正下方的晶种层的影响而确保了紧贴力,电极16自身的变形量变少。其结果,还能使在电极16与第2绝缘层54界面的损伤减少,能对作为半导体装置的可靠性提高作出大的贡献。
除此之外,半导体装置200对于引线键合用所需的区域8的宽度d2,可以仅具有针对接合偏离的余量来形成电极16,而不需要考虑针对开口部541的余量。因而,与图1(b)所示的背景技术的半导体装置相比,能使电极配置所需的空间较小,进而能实现半导体装置的小型化。
(第1实施方式的变形例1)
接下来,说明第1实施方式的变形例1。图3是示意地表示本变形例所涉及的半导体装置210的构成的图,图3(a)是截面图,图3(b)是从图3(a)中的A一侧看到的俯视图。
如图2(b)等所示那样,在第1实施方式中,在电极16的外方区域r2的正下方,布线51未延伸过来,且也不存在其它的金属材料。与此相对,在图3(a)所示的本变形例的半导体装置210中,在电极16中的外方区域r2的正下方断续地配置了金属材料9。至少在这一点上,本变形例的半导体装置与第1实施方式的半导体装置不同。如图3(b)所示,电极16的键合用所需的区域8、与金属材料9在半导体装置210的厚度方向上交叠。
在本变形例中,在因引线键合时的热、荷重、振动而在金属材料和第1绝缘层53产生翘曲这一点上,与图1(a)~(c)所示的背景技术的半导体装置相同。但是,断续形成的金属材料与第1绝缘层53的接触面积较大,翘曲的影响分散而减轻。因而,由于难以产生剥离、裂纹等物理损伤,还能使电极16与第2绝缘层54的界面的损伤减少,因此,与第1实施方式相同,能对作为半导体装置的可靠性提高作出大的贡献。
金属材料9既可以与布线51相同,也可以不同,但在与布线51相同的工艺中形成会使工序简易。
(第1实施方式的变形例2)
接下来,说明第1实施方式的变形例2。图4(a)以及(b)是示意地表示本变形例所涉及的例示的半导体装置220的构成的图,图4(a)是截面图,图4(b)是从图4(a)中的A一侧看到的俯视图。
在第1实施方式中,电极16在再布线层50上与接合区域r1以及外方区域r2一起大致平坦地形成。与此相对,在图4(a)所示的半导体装置220中,通过在第1绝缘层53以及第2绝缘层54、与扩展部2间设置高低差,电极26也成为具有高低差的形状,在这一点上与第1实施方式不同。
更详细地,在扩展部2的端部的内侧形成第1绝缘层53的端部,且在第1绝缘层53的端部的内侧形成第2绝缘层54的端部,由此使扩展部2在其外周部露出。另外,使在开口部541引出的电极26介由第1绝缘层53以及第2绝缘层54的端部的高低差延伸到扩展部2的露出的部分,从而在扩展部2上确保了大致平坦的区域r3。
如图4(b)所示,在在本变形例中,电极26在延伸到扩展部2上的区域r3确保键合用所需的区域8,且利用该区域8进行键合。因此,在电极26的键合点的正下方,布线51自不必说,也不存在第1绝缘层53与第2绝缘层54界面、以及第1绝缘层53与扩展部2的界面。由此,由于能进一步减轻物理损伤,因此能对作为半导体装置的可靠性提高作出更大的贡献。
另外,在本变形例中,在第1绝缘层53的端部的内侧形成第2绝缘层54的端部,但第1绝缘层53以及第2绝缘层54的端部大致齐平地形成也没关系。
到此为止说明了本公开的实施方式以及其变形例,下面加上各实施方式以及变形例中公共的事项来进行补充。
布线51通过镀敷法或溅射法形成,由含铜或铝的金属材料构成。与此相对,引线键合用的电极16以及电极26作为弹性模量比布线51高的材料,使用通过镀敷法等形成的镍等。
扩展部2在第1实施方式中配置于半导体芯片1的四方,但并不限于此。例如,也可以仅覆盖对置的2边,也可以向3方扩展。另外,也可以覆盖到半导体芯片1的背面。
各实施方式中的“约”、“大致”等的范围是担保本领域技术人员的概念的范围,设为还包含通过通常制造方法来形成的情况下的誤差的范围的范围。
另外,在图1(b)、图2(c)、图3(b)中未图示绝缘层,但这是为了易于理解地说明实施方式以及变形例的特征进行的省略,在本公开的任意的实施方式、实施例中都将绝缘层作为构成要素而具备。
以上,基于上述实施方式以及其变形例、制造方法的一例来详细说明了本公开,但本公开并不限于上述实施方式等。只要不脱离本公开的宗旨就能进行变形和变更,例如,将构成要素的一部分置换为实施方式未记载的代替物的构成,也属于本公开的技术的范畴。
产业上的利用可能性
根据本公开的技术,能在使用了CoC形式的、通过树脂等扩展下侧的半导体芯片的周围的半导体装置的广泛的电子设备中运用。
符号的说明
1 半导体芯片
2 扩展部
4 连接端子
5 连接端子
8 区域
9 金属材料
16 电极
26 电极
50 再布线层
51 布线
53 第1绝缘层
54 第2绝缘层
200 半导体装置
210 半导体装置
220 半导体装置
531 开口部
541 开口部
r1 接合区域
r2 外方区域
r3 区域

Claims (8)

1.一种半导体装置,具有:
第1半导体芯片;
扩展部,其从所述第1半导体芯片的侧面起形成于外方;
连接端子,其形成于所述第1半导体芯片上;
再布线部,其配置为从所述第1半导体芯片上跨到所述扩展部上,且由与所述连接端子连接的布线以及覆盖所述布线的绝缘层构成;和
电极,其位于所述扩展部的正上方,且在所述再布线部的表面,与从设于所述绝缘层的开口部露出的所述布线接合,
所述电极形成为以弹性模量高于所述再布线部的所述布线的材料为主,
所述电极具有:在所述绝缘层的所述开口部与所述布线接合的接合区域、和比所述接合区域更靠近所述扩展部的端部的外方区域,
所述再布线部的所述布线形成为避免连续延伸到所述电极的所述外方区域的正下方。
2.根据权利要求1所述的半导体装置,其中,
所述再布线层的所述布线不存在于所述电极的所述外方区域的正下方。
3.根据权利要求1所述的半导体装置,其中,
在所述外方区域的正下方不存在金属。
4.在权利要求1所述的半导体装置中,其中,
在所述电极的所述外方区域的正下方,在与所述布线层相同的层断续地配置有金属。
5.根据权利要求1所述的半导体装置,其中,
所述再布线层的端部位于所述扩展部的端部的内侧,
所述扩展部在所述再布线层的端部的外侧露出,
所述电极从所述再布线层的所述绝缘层上超出所述再布线层的端部并跨到露出的所述扩展部上而一体形成。
6.根据权利要求1~5中任一项所述的半导体装置,其中,
所述布线是含铜或铝的金属材料。
7.根据权利要求1~5中任一项所述的半导体装置,其中,
所述电极包含由镍构成的金属。
8.根据权利要求1~5中任一项所述的半导体装置,其中,
在所述第1半导体芯片上搭载第2半导体芯片。
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