CN106024754A - 半导体封装组件 - Google Patents

半导体封装组件 Download PDF

Info

Publication number
CN106024754A
CN106024754A CN201610182901.6A CN201610182901A CN106024754A CN 106024754 A CN106024754 A CN 106024754A CN 201610182901 A CN201610182901 A CN 201610182901A CN 106024754 A CN106024754 A CN 106024754A
Authority
CN
China
Prior art keywords
semiconductor
semiconductor package
bare chip
chip
semiconductor bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610182901.6A
Other languages
English (en)
Other versions
CN106024754B (zh
Inventor
林子闳
彭逸轩
萧景文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN106024754A publication Critical patent/CN106024754A/zh
Application granted granted Critical
Publication of CN106024754B publication Critical patent/CN106024754B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明公开了一种半导体封装组件，以将电子元件(如无源元件)嵌入于重布线结构内。其中，该半导体封装组件包括半导体封装体，且该半导体封装体包括：重布线结构，具有第一表面及与其相对的第二表面；半导体裸芯片，设置于该第一重布线结构的该第一表面上；模塑化合物，设置于该第一重布线结构的该第一表面上，且围绕该第一半导体裸芯片；以及电子元件，嵌入于该第一重布线结构内，且经由该第一重布线结构电性耦接至该第一半导体裸芯片。

Description

半导体封装组件
技术领域
本发明涉及封装技术领域，尤其一种具有无源元件的半导体封装组件。
背景技术
为了确保电子产品及通讯装置的微型化及多功能性，所需的半导体封装体需具备小尺寸、支持多引脚(pin)连接、高速操作以及高功能性。另外，在高频应用(例如，射频(radio frequency,RF)系统封装(system in package,SiP)组件)中，通常使用一或多个整合的无源元件(integrated passive device,IPD)来进行上述功能。
在传统的SiP组件中，无源元件通常放置在印刷电路板(printed circuit board,PCB)或封装体上。然而，印刷电路板须提供额外的区域以将无源元件组装于其上。另外，当无源元件组装于封装体上时，SiP组件的总体高度将会增加。如此一来，势必难以缩小封装组件的尺寸。
因此，需要寻求一种新的半导体封装组件。
发明内容
有鉴于此，本发明提供了一种半导体封装组件，具有整合了的电子元件(如无源元件)。
本发明提供了一种半导体封装组件，包括︰第一半导体封装体，且该第一半导体封装体包括：第一重布线结构，具有第一表面及与其相对的第二表面；第一半导体裸芯片，设置于该第一重布线结构的该第一表面上；第一模塑化合物，设置于该第一重布线结构的该第一表面上，且围绕该第一半导体裸芯片；以及电子元件，嵌入于该第一重布线结构内，且经由该第一重布线结构电性耦接至该第一半导体裸芯片。
其中，该电子元件为无源元件。
其中，该第一半导体封装体更包括第二半导体裸芯片，嵌入于该第一重布线结构内。
其中，该第一半导体封装体更包括多个第一导电结构，设置于该第一重布线结构的该第二表面上，且电性耦接至该第一重布线结构。
其中，更包括印刷电路板，电性耦接至该多个第一导电结构。
其中，该第一重布线结构包括：第一金属层间介电层；多个第一导线，位于该第一金属层间介电层的第一层位，且该多个第一导线中的其中一个电性耦接至该第一半导体裸芯片；以及多个第二导线，位于该第一金属层间介电层的不同于该第一层位的第二层位。
其中，该电子元件包括至少一个电极，电性耦接至该多个第二导线的其中一者。
其中，该无源元件包括电容、电感、电阻或其组合。
其中，该第一半导体封装体还包括：第二重布线结构，设置于该第一半导体裸芯片及该第一模塑化合物上，使该第二重布线结构藉由该第一半导体裸芯片及该第一模塑化合物而与该第一重布线结构隔开；以及多个第一通孔电极，穿过该第一模塑化合物以形成该第一重布线结构与该第二重布线结构之间的电性连接。
其中，更包括︰第二半导体封装体，叠置于该第一半导体封装体上，且该第二半导体封装体包括：第三重布线结构，电性耦接至该第二重布线结构，且具有第三表面及与其相对的第四表面；第三半导体祼芯片，设置于该第三重布线结构的该第三表面上；以及第二模塑化合物，设置于该第三重布线结构的该第三表面上且围绕该第三半导体祼芯片。
其中，该第二半导体封装体更包括多个第二导电结构，设置于该第三重布线结构的该第四表面上且电性耦接至该第二重布线结构。
其中，该第一半导体封装体为片上系统封装体，且该第二半导体封装体为动态随机存取存储器封装体。
其中，该第一半导体封装体更包括：第四半导体裸芯片，设置于该第一重布线结构的该第一表面上，使该第一半导体裸芯片及该第四半导体裸芯片并排排列。
其中，该第一半导体裸芯片为系统裸芯片，而该第四半导体裸芯片为动态随机存取存储器裸芯片。
其中，该电子元件为多层陶瓷电容，包括：本体；以及第一及第二电极层，分别设置于该本体的两端，使该第一及该第二电极层覆盖该本体的侧壁、局部的上表面及局部的下表面，其中该第一及该第二电极层分别电性耦接至该多个第二导线中的至少二者。
其中，该电子元件为芯片电容，包括：本体；以及第一及第二电极层，分别设置于该本体的两端，使该第一及该第二电极层露出该本体的侧壁及局部的下表面，其中该第一及该第二电极层分别电性耦接至该多个第二导线中的至少二者。
本发明实施例的有益效果是：
以上的半导体封装组件，电子元件(如无源元件)嵌入于重布线结构内，且经由重布线结构电性耦接至半导体裸芯片，从而将半导体元件(如无源元件)整合进半导体封装组件中的重布线结构内。
附图说明
图1A绘示出根据本发明一些实施例的半导体封装组件的横截面示意图。
图1B为图1A中区域A1的放大图，其绘示出多层陶瓷电容(multi-layerceramic capacitor,MLCC)嵌入于重布线结构内。
图1C绘示出根据本发明一些实施例的半导体封装组件的横截面示意图。
图2A绘示出根据本发明一些实施例的半导体封装组件的横截面示意图。
图2B为图2A中区域A2的放大图，其绘示出芯片电容(chip-cap capacitor)嵌入于重布线结构内。
图2C绘示出根据本发明一些实施例的半导体封装组件的横截面示意图。
图3绘示出根据本发明一些实施例的具有层叠封装(package on package,PoP)结构的半导体封装组件的横截面示意图。
图4绘示出根据本发明一些实施例的具有片上系统(system-on-chip,SOC)封装体的半导体封装组件的横截面示意图，该SOC封装体包括二个并排设置的半导体裸芯片(die)。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明将参照特定的实施例及参照附图进行说明，然而这些说明并非用以局限本发明的范围而本发明的范围仅以权利要求的界定为准。在所绘的附图中，某些部件的尺寸会为了阐述目的放大并且未依比例绘示。外观尺寸及相对尺寸并未对应于本发明的实际尺寸。
图1A绘示出本发明一些实施例的半导体封装组件10a的横截面示意图。图1B为图1A中区域A1的放大图，其绘示出多层陶瓷电容(MLCC)150嵌入于重布线结构内。在一些实施例中，半导体封装组件10a为晶圆级半导体封装组件，例如覆晶半导体封装组件。
请参照图1A，半导体封装组件10a包括至少一个晶圆级半导体封装体100a，装设于基体600上。在本实施例中，晶圆级半导体封装体100a包括片上系统(SOC)封装体。再者，基体600包括印刷电路板(PCB)，其可由聚丙烯(polypropylene,PP)所制成。在一些实施例中，基体600可包括封装基底。
在本实施例中，基体600可为单层或多层结构。多个导电垫(未绘示)及与其电性耦接的导线(未绘示)设置于基体600的表面602及/或基体600内。在此情形中，导线可包括信号导线区段和电源/接地区段，以供半导体封装体100a的输入/输出(I/O)连接之用。在一实施例中，半导体封装体100a直接装设于导线上。在一些实施例中，设置于表面602的导电垫连接至不同的导线接端。在此情形中，这些导电垫供直接装设于导线上的半导体封装体100a之用。
半导体封装体100a藉由接合工艺装设于基体600的表面602上。举例来说，半导体封装体100a包括多个导电结构130，其藉由接合工艺装设于基体600上且电性耦接至基体600。半导体封装体100a包括半导体裸芯片100(例如，SOC裸芯片)及重布线(Redistribution Layer,RDL)结构126。举例来说，SOC裸芯片可包括逻辑裸芯片，其包括中央处理单元(Central Processing Unit,CPU)、图像处理单元(Graphics Processing Unit,GPU)、动态随机存取存储(DynamicRandom Access Memory,DRAM)控制器或其任何组合。再者，举例来说，导电结构130可包括导电凸块结构(例如铜凸块或焊料凸块结构)、导电柱体结构、导电接线结构或导电膏结构。
如图1A所示，由覆晶技术来制造半导体裸芯片100。半导体裸芯片100的接垫109电性连接至半导体裸芯片100的电路(未绘示)。在一些实施例中，接垫109属于半导体裸芯片100的内连接结构(未绘示)的最上金属层。半导体裸芯片100的接垫109与对应的导电结构111(例如，导电凸块、柱体或锡膏)接触。需注意的是整合于半导体封装组件10a内的半导体裸芯片100的数量并未局限于所述的实施例。
重布线(RDL)结构126(其也称作扇出式(fan-out)结构)具有第一表面101及与其相对的第二表面103。半导体裸芯片100设置于RDL结构126的第一表面101上。半导体封装体100a的半导体裸芯片100经由导电结构111而连接至RDL结构126。
在本实施例中，RDL结构126包括一个或多个导线，设置于金属层间介电(Inter-Metal Dielectric,IMD)层120内。举例来说，多个第一导线123设置于IMD层120内的第一层位，且至少一个第一导线123电性耦接至半导体裸芯片100。再者，多个第二导线121设置于IMD层120内不同于第一层位的第二层位。在此情形中，IMD层120可包括第一、第二及第三次介电层(sub-dielectriclayer)120a、120b及120c，依序从RDL结构126的第二表面103朝向RDL结构126的第一表面101堆叠，使第一导线123位于第三次介电层120c上，而第二导线121位于第二次介电层120b上且为第一次介电层120a所覆盖。再者，第一导线123藉由第二次介电层120b而与第二导线121隔开。在一些实施例中，IMD层120可由有机材料(包括高分子材料)或无机材料(包括氮化硅(SiNx)、氧化硅(SiOx)、石墨烯(graphene)等等)所形成。举例来说，第一、第二及第三次介电层120a、120b及120c由高分子材料制成，其中第一次介电层120a的厚度约为12微米(μm)，且第二次介电层120b的厚度约为24μm。
在一些实施例中，IMD层120为高k值介电层(k为介电层的介电常数)。在其他一些实施例中，IMD层120可由光敏性材料所制成，其包括干膜光阻或胶带膜(taping film)。
第二导线121的接垫部从第一次介电层120a的开口露出，且连接至导电结构130(其设置于RDL结构126的第二表面103)。同样需注意的是图1A中导线的数量及RDL结构126中次介电层的数量仅为例示，且本发明并未局限于此。
在本实施例中，半导体封装体100a更包括至少一个电子元件，例如整合的无源元件(IPD)，嵌入于RDL结构126内。IPD经由RDL结构126电性耦接至半导体裸芯片100。在一些实施例中，IPD可包括电容、电感、电阻或其组合。再者，IPD包括至少一个电极，电性耦接至该多个第二导线121中的其中一个。
在本实施例中，举例来说，IPD可为电容，例如多层陶瓷电容(MLCC)150，如图1A及1B所示。MLCC 150电性耦接至半导体裸芯片100。在此情形中，MLCC 150包括本体152与分别设置于本体152两端的第一和第二电极层154及156。再者，第一及第二电极层154及156覆盖本体152的侧壁、部分的上表面及部分的下表面。第一及第二电极层154及156分别电性耦接于该多个第二导线121中的至少二个。
在本实施例中，如图1A所示，半导体封装体100a更包括模塑化合物104，设置于RDL结构126的第一表面101上，且覆盖并围绕半导体裸芯片100。在一些实施例中，模塑化合物104由环氧化物、树脂、可塑型高分子等形成。模塑化合物104在实质上为液体时应用，接着经由化学反应而固化，例如位于环氧化物或树脂中。在其他一些实施例中，模塑化合物104可为紫外光(UV)或热力固化高分子，其为胶体或具延展性固体，且能够设置于半导体裸芯片100周围，接着可经由UV或热力固化工艺将其固化。模塑化合物104可以模具(未绘示)进行固化。
在本实施例中，模塑化合物104包括穿过其内的通孔电极(via)106。通孔电极106电性耦接至RDL结构126的第一导线123，然后再经由第一导线123耦接至RDL结构126的第二导线121。再者，通孔电极106可围绕半导体裸芯片100。在一些实施例中，通孔电极106可包括由铜构成的贯通封装体通孔(through package via,TPV)电极。
同样地，导电结构130经由RDL结构126而与模塑化合物104隔开。换句话说，导电结构130未与模塑化合物104接触。在一些实施例中，导电结构130可包括导电凸块结构(例如，铜或焊料凸块结构)、导电柱体结构、导电接线结构或导电膏结构。
根据上述实施例，半导体封装组件10a为设计成用以制造IPD结构。举例来说，MLCC 150嵌入于RDL结构126内。MLCC 150于半导体封装组件中提供可比拟的工艺能力。再者，半导体封装组件10a有助于改善表面黏着技术(Surface-Mount Technology,SMT)良率，即使更换半导体裸芯片(例如，半导体裸芯片100)时。另外，由于缩短了半导体裸芯片(例如，半导体裸芯片100)与MLCC 150之间的布线路径，因此可改善嵌入的MLCC 150的信号完整性/电源完整性(Signal Integrity/Power Integrity,SI/PI)效能。嵌入的MLCC 150可为半导体封装组件10a的系统整合提供设计弹性。
图1C绘示出根据本发明一些实施例的半导体封装组件10b的横截面示意图。以下部件的实施例的说明省略说明相同或相似于先前图1A中所述的部件。在本实施例中，除了半导体封装组件10b的半导体封装体100b更包括半导体裸芯片160(例如，SOC裸芯片)嵌入于RDL结构126内以外，半导体封装组件10b相似于图1A所示的半导体封装组件10a。半导体裸芯片160经由RDL结构126电性耦接至半导体裸芯片100。
再者，半导体裸芯片160包括至少一个接垫，电性耦接至该多个第二导线121中的其中一个。举例来说，半导体裸芯片160包括接垫164，其电性耦接至第二导线121。
根据此实施例，半导体封装组件10b为设计成用以制造IPD结构(即MLCC150)及嵌入于RDL结构126内的半导体裸芯片160。MLCC 150及半导体裸芯片160于半导体封装组件中提供可比拟的工艺能力。再者，半导体封装组件10b有助于改善SMT良率，即使更换半导体裸芯片(例如，半导体裸芯片100)时也有助于改善SMT良率。另外，由于缩短了半导体裸芯片(例如，半导体裸芯片100)与MLCC 150及半导体裸芯片160之间的布线路径，因此可改善嵌入的MLCC 150及半导体裸芯片160的SI/PI效能。嵌入的MLCC 150及半导体裸芯片160可对半导体封装组件10b的系统整合提供设计弹性。
图2A绘示出根据本发明一些实施例的半导体封装组件10c的横截面示意图，而图2B为图2A中区域A2的放大图，其绘示出芯片电容150’嵌入于重布线结构内。以下部件的实施例的说明省略说明相同或相似于先前图1A及1B中所述的部件。
在本实施例中，除了半导体封装组件10c中的半导体封装体100c包括芯片电容150’取代图1A及1B中的MLCC 150，而嵌入于RDL结构126内以外，半导体封装组件10c相似于图1A所示的半导体封装组件10a。
再者，芯片电容150’电性耦接至半导体裸芯片100。在此情形中，芯片电容150’包括本体152’与分别设置于本体152’两端的第一及第二电极层154’及156’。再者，第一及第二电极层154’及156’露出本体152’的部分侧壁、本体152’的上表面与本体152’的部分下表面。第一及第二电极层154’及156’分别电性耦接于该多个第二导线121中的至少二个。
根据上述实施例，半导体封装组件10c设计成用以制造IPD结构。举例来说，芯片电容150’嵌入于RDL结构126内。芯片电容150’于半导体封装组件中提供可比拟的工艺能力。相似地，半导体封装组件10c有助于改善SMT良率，即使更换半导体裸芯片(例如，半导体裸芯片100)时也有助于改善SMT良率。另外，由于缩短了半导体裸芯片(例如，半导体裸芯片100)与芯片电容150’之间的布线路径，因此可改善嵌入的芯片电容150’的SI/PI效能。嵌入的芯片电容150’可为半导体封装组件10c的系统整合提供设计弹性。
图2C绘示出根据本发明一些实施例的半导体封装组件10d的横截面示意图。以下部件的实施例的说明省略说明相同或相似于先前图1C中所述的部件。在本实施例中，除了半导体封装组件10d中的半导体封装体100d更包括：嵌入于RDL结构126内的半导体裸芯片160(例如，SOC裸芯片)以外，半导体封装组件10d相似于图2A所示的半导体封装组件10c。半导体裸芯片160经由RDL结构126电性耦接至半导体裸芯片100。再者，半导体裸芯片160包括至少一个接垫，电性耦接至第二导线121中的其中一个。举例来说，半导体裸芯片160包括接垫164，其电性耦接至第二导线121。
根据此实施例，半导体封装组件10d设计成用以制造IPD结构(即，芯片电容150’)及嵌入于RDL结构126内的半导体裸芯片160。芯片电容150’及半导体裸芯片160于半导体封装组件中提供可比拟的工艺能力。再者，半导体封装组件10d有助于改善SMT良率，即使更换半导体裸芯片(例如，半导体裸芯片100)时也有助于改善SMT良率。另外，由于缩短了半导体裸芯片(例如，半导体裸芯片100)与芯片电容150’及半导体裸芯片160之间的布线路径，因此可改善嵌入的芯片电容150’及半导体裸芯片160的SI/PI效能。嵌入的芯片电容150’及半导体裸芯片160可为半导体封装组件10b的系统整合提供设计弹性。
图3绘示出根据本发明一些实施例的具有层叠封装(PoP)结构的半导体封装组件的横截面示意图。以下部件的实施例的说明省略说明相同或相似于先前图1A至1C或图2A至2C中所述的部件。在本实施例中，除了半导体封装体100e更包括RDL结构226设置于半导体裸芯片100及模塑化合物104上，使RDL结构226藉由半导体裸芯片100及模塑化合物104而与RDL结构126隔开以外，半导体封装体100e相似于图2A所示的半导体封装体100c。再者，通孔电极106穿过模塑化合物104而形成RDL结构126与RDL结构226之间的电性连接。
RDL结构226具有第一表面201及与其相对的第二表面203。RDL结构226的第一表面201位于半导体裸芯片100及模塑化合物104上。亦即，相较于第二表面203，第一表面201靠近于半导体裸芯片100且与模塑化合物104接触。如同RDL结构126，RDL结构226可包括一个或多个导线，设置于IMD层220内。举例来说，多个导线221及多个介层连接窗223设置于IMD层220内，且该多个导线221中的至少一个电性连接至通孔电极106。在此情形中，IMD层220类似于IMD层120，且可包括第一、第二及第三次介电层220a、220b及220c，依序从RDL结构226的第二表面203朝向RDL结构226的第一表面201堆叠。再者，IMD层220由类似于IMD层120的材料形成。
导线221的接垫部从第三次介电层220c的开口处露出。需注意的是，图3中导线221与介层连接窗223的数量及IMD层220中次介电层的数量仅为例示，且本发明并未局限于此。如图3所示，RDL结构226藉由穿过RDL结构126与RDL结构226之间的模塑化合物104的通孔电极106而耦接至RDL结构126。
在一些实施例中，嵌入于RDL结构126内的芯片电容150’可取代为MLCC150，如图1A所示。在一些实施例中，半导体裸芯片160与芯片电容150’或MLCC 150可一同嵌入于RDL结构126内，如图1C或2C所示。
在本实施例中，如图3所示，半导体封装组件10e包括半导体封装体200a，藉由接合工艺而叠置于半导体封装体100e上。半导体封装体200a可包括存储器封装体，例如DRAM封装体。半导体封装体200a包括多个导电结构328，装设于半导体封装体100e上。半导体封装体200a藉由半导体封装体100e的RDL结构226及通孔电极106而耦接至RDL结构126。
在本实施例中，如图3所示，半导体封装体200a包括RDL结构326、至少一个半导体裸芯片(例如，二个DRAM裸芯片300及302)及模塑化合物304。RDL结构326具有相对的表面301及303。表面301供半导体裸芯片装设于其上之用，而表面303供导电结构328(例如，凸块)贴合于其上之用。
如同RDL结构126，RDL结构326可包括一个或多个位于IMD层320内的导线。举例来说，多个第一导线321及多个第二导线323设置于IMD层320内的不同层位。IMD层320的结构及材料类似于IMD层120的结构及材料。举例来说，IMD层320可包括第一、第二及第三次介电层320a、320b及320c，依序从RDL结构326的表面303朝向RDL结构326的表面301堆叠。
第一导线321的接垫部从第一次介电层320a的开口处露出。需注意的是图3中导线的数量及IMD层320的次介电层的数量仅为例示，且本发明并未局限于此。
在此实施例中，如图3所示，半导体裸芯片302及300依序叠置于RDL结构326的表面301上，其中半导体裸芯片302利用膏料(未绘示)而装设于RDL结构326上。同样地，半导体裸芯片300利用膏料(未绘示)而叠置于半导体裸芯片302上。半导体裸芯片302具有接垫308位于其上，而半导体裸芯片300具有接垫310位于其上。
接垫308及310可分别藉由接线(例如，接线314及316)耦接至RDL结构326的接垫325。需注意的是半导体封装体200a内堆叠的半导体裸芯片的数量并未局限于所述的实施例。在其他实施例中，二个半导体裸芯片300及302也可并排排列。
在本实施例中，模塑化合物304设置于RDL结构326的表面301上。再者，模塑化合物304覆盖并围绕二个半导体裸芯片300及302。模塑化合物304可由相同或相似于模塑化合物104的材料形成。
如图3所示，导电结构328设置于RDL结构326的表面303上，且电性耦接于RDL结构326的第一导线321与RDL结构226的介层连接窗223之间。半导体封装体200a电性耦接至半导体封装体100e的RDL结构126。如同导电结构130，导电结构328可包括铜或焊料凸块结构、导电柱体结构、导电接线结构或导电膏结构。
图4绘示出根据本发明其他一些实施例的半导体封装组件10f的横截面示意图，其包括具有二个并排的半导体裸芯片400a及400b的半导体封装体100f。以下部件的实施例的说明省略说明相同或相似于先前图1A至1B或图2A至2B中所述的部件。在本实施例中，如图4所示，半导体封装体100f可为SOC封装体，且包括二个并排设置的半导体裸芯片400a及400b。在一些实施例中，半导体裸芯片400a及400b中的至少一者为SOC裸芯片。举例来说，半导体裸芯片400a及400b皆为SOC裸芯片。在其他实施例中，半导体裸芯片400a为SOC裸芯片，而半导体裸芯片400b为存储器裸芯片，例如DRAM裸芯片。
在一些实施例中，IPD(例如，芯片电容150’)嵌入于RDL结构126内，且耦接至SOC裸芯片(例如，半导体裸芯片400a)。因此，半导体封装组件10f的半导体封装体100f包括纯SOC封装体或混合式SOC封装体。然而，半导体裸芯片的数量及排列方式并未局限于所述的实施例。
在一些实施例中，嵌入于RDL结构126内的芯片电容150’可取代为MLCC150，如图1A所示。在一些实施例中，半导体裸芯片160及芯片电容150’或MLCC 150可一同嵌入于RDL结构126内，如图1C或2C所示。
图3及4所示的实施例提供了一种半导体封装组件。在一些实施例中，半导体封装组件设计成用以制造IPD结构，例如嵌入于RDL结构126内的MLCC或芯片电容。半导体封装组件有助于改善SMT良率，即使更换半导体裸芯片(例如，SOC裸芯片)时也有助于改善SMT良率。另外，由于缩短了半导体裸芯片(例如，SOC裸芯片)与IPD之间的布线路径，因此可改善嵌入的IPD的SI/PI效能。嵌入的IPD可为半导体封装组件的系统整合提供设计弹性。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (16)

1.一种半导体封装组件，其特征在于，包括︰第一半导体封装体，且该第一半导体封装体包括：
第一重布线结构，具有第一表面及与其相对的第二表面；
第一半导体裸芯片，设置于该第一重布线结构的该第一表面上；
第一模塑化合物，设置于该第一重布线结构的该第一表面上，且围绕该第一半导体裸芯片；以及
电子元件，嵌入于该第一重布线结构内，且经由该第一重布线结构电性耦接至该第一半导体裸芯片。
2.如权利要求1所述的半导体封装组件，其特征在于，该电子元件为无源元件。
3.如权利要求1或2所述的半导体封装组件，其特征在于，该第一半导体封装体更包括第二半导体裸芯片，嵌入于该第一重布线结构内。
4.如权利要求1或2所述的半导体封装组件，其特征在于，该第一半导体封装体更包括多个第一导电结构，设置于该第一重布线结构的该第二表面上，且电性耦接至该第一重布线结构。
5.如权利要求4所述的半导体封装组件，其特征在于，更包括印刷电路板，电性耦接至该多个第一导电结构。
6.如权利要求1或2所述的半导体封装组件，其特征在于，该第一重布线结构包括：
第一金属层间介电层；
多个第一导线，位于该第一金属层间介电层的第一层位，且该多个第一导线中的其中一个电性耦接至该第一半导体裸芯片；以及
多个第二导线，位于该第一金属层间介电层的不同于该第一层位的第二层位。
7.如权利要求6所述的半导体封装组件，其特征在于，该电子元件包括至少一个电极，电性耦接至该多个第二导线的其中一者。
8.如权利要求2所述的半导体封装组件，其特征在于，该无源元件包括电容、电感、电阻或其组合。
9.如权利要求1或2所述的半导体封装组件，其特征在于，该第一半导体封装体还包括：
第二重布线结构，设置于该第一半导体裸芯片及该第一模塑化合物上，使该第二重布线结构藉由该第一半导体裸芯片及该第一模塑化合物而与该第一重布线结构隔开；以及
多个第一通孔电极，穿过该第一模塑化合物以形成该第一重布线结构与该第二重布线结构之间的电性连接。
10.如权利要求9所述的半导体封装组件，其特征在于，更包括︰
第二半导体封装体，叠置于该第一半导体封装体上，且该第二半导体封装体包括：
第三重布线结构，电性耦接至该第二重布线结构，且具有第三表面及与其相对的第四表面；
第三半导体祼芯片，设置于该第三重布线结构的该第三表面上；以及
第二模塑化合物，设置于该第三重布线结构的该第三表面上且围绕该第三半导体祼芯片。
11.如权利要求10所述的半导体封装组件，其特征在于，该第二半导体封装体更包括多个第二导电结构，设置于该第三重布线结构的该第四表面上且电性耦接至该第二重布线结构。
12.如权利要求10所述的半导体封装组件，其特征在于，该第一半导体封装体为片上系统封装体，且该第二半导体封装体为动态随机存取存储器封装体。
13.如权利要求1或2所述的半导体封装组件，其特征在于，该第一半导体封装体更包括：第四半导体裸芯片，设置于该第一重布线结构的该第一表面上，使该第一半导体裸芯片及该第四半导体裸芯片并排排列。
14.如权利要求13所述的半导体封装组件，其特征在于，该第一半导体裸芯片为系统裸芯片，而该第四半导体裸芯片为动态随机存取存储器裸芯片。
15.如权利要求6所述的半导体封装组件，其特征在于，该电子元件为多层陶瓷电容，包括：
本体；以及
第一及第二电极层，分别设置于该本体的两端，使该第一及该第二电极层覆盖该本体的侧壁、局部的上表面及局部的下表面，其中该第一及该第二电极层分别电性耦接至该多个第二导线中的至少二者。
16.如权利要求6所述的半导体封装组件，其特征在于，该电子元件为芯片电容，包括：
本体；以及
第一及第二电极层，分别设置于该本体的两端，使该第一及该第二电极层露出该本体的侧壁及局部的下表面，其中该第一及该第二电极层分别电性耦接至该多个第二导线中的至少二者。
CN201610182901.6A 2015-03-30 2016-03-28 半导体封装组件 Active CN106024754B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201562139932P 2015-03-30 2015-03-30
US62/139,932 2015-03-30
US201562157046P 2015-05-05 2015-05-05
US62/157,046 2015-05-05
US15/047,980 US10217724B2 (en) 2015-03-30 2016-02-19 Semiconductor package assembly with embedded IPD
US15/047,980 2016-02-19

Publications (2)

Publication Number Publication Date
CN106024754A true CN106024754A (zh) 2016-10-12
CN106024754B CN106024754B (zh) 2019-05-03

Family

ID=55527457

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610182901.6A Active CN106024754B (zh) 2015-03-30 2016-03-28 半导体封装组件

Country Status (4)

Country Link
US (1) US10217724B2 (zh)
EP (1) EP3076429B1 (zh)
CN (1) CN106024754B (zh)
TW (1) TWI642152B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018090622A1 (zh) * 2016-11-18 2018-05-24 华为技术有限公司 芯片封装结构和方法
CN108364932A (zh) * 2017-01-26 2018-08-03 日月光半导体制造股份有限公司 半导体封装结构
CN110391206A (zh) * 2018-04-19 2019-10-29 南亚电路板股份有限公司 封装结构及其形成方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283443B2 (en) * 2009-11-10 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package having integrated capacitor
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
KR101982049B1 (ko) 2016-11-23 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
US10593628B2 (en) * 2018-04-24 2020-03-17 Advanced Micro Devices, Inc. Molded die last chip combination
DE102018212273A1 (de) * 2018-07-24 2020-01-30 Robert Bosch Gmbh Elektronikeinheit
TWI659515B (zh) 2018-07-26 2019-05-11 欣興電子股份有限公司 封裝結構及其製造方法
US10672712B2 (en) 2018-07-30 2020-06-02 Advanced Micro Devices, Inc. Multi-RDL structure packages and methods of fabricating the same
FR3096808B1 (fr) * 2019-05-29 2021-10-22 Saint Gobain Pont A Mousson Dispositif d’identification, élément tubulaire et procédé correspondants
US11367628B2 (en) * 2019-07-16 2022-06-21 Advanced Micro Devices, Inc. Molded chip package with anchor structures
TWI734545B (zh) * 2020-07-03 2021-07-21 財團法人工業技術研究院 半導體封裝結構
US20220216154A1 (en) * 2021-01-06 2022-07-07 Mediatek Singapore Pte. Ltd. Semiconductor structure
US20230098054A1 (en) * 2021-09-29 2023-03-30 International Business Machines Corporation Electronic substrate stacking

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227095A1 (en) * 2002-05-31 2003-12-11 Tetsuya Fujisawa Semiconductor device and manufacturing method thereof
US20080119013A1 (en) * 2006-11-17 2008-05-22 Mangrum Marc A Method of packaging a device using a dielectric layer
US20090237900A1 (en) * 2008-03-24 2009-09-24 Makoto Origuchi Component built-in wiring board
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20110068468A1 (en) * 2008-12-08 2011-03-24 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4552524B2 (ja) 2004-06-10 2010-09-29 パナソニック株式会社 複合型電子部品
JP4912716B2 (ja) 2006-03-29 2012-04-11 新光電気工業株式会社 配線基板の製造方法、及び半導体装置の製造方法
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
KR100796523B1 (ko) 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
TWI452665B (zh) 2010-11-26 2014-09-11 矽品精密工業股份有限公司 具防靜電破壞及防電磁波干擾之封裝件及其製法
KR101434003B1 (ko) 2011-07-07 2014-08-27 삼성전기주식회사 반도체 패키지 및 그 제조 방법
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
KR20150025129A (ko) 2013-08-28 2015-03-10 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
KR102157551B1 (ko) 2013-11-08 2020-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9570418B2 (en) * 2014-06-06 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for package warpage control using dummy interconnects
WO2016092692A1 (ja) 2014-12-12 2016-06-16 株式会社メイコー モールド回路モジュール及びその製造方法
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US20160329299A1 (en) 2015-05-05 2016-11-10 Mediatek Inc. Fan-out package structure including antenna

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227095A1 (en) * 2002-05-31 2003-12-11 Tetsuya Fujisawa Semiconductor device and manufacturing method thereof
US20080119013A1 (en) * 2006-11-17 2008-05-22 Mangrum Marc A Method of packaging a device using a dielectric layer
US20090237900A1 (en) * 2008-03-24 2009-09-24 Makoto Origuchi Component built-in wiring board
US20110068468A1 (en) * 2008-12-08 2011-03-24 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018090622A1 (zh) * 2016-11-18 2018-05-24 华为技术有限公司 芯片封装结构和方法
CN108364932A (zh) * 2017-01-26 2018-08-03 日月光半导体制造股份有限公司 半导体封装结构
CN110391206A (zh) * 2018-04-19 2019-10-29 南亚电路板股份有限公司 封装结构及其形成方法

Also Published As

Publication number Publication date
TW201707164A (zh) 2017-02-16
EP3076429A3 (en) 2016-12-07
EP3076429B1 (en) 2020-05-06
US20160293581A1 (en) 2016-10-06
TWI642152B (zh) 2018-11-21
US10217724B2 (en) 2019-02-26
CN106024754B (zh) 2019-05-03
EP3076429A2 (en) 2016-10-05

Similar Documents

Publication Publication Date Title
CN106024754B (zh) 半导体封装组件
US11791256B2 (en) Package substrate and method of fabricating the same
JP7455951B2 (ja) チップパッケージ構造、およびチップパッケージ構造の製造方法
US8064215B2 (en) Semiconductor chip package and printed circuit board
CN108022923B (zh) 半导体封装
KR100818088B1 (ko) 반도체 패키지 및 그 제조 방법
US9179549B2 (en) Packaging substrate having embedded passive component and fabrication method thereof
CN105938816A (zh) 半导体封装结构
CN111279474B (zh) 具有分层保护机制的半导体装置及相关系统、装置及方法
TWI780081B (zh) 半導體元件及其製造方法
KR20050037430A (ko) 반도체 패키지 디바이스와 그의 형성 및 테스트 방법
US20130258623A1 (en) Package structure having embedded electronic element and fabrication method thereof
CN104037142A (zh) 封装对准结构及其形成方法
US11037879B2 (en) Semiconductor device
US20130020572A1 (en) Cap Chip and Reroute Layer for Stacked Microelectronic Module
US10529680B2 (en) Encapsulated electronic device mounted on a redistribution layer
CN102157501B (zh) 三维系统级封装结构
KR102559874B1 (ko) 박형 시스템 인 패키지
KR102559873B1 (ko) 시스템 인 패키지
CN105009279B (zh) 半导体器件及制造半导体器件的方法
CN106469706B (zh) 电子封装件及其制法
CN113169143B (zh) 半导体封装结构及其封装方法
US20230163077A1 (en) Electronic package
CN109256374B (zh) 电子封装件暨基板结构及其制法
CN109509728B (zh) 电子封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant