CN102157501B - 三维系统级封装结构 - Google Patents
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Abstract
一种三维系统级封装结构,包括:载板;位于载板上的至少两组封装组,所述封装组包括依次位于载板上的贴装层、封料层、布线层;位于顶部封装组上方的保护层,所述保护层设置有贯穿所述保护层的连接线,所述连接线连接于所述布线层;设置于所述保护层上,与所述连接线相连的连接球。本发明三维系统级封装结构实现了系统级功能的封装,并且具有复杂的多层互联结构,具有较高的集成度。
Description
技术领域
本发明涉及半导体技术,尤其涉及一种三维系统级封装结构。
背景技术
晶圆级封装(Wafer Level Packaging,WLP)技术是对整片晶圆进行封装测试后再切割得到单个成品芯片的技术,封装后的芯片尺寸与裸片完全一致。晶圆级芯片尺寸封装技术彻底颠覆了传统封装如陶瓷无引线芯片载具(Ceramic Leadless Chip Carrier)以及有机无引线芯片载具(Organic LeadlessChip Carrier)等模式,顺应了市场对微电子产品日益轻、小、短、薄化和低价化要求。经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微型化,芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。晶圆级芯片尺寸封装技术是可以将IC设计、晶圆制造、封装测试、基板制造整合为一体的技术,是当前封装领域的热点和未来发展的趋势。
扇出晶圆封装是晶圆级封装的一种。例如,中国发明专利申请第200910031885.0号公开一种晶圆级扇出芯片封装方法,包括以下工艺步骤:在载体圆片表面依次覆盖剥离膜和薄膜介质层I,在薄膜介质层I上形成光刻图形开口I;在图形开口I及其表面实现与基板端连接之金属电极和再布线金属走线;在与基板端连接之金属电极表面、再布线金属走线表面以及薄膜介质层I的表面覆盖薄膜介质层II,并在薄膜介质层II上形成光刻图形开口II;在光刻图形开口II实现与芯片端连接之金属电极;将芯片倒装至与芯片端连接之金属电极后进行注塑封料层并固化,形成带有塑封料层的封装体;将载体圆片和剥离膜与带有塑封料层的封装体分离,形成塑封圆片;植球回流,形成焊球凸点;单片切割,形成最终的扇出芯片结构。
按照上述方法所封装制造的最终产品仅具有单一的芯片功能。如需实现完整的系统功能,需要在最终产品之外加上包含有各种电容、电感或电阻等的外围电路。此外,上述方法也不适用于具有复杂线路连接的多层封装结构的制造。
发明内容
本发明解决的技术问题是提供一种集成度较高的三维系统级封装结构。
为解决上述技术问题,本发明提供一种三维系统级封装结构,包括:载板;位于载板上的至少两组封装组,所述封装组包括依次位于载板上的贴装层、封料层、布线层;位于顶部封装组上方的保护层,所述保护层设置有贯穿所述保护层的连接线,所述连接线连接于所述布线层;设置于所述保护层上,与所述连接线相连的连接球。
所述系统级封装结构包括两组封装组,包括:依次位于基板上的第一贴装层、第一封料层、一布线层,第二贴装层、第二封料层、第二布线层。
所述系统级封装结构还包括依次位于第二布线层上的第三贴装层、第三封料层、第三布线层。
所述保护层包括位于顶部封装组上的第一保护层和第二保护层,所述连接线包括贯穿于所述第一保护层的金属层布线层,覆盖于第一保护层上且与金属层布线层相连的层间布线层,贯穿第二保护层且连接于层间布线层的球下金属层。
所述连接线包括贯穿所述保护层的球下金属层。
所述布线层包括贯穿相应封装组的封料层的纵向布线,覆盖于相应封装组的封料层上,且连接于所述纵向布线的横向布线。
所述贴装层包括芯片和无源器件组。
所述保护层的材料为聚酰亚胺。
所述无源器件组包括电容、电阻和/或电感。
贴装层包括一个或多个相同或不同的芯片。
与现有技术相比,本发明具有以下优点:
1.整合了芯片和无源器件并一并封装,具有整体系统功能而非单一的芯片功能,相比现有的系统级封装,具有较高的集成度;
2.多层封装组所组成的立体封装结构,各层之间的布线层贯穿封料层实现电连接,具有复杂的多层互联结构,进一步提高了集成度。
附图说明
图1是本发明三维系统级封装结构一实施例的示意图;
图2是本发明三维系统级封装结构另一实施例的示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施的限制。
其次,本发明利用示意图进行详细描述,在详述本发明实施例时,为便于说明,所述示意图只是实例,其在此不应限制本发明保护的范围。
本发明提供一种三维系统级封装结构,包括:载板;位于载板上的至少两组封装组,所述封装组包括依次位于载板上的贴装层、封料层、布线层;位于顶部封装组上方的保护层,所述保护层设置有贯穿所述保护层的连接线,所述连接线连接于布线层;设置于保护层上,与所述连接线相连的连接球。所述三维系统级封装结构可以形成包含整体系统功能而非单一的芯片功能的最终封装产品,所述三维系统级封装结构降低了系统内电阻、电感等干扰因素,能顺应半导体封装轻薄短小的趋势要求,提高了三维系统级封装结构的集成度。
下面结合附图对本发明的具体实施例做详细的说明。
参考图1,示出了本发明三维系统级封装结构一个实施例的示意图。本实施例中所述三维系统级封装结构包括两组封装组,所述三维系统级封装结构包括:载板101,位于载板101上的胶合层102,贴附于胶合层102上的第一封装组105,堆叠于第一封装组105上的第二封装组106,位于第二封装组106上的第一保护层113,贯穿所述第一保护层113上的金属再布线层124,位于第一保护层113上第二保护层114,贯穿所述第二保护层114的球下金属层124;位于第二保护层114上,且与所述球下金属层124对应位置处的连接球114。其中,
载板101为承载后续第一封装组105以及后续各层封装组的基础,通常采用硅化合物材质制成,所述硅化合物中可设有金属线路以实现对最终产品的线路整理功能。当然,本领域技术人员了解,载板101也可根据设计需要采用玻璃材质以提供较好的硬度和平整度,在此不做限制。
胶合层102用于将第一封装组105固定在载板101上,可以通过诸如旋涂或印刷等方法将胶合层102涂覆在载板101上。这样的方法在半导体制造领域中已为本领域技术人员所熟知,在此不再赘述。
第一封装组105包括依次位于载板101上的第一贴装层107、第一封料层108和第一布线层109,其中,
第一贴装层107包括各种半导体器件,本实施例中,所述第一贴装层107包括芯片和无源器件,所述第一贴装层107功能面的相对面贴于胶合层102上,在本发明的具体实施方式中,所述第一贴装层107的功能面是指芯片的焊盘和无源器件的焊盘所在表面。
在本发明的一个优选的实施例中,所述第一贴装层107及后续的贴装层都可以包含一个或多个相同或不同芯片,还可以包括一个或多个相同或不同的无源器件。这些芯片和无源器件各自成为一个系统级封装产品的一部分,各自完成实现系统级功能中的一个或多个单独的功能。
在本发明的一个优选的实施例中,第一贴装层107中的芯片与无源器件的组合是根据系统功能来设计的。因此,在一个或一组芯片的周围,可能有相同或不同的另外的一个或一组芯片,或者相同或不同的电容、电阻和/或电感等无源器件;类似的,在一个无源器件的周围,可能有相同或不同的其他的无源器件,或者一个或多个相同或不同芯片。
第一封料层108填充于所述第一贴装层107各个器件之间,使第一贴装层107的芯片的焊盘和无源器件的焊盘裸露,在后续工艺过程中,第一封料层108既可保护第一贴装层107,又可作为后续工艺的承载体。具体地,第一封料层108的材料是环氧树脂。这种材料的密封性能好,塑型容易,是形成第一封料层108的较佳材料。形成第一封料层108的方法可以例如是转注、压缩或印刷的方法。这些方法的具体步骤已为本领域技术人员所熟知,在此不再赘述。
第一布线层109包括第一纵向布线和第一横向布线,所述第一纵向布线贯穿所述第一封料层108,用于连接第一贴装层107和其他贴装层,或者,根据设计需求,所述第一纵向布线还用于将第一封装组中和连接球115相连,所述第一横向布线连接于第一纵向布线,用于连接第一纵向布线和第一贴装层中的各个器件,所述第一贴装层中的各个器件可以依次通过第一横向布线、第一纵向布线与连接球115实现电连接。
所述第二封装组106堆叠于第一封装组105上,这里所说的堆叠,是指将第二芯片层置于第一封料层108上的预定位置处,所述第二封装组106的构成和第一封装组105的结构类似,包括依次位于第一封装组105上第二贴装层111、第二封料层112和第二布线层110。其中,所述第二贴装层111与第一贴装层107类似,同样包括多个半导体器件,本实施例中,所述第二贴装层111只包括芯片,第二封料层112覆盖于所述芯片露出的第二贴装层111上,部分第二封料层112覆盖于所述芯片上,所述第二封料层112裸露出所述芯片的焊盘,所述第二布线层110包括第二纵向布线和第二横向布线,所述第二纵向布线贯穿所述第二封料层112,用于连接第二贴装层111和其他各贴装层,所述第二横向布线覆盖于第二封料层112上,且连接于所述第二纵向布线。
所述三维系统级封装结构还包括位于第二封装组106上的第一保护层113,用于保护三维系统级封装结构,同时还起到隔离和绝缘的作用,具体地,所述第一保护层113的材料可以是聚酰亚胺。
所述第一保护层113中设置有贯穿所述第一保护层113的金属再布线层,所述金属再布线层设置于与所述第二横向布线对应的位置处,用于实现第二横向布线的功能性系统互联和走线。
所述第一保护层113上还覆盖有层间布线层,所述层间布线层覆盖于第一保护层113裸露出的金属再布线层上。
所述层间布线层上还覆盖有第二保护层114,具体地,所述第二保护层114的材料也可以是聚酰亚胺,所述第二保护层114中设置有贯穿所述第二保护层114的球下金属层,所述球下金属层设置于与层间布线层对应的位置处,与所述层间布线层相连。
所述球下金属层上设置有连接球115,所述连接球115的材料为导电材料,例如金属锡等。各封装组间通过布线层实现了相邻或相隔封装组间的互联,再依次经由第一保护层113和第二保护层114中的连接线实现了系统的整合,最终通过连接球115将功能输出。
在上述实施例中,贯穿所述第一保护层113的金属再布线层,覆盖于第一保护层113上的层间布线层,以及贯穿第二保护层114的球下金属层,构成贯穿保护层的连接线,从而实现封装组和连接球的电连接。
需要说明的是,本领域技术人员了解,层间布线层不是必须的。层间布线层是封装设计的需要,而非封装工艺的需要。在封装设计不需要层间布线层时,可以直接在最后一层芯片的电极或无源器件的焊盘上形成保护层,以及贯穿所述保护层的球下金属层,并在球下金属层对应位置的保护层表面形成连接球。
参考图2,示出了本发明三维系统级封装结构另一实施例的示意图。本实施例中,所述三维系统级封装结构包括三个封装组。具体地,所述三维系统级封装结构包括:载板201,位于载板201上的胶合层202,贴附于胶合层202上的第一封装组205,堆叠于第一封装组205上的第二封装组206,堆叠于第二封装组206上的第三封装组207,位于第三封装组207上的保护层213,贯穿所述保护层213的球下金属层224,位于保护层213上并且与所述球下金属层224上的连接球225。
本实施例与图1所述实施例相同的地方不再赘述,本实施与图1所示实施例的不同之处在于,还包括堆叠于第二封装组206上的第三封装组207,所述第三封装组207与第一封装组205和第二封装组206的结构类似,包括依次位于第二封装组206上的第三贴装层、第三封料层和第三布线层。其中,所述第三贴装层与第一贴装层、第二贴装层类似,同样包括多个半导体器件,本实施例中,所述第三贴装层只包括芯片。
此外,本实施例中,在第三封装组206上设置有保护层213,以及贯穿所述保护层213的球下金属层224,所述球下金属层224直接连接于第三布线层。所述三维系统级封装结构还包括保护层213上,并设置于与球下金属层224对应位置处的连接球225。
需要说明的是,在上述具体实施方式中,在第二封装组或第三封装组中仅示意出了芯片部分,但是本发明并不限于此,在每一层中都可以包括多个芯片和多个其他无源器件。
综上,本发明提供了一种集成度较高的三维系统级封装结构。
虽然本发明已以较佳实施例披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (9)
1.一种三维系统级封装结构,其特征在于,包括:载板;依次位于载板上的至少两组封装组,所述封装组包括:包括半导体器件的贴装层,填充于所述半导体器件之间且裸露出半导体器件的焊盘的封料层,由贯穿封料层用于实现不同贴装层之间电连接的纵向布线、覆盖于封料层上且与所述纵向布线相连的横向布线所构成的布线层;位于顶部封装组上方的保护层,所述保护层设置有贯穿所述保护层的连接线,所述连接线连接于所述布线层;设置于所述保护层上,与所述连接线相连的连接球。
2.如权利要求1所述的三维系统级封装结构,其特征在于,所述系统级封装结构包括两组封装组,包括:依次位于基板上的第一贴装层、第一封料层、一布线层,第二贴装层、第二封料层、第二布线层。
3.如权利要求2所述的三维系统级封装结构,其特征在于,所述系统级封装结构还包括依次位于第二布线层上的第三贴装层、第三封料层、第三布线层。
4.如权利要求1所述的三维系统级封装结构,其特征在于,所述保护层包括位于顶部封装组上的第一保护层和第二保护层,所述连接线包括贯穿于所述第一保护层的金属层布线层,覆盖于第一保护层上且与金属层布线层相连的层间布线层,贯穿第二保护层且连接于层间布线层的球下金属层。
5.如权利要求1所述的三维系统级封装结构,其特征在于,所述连接线包括贯穿所述保护层的球下金属层。
6.如权利要求1所述的三维系统级封装结构,其特征在于,所述贴装层包括芯片和无源器件组。
7.如权利要求1所述的三维系统级封装结构,其特征在于,所述保护层的材料为聚酰亚胺。
8.如权利要求6所述的三维系统级封装结构,其特征在于,所述无源器件组包括电容、电阻和/或电感。
9.如权利要求1所述的三维系统级封装结构,其特征在于,贴装层包括一个或多个相同或不同的芯片。
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