CN2664198Y - 多芯片封装结构 - Google Patents

多芯片封装结构 Download PDF

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CN2664198Y
CN2664198Y CNU032053568U CN03205356U CN2664198Y CN 2664198 Y CN2664198 Y CN 2664198Y CN U032053568 U CNU032053568 U CN U032053568U CN 03205356 U CN03205356 U CN 03205356U CN 2664198 Y CN2664198 Y CN 2664198Y
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chip
carrier
packaging structure
insulating barrier
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何昆耀
宫振越
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Via Technologies Inc
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Abstract

本实用新型公开一种多芯片封装结构，至少包括一承载器、至少一封装模块、一绝缘层及一图案化金属层。承载器具有一表面，而封装模块位于承载器的表面上，封装模块具有多个芯片，芯片为堆叠接合，而芯片之间可以利用倒装芯片的方式电连接。绝缘层位于承载器的表面上并包覆封装模块，绝缘层具有多个导通孔，导通孔连通至承载器及封装模块的表面，其中至少一导通孔垂直于承载器的表面的深度大于封装模块垂直于承载器的表面的高度。图案化金属层位于绝缘层上并填入于导通孔中，以作为本实用新型多芯片封装结构的内连线层。

Description

多芯片封装结构
技术领域
本实用新型有关一种多芯片封装结构，且特别是有关一种具有高电性效能的多芯片封装结构。
背景技术
在现今的资讯社会中，均追求高速度、高品质、多功能性的产品，而就产品外观而言，朝向轻、薄、短、小的趋势迈进。为了达到上述目的，现今许多公司在进行电路设计时，均融入系统化的概念，使得单一一颗芯片可以具备有许多功能，如此可以节省芯片配置在电子产品中的数目，而达到缩减电路体积的目的。另外，就电子封装技术而言，为了配合轻、薄、短、小的设计趋势，亦发展出多芯片模块(MCM)的封装设计概念、芯片尺寸封装(CSP)的封装设计概念及堆叠型多芯片封装设计的概念等。
接下来，介绍一种现有多芯片封装结构，如图1所示。多芯片封装结构100包括三芯片110、120、130、多层绝缘层140、142、144、146、三层金属层150、152、154及多个焊球160。芯片110、120、130分别具有多个芯片接垫114、124、134，位于芯片110、120、130的有源表面112、122、132上。
就工艺而言，芯片120先以其背面126并藉由一黏着材料170贴附于芯片110的有源表面112上，然后将绝缘层140形成于芯片110的有源表面112上并包覆芯片120，接着通过图案化绝缘层140的过程，分别形成多个导通孔141a、141b，暴露出芯片接垫114、124，然后形成金属层150于绝缘层140上并填入于导通孔141a、141b中，之后利用光刻蚀刻的方式图案化金属层150，接着形成绝缘层142于绝缘层140上，并覆盖金属层150。
接下来，将芯片130以其背面136并藉由一黏着材料172贴附于绝缘层142上，然后将绝缘层144形成于绝缘层142上并包覆芯片130，接着图案化绝缘层144、142，藉以形成多个导通孔144a、144b，分别暴露出金属层150及芯片接垫134。然后形成金属层152于绝缘层144上并填入于导通孔144a、144b中，之后可以利用光刻蚀刻的方式图案化金属层152，接着形成绝缘层146于绝缘层144上，并覆盖金属层152。接下来，通过图案化绝缘层146的步骤，可以形成多个开口147，暴露出金属层152，然后形成金属层154于绝缘层146上并填入于开口147中，之后可以利用光刻蚀刻的方式图案化金属层154。最后可以形成多个焊球160于金属层154上，藉此，多芯片封装结构100可以通过焊球160与一外界电路(未示出)电连接。
然而，在上述的多芯片封装工艺中，在芯片120堆叠于芯片110上之后，需形成绝缘层140、142及金属层150，使芯片110、120间电连接，而在芯片130贴覆于绝缘层142上之后，还必需形成绝缘层144、146及金属层152，藉以使芯片110、120、130间电连接。如上所述，每增加一块芯片于多芯片封装结构中，均需形成至少一层的绝缘层及金属层，并且其中的穿过各绝缘层的导通孔141a、144a的深度仅约为一个芯片的高度，因此就工艺而言，甚为耗时且不具效率性。
另外，芯片110、120、130之间需通过金属层150、152才能电连接，使得芯片110、120、130间的电性距离甚长，因而导致芯片110、120、130间的信号传输品质不佳。
实用新型内容
本实用新型的目的之一是提出一种多芯片封装结构及其工艺，由于芯片之间可以利用倒装芯片的方式电连接，因此可以大幅缩短芯片之间电连接的距离，故能够改善多芯片封装结构的信号传输品质。
本实用新型的目的之二是提出一种多芯片封装结构及其工艺，由于仅需在所有芯片接合于承载器上之后，才形成绝缘层及图案化金属层于承载器上，故仅需形成一层图案化金属层便可以制作完成多芯片封装的内连线，因此所需的工艺步骤较少，可以提高工艺的效率。
本实用新型的目的之三是提出一种多芯片封装结构及其工艺，其中部分芯片可先行完成封装及电气测试，确认为良好后再进行下一步骤的封装，可大幅提高多芯片封装产品的良率。
为达成本实用新型的上述目的，提出一种多芯片封装结构，至少包括一承载器、一具有堆叠芯片的多芯片封装模块、一绝缘层及一图案化金属层。承载器具有一表面，而封装模块位于承载器的表面上。绝缘层位于承载器的表面上并包覆封装模块，绝缘层具有多个导通孔，而导通孔连通至承载器的表面或封装模块，其中至少一导通孔的深度大于封装模块的高度。图案化金属层位于绝缘层上并填入于导通孔中，以作为多芯片封装结构的内连线层。
为达成本实用新型的上述目的，提出一种多芯片封装工艺，至少包括下列步骤。首先，提供至少一具有堆叠芯片的多芯片封装模块及一承载器，接着接合封装模块于承载器的一表面上。然后，形成一绝缘层于承载器的表面上，并包覆封装模块。之后，形成多个导通孔贯穿绝缘层并连通至承载器或封装模块。接着，形成一图案化金属层于绝缘层上并填入于导通孔中。
附图说明
为让本实用新型的上述目的、特征、和优点能更明显易懂，下文特举一优选实施例，并配合附图，作详细说明如下，其中：
图1示出现有多芯片封装结构的剖面示意图；
图2至图8示出依照本实用新型第一优选实施例的多芯片封装工艺的剖面示意图；
图9示出依照本实用新型第二优选实施例的多芯片封装结构的剖面示意图；
图10示出依照本实用新型第三优选实施例的多芯片封装结构的剖面示意图；以及
图11示出依照本实用新型第四优选实施例的多芯片封装结构的剖面示意图。
附图中的附图标记说明如下：
100：多芯片封装结构
110：芯片                 112：有源表面
114：芯片接垫             120：芯片
122：有源表面             124：芯片接垫
126：背面                 130：芯片
132：有源表面             134：芯片接垫
136：背面                 140：绝缘层
141a：导通孔             141b：导通孔
142：绝缘层              144：绝缘层
144a：导通孔             144b：导通孔
146：绝缘层              147：开口
150：金属层              152：金属层
154：金属层              160：焊球
170：黏着材料            172：黏着材料
200：多芯片封装结构
210：承载器              212：接垫
214：接垫                216：表面
220：封装模块            221：芯片
222：有源表面            225：凸块
226：绝缘层
230：封装模块            231：芯片
232：接垫                233：有源表面
236：芯片                237：接垫
238：接垫                239：有源表面
240：背面                241：黏着材料
242：凸块                243：接点
244：绝缘层
250：接点                252：凸块
254：凸块                260：绝缘层
262：导通孔              264：导通孔
270：金属层              280：绝缘层
282：开口                290：金属层
292：焊球
d：导通孔的深度
h：封装模块的高度
具体实施方式
图2至图8示出依照本实用新型第一优选实施例的多芯片封装工艺的剖面示意图。
请先参照图2，首先要提供一承载器210及二封装模块220、230，承载器210比如是芯片(有源元件)或是IC(集成电路)封装基板(如玻璃基板、陶瓷基板、塑胶基板等)，且该承载器210亦可内嵌无源元件，承载器210具有多个接垫212、214，位于承载器210的一表面216上，而多个接点250形成于承载器210的接垫212上，其中每一接点可以是由一个凸块或多个凸块所形成，视工艺的需求而定，本实施例示出堆叠两个凸块252、254而形成的接点250。或者，本实用新型亦可以省去接点250的配置。
封装模块220为一芯片尺寸封装(Chip Scaled Package；CSP)型态，具有一芯片221、多个凸块225及一绝缘层226，芯片221具有多个芯片接垫223，位于芯片221的有源表面222上，而凸块225接合在芯片接垫223上，绝缘层226位于芯片221的有源表面222上，并包覆凸块225。在封装模块220接合于承载器210之前，封装模块220可先完成电气测试以确定该芯片221为良好状态。
封装模块230为一多芯片堆叠式(Stacked chips)封装型态，本实施例中封装模块230具有二芯片231、236、多个凸块242、多个接点243、及一绝缘层244，芯片231具有多个接垫232，位于芯片231的有源表面233上，芯片236具有多个接垫237、238，位于芯片236的有源表面239上。芯片231藉由凸块242以倒装芯片方式连结于芯片236的接垫238上，并将绝缘层244形成于芯片231的有源表面233与芯片236之间，并包覆凸块242而完成二芯片231、236的堆叠。在芯片231接合于芯片236上之前或是之后，可以形成多个接点243于芯片236的接垫237上。并且，在封装模块230接合于承载器210的前，可藉由芯片236上的接点243，先行进行封装模块230的电气测试以确定在芯片231与芯片236结合后的运作是正常的。
接下来，请参照图3，将封装模块220以倒装芯片接合方式藉由凸块225接合到承载器210上，而封装模块230以芯片236的背面240藉由一黏着材料241贴覆于承载器210上。
接下来，请参照图4，比如可以利用旋涂或是热压合的方式，形成一绝缘层260于承载器210上，绝缘层260包覆封装模块220、230。接着，比如利用光刻蚀刻、激光钻孔或机械钻孔等方式，使绝缘层260形成多个导通孔262、264，导通孔262连通至承载器210的接垫212，且接点250位于导通孔262中，其中导通孔262垂直于承载器210的表面216的深度d大于封装模块230垂直于承载器210的表面216的高度h，即导通孔262的深度d大于二堆叠芯片的高度h。导通孔264连通至芯片236的接垫237，且接点243位于导通孔264中。
接下来，请参照图5，比如可以利用溅镀及电镀的方式，形成一金属层270于绝缘层260上，且金属层270还填入于导通孔262、264中，并与接点250、243连接。接着，比如利用光刻蚀刻的步骤，图案化金属层270。如此，芯片221、231、236及承载器210可以藉由接点243、250及图案化金属层270彼此电连接。
接下来，请参照图6，比如可以利用旋涂或是热压合的方式，形成一绝缘层280于绝缘层260上，绝缘层280覆盖金属层270。接着，比如利用光刻蚀刻的步骤，使绝缘层280形成多个开口282，暴露出部分金属层270。
接下来，请参照图7，形成一图案化金属层290于绝缘层280上，并填入于绝缘层280的开口282中，使金属层290与金属层270接触，以作为接垫。接下来，请参照图8，比如利用网板印刷的方式或植球的方式，形成焊球292于金属层接垫290上。至此，多芯片封装结构200便制作完成，而多芯片封装结构200可以通过焊球292与一外界电路电连接。
关于本实用新型实施例中的接点250及243形式并不限于此，可以根据导通孔形成及填塞金属的工艺能力，并配合导通孔深度而制作适合的接点，故接点可以是单一个凸块(如图9)，或是由多个凸块堆叠而成(如图8)，其中所述凸块可以是焊料凸块(solder bump)或锥形凸块(stud bump)。或者，接点亦可以是一个导电柱状凸块(column bump)(如图10)。或者，图案化金属层270可以直接与接垫212及237连接，而省略额外接点250及243的制作(如图11)。
根据本实用新型实施例，本实用新型结构上的重点之一在于多芯片封装结构的内连线结构中，导通孔的深度大于封装模块垂直于承载器的高度，而封装模块中的堆叠芯片数目并不限于二个，二个以上的芯片堆叠设置都属于本实用新型的范围，因此本实用新型中导通孔的深度大于二个以上芯片堆叠的高度。
结论
综上所述，本实用新型至少具有下列优点：
1.本实用新型的多芯片封装结构及其工艺，由于芯片之间可以利用倒装芯片的方式电连接，因此可以大幅缩短芯片之间电连接的距离，故能够改善多芯片封装结构的信号传输品质。
2.本实用新型的多芯片封装结构及其工艺，由于仅需在所有封装模块接合于承载器上之后，才形成绝缘层及图案化金属层于承载器上，故仅需形成一层图案化金属层便可以制作完成多芯片封装的内连线，因此相较于现有技术，本实用新型所需的工艺步骤较少，可以提高工艺的效率。
3.本实用新型的多芯片封装结构及其工艺，由于封装模块在接合于承载器之前，可先行电气测试，确认为良好状态后再进行下一步骤的封装，故可大幅提高多芯片封装产品的良率。
虽然本实用新型已以一优选实施例公开如上，但是其并非用以限定本实用新型，本领域技术人员在不脱离本实用新型的精神和范围的情况下，可作各种的更动与润饰，因此本实用新型的保护范围应以所附权利要求所确定的为准。

Claims (7)

1.一种多芯片封装结构，其特征在于，至少包括：
一承载器，具有一表面；
至少一封装模块，位于该承载器的该表面上，该封装模块具有多个芯片，该些芯片的至少二个为堆叠接合；
一绝缘层，位于该承载器的该表面上并包覆该封装模块，该绝缘层具有多个第一导通孔，该些第一导通孔连通至该承载器的该表面，该些第一导通孔垂直于该承载器的该表面的深度大于该封装模块垂直于该承载器的该表面的高度；以及
一图案化金属层，位于该绝缘层上并填入于该些第一导通孔中，作为该多芯片封装结构的内连线。
2.如权利要求1所述的多芯片封装结构，其特征在于，还包括多个接点，其位于该承载器的该表面上，并分别位于该些第一导通孔中，该图案化金属层通过该些接点与该承载器电连接。
3.如权利要求1所述的多芯片封装结构，其特征在于，该封装模块中的该些堆叠芯片以倒装芯片方式彼此连接。
4.如权利要求1所述的多芯片封装结构，其特征在于，该绝缘层具有多个第二导通孔，其连通至该封装模块的该些芯片的至少一个，该图案化金属层还填入于该些第二导通孔中。
5.如权利要求4所述的多芯片封装结构，其特征在于，还包括多个接点，其位于该些芯片的至少一个上，并且该些接点分别位于该些第二导通孔中，该图案化金属层通过该些接点与该些芯片的至少一个电连接。
6.如权利要求1所述的多芯片封装结构，其特征在于，该承载器为一芯片。
7.如权利要求1所述的多芯片封装结构，其特征在于，该承载器为一集成电路封装基板。
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