WO2015018144A1 - 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法 - Google Patents

先蚀后封芯片正装三维系统级金属线路板结构及工艺方法 Download PDF

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Publication number
WO2015018144A1
WO2015018144A1 PCT/CN2013/088317 CN2013088317W WO2015018144A1 WO 2015018144 A1 WO2015018144 A1 WO 2015018144A1 CN 2013088317 W CN2013088317 W CN 2013088317W WO 2015018144 A1 WO2015018144 A1 WO 2015018144A1
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Prior art keywords
metal
photoresist film
metal substrate
chip
conductive
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PCT/CN2013/088317
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English (en)
French (fr)
Inventor
梁新夫
梁志忠
林煜斌
王亚琴
张友海
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江苏长电科技股份有限公司
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Application filed by 江苏长电科技股份有限公司 filed Critical 江苏长电科技股份有限公司
Priority to DE112013007318.8T priority Critical patent/DE112013007318B4/de
Priority to US14/901,878 priority patent/US9640413B2/en
Publication of WO2015018144A1 publication Critical patent/WO2015018144A1/zh

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Definitions

  • the invention relates to a three-dimensional system-level metal circuit board structure and a process method for a pre-etched and post-sealed chip. It belongs to the field of semiconductor packaging technology. Background technique
  • the basic manufacturing method of the conventional metal lead frame has the following methods: under the bottom or from the bottom to the punching, the lead frame can form a base island carrying the chip in the metal piece, and the inner lead and the external PCB for signal transmission.
  • the external pins are connected, and then some areas of the inner leads and/or islands are coated with metal plating to form a truly usable lead frame (see Figure 76-78).
  • Another way is based on method one or method two, in the base island that has been attached with the chip, the inner pin of the signal transmission, the outer pin connected to the external PCB, and the inner bow I and Or)
  • the back surface of the lead frame formed by coating the metal plating layer is further coated with a high-temperature adhesive film resistant to 260 degrees Celsius, which becomes a lead for packaging which can be used in a four-sided leadless package and a reduced package volume. Box (see Figure 81).
  • Another way is to use method 1 or method 2, the base island with chip carrier, the inner pin of signal transmission, the outer pin connected to the external PCB, and the inner pin and/or island.
  • the lead frame formed by the metal plating coating is pre-encapsulated, and the metal piece is die-cut.
  • the chemically etched area is filled with a thermosetting epoxy resin, making it a pre-filled leadframe that can be used in a four-sided leadless package, shrink molded volume, and copper bond capability package (see Figure 82). .
  • Mechanical punching is to use the upper and lower cutters to form a vertical section from top to bottom or from bottom to top, so it is impossible to perform other functions or embedded objects inside the lead frame.
  • the system object is integrated in the metal lead. Box itself
  • Mechanical stamping is to use the upper and lower cutters to press the edge of the metal sheet to each other to extend along the metal region, and the length of the metal region to be extruded is at most 80% of the thickness of the lead frame. If the thickness of the wire I-frame is more than 80%, the metal area stretched by the extrusion is prone to warping, cracking, cracking, irregular shape and surface holes, and the ultra-thin lead frame is easier. The above problem occurs (see Figure 83 to Figure 84).
  • the subtractive etch can use a half-etch technique to etch the space that needs to be buried in the object, but the biggest disadvantage is that the depth dimension of the etched surface and the flatness of the etched plane are difficult to control.
  • the structural strength of the lead frame will become quite soft, which will directly affect the working conditions required for subsequent re-buried objects (such as pick-and-place, transportation, high temperature, The difficulty of high pressure and thermal stress shrinkage).
  • the lead frame of the chemical etching technology can only present the outer or inner leg of the front and back of the lead frame, and it is impossible to realize the system-level metal lead frame of the multi-layer three-dimensional metal circuit. Summary of the invention
  • the object of the present invention is to overcome the above deficiencies and to provide a three-dimensional system for pre-etching and post-sealing chips.
  • the structure and processing method of the metal circuit board can solve the function and application performance of the metal wire frame which cannot be buried in the traditional metal lead frame.
  • a method for pre-etching a post-sealed chip to mount a three-dimensional system-level metal circuit board comprising the following steps:
  • Step one taking a metal substrate
  • Step 2 Pre-plating a copper layer on the surface of the metal substrate
  • Step 3 Applying a photoresist film
  • a photoresist film capable of being exposed and developed is attached to the front surface and the back surface of the metal substrate on which the pre-plated micro copper layer is completed;
  • Step 4 removing a part of the photoresist film on the back surface of the metal substrate
  • step 3 Performing the method of exposing, developing and removing a portion of the patterned photoresist film on the back surface of the metal substrate on which the photoresist film is applied in step 3 by using an exposure and developing device to expose a region pattern of the back surface of the metal substrate after being electrically discharged;
  • Step five plating metal circuit layer
  • step 4 a metal wiring layer is plated in a region where a portion of the photoresist film is removed from the back surface of the metal substrate;
  • Step six paste the photoresist film operation
  • step 5 a photoresist film capable of exposure and development is attached to the back surface of the metal substrate;
  • Step 7 Remove a part of the photoresist film on the back side of the metal substrate
  • step 6 Performing the method of exposing, developing and removing a part of the pattern photoresist film on the back surface of the metal substrate on which the photoresist film is applied in step 6 by using an exposure and developing device to expose the area pattern of the back surface of the metal substrate after being electrically discharged;
  • Step 8 Electroplating a highly conductive metal circuit layer
  • Step IX Removing the photoresist film
  • Step ten epoxy resin plastic seal
  • the surface of the metal circuit layer on the back surface of the metal substrate is protected by an epoxy resin material;
  • Step 11 Surface polishing of the epoxy resin
  • Step 12 Applying a photoresist film
  • a photoresist film which can be exposed and developed is attached to the front and back surfaces of the metal substrate of the step 11;
  • Step 13 Remove a portion of the photoresist film on the front side of the metal substrate.
  • step 12 Forming, developing and removing a portion of the patterned photoresist film on the front side of the metal substrate on which the photoresist film is applied in step 12 by using an exposure developing device to expose a region pattern of the front surface of the metal substrate which needs to be etched;
  • Forming a metal layer on the front surface of the metal substrate in step 14 is completed, and after the metal layer is plated, the corresponding island upper portion and the upper portion of the pin are formed on the metal substrate;
  • Step 16 Apply photoresist to the film
  • a photoresist film which can be exposed and developed is attached to the front and back surfaces of the metal substrate of the fifteenth step;
  • Step 17 Remove a portion of the photoresist film on the front side of the metal substrate.
  • Step 18 plating metal pillars
  • step 17 the metal substrate is plated with a metal pillar in a region where a portion of the photoresist film is removed from the front surface of the metal substrate;
  • Step 19 remove the photoresist film
  • Step 20 coating the bonding substance Applying a conductive or non-conductive bonding substance to the front surface of the upper portion of the island formed in step 15; Step 21: Loading
  • Bonding wire work between the front side of the chip and the front side of the pin
  • the front side of the metal substrate in step 22 is plastically sealed with a molding compound
  • Step 23 plating the anti-oxidation metal layer or coating the antioxidant (OSP)
  • the metal exposed on the surface of the metal substrate after the completion of the step twenty-four is subjected to electroplating of an anti-oxidation metal layer or an emulsion (OSP).
  • OSP emulsion
  • step fifteen moves to between step four and step five.
  • a pre-etched and post-sealed chip-mounted three-dimensional system-level metal circuit board structure comprising a metal substrate frame, wherein a base island and a pin are disposed in the metal substrate frame, and the front or back side of the base island is electrically conductive or not
  • the conductive material is provided with a chip, and the front surface of the chip is connected with the front surface of the lead by a metal wire, and a conductive pillar is disposed on the front or back surface of the pin, and a region, a base island and a pin between the outer periphery of the base island
  • the area, the area between the pin and the pin, the area of the base island and the upper part of the pin, the area of the base island and the lower part of the pin, and the chip, the metal wire and the conductive post are all encapsulated with a molding compound, the molding compound It is flush with the top of the conductive pillar, and the surface of the metal substrate frame, the lead and the conductive pillar exposing the molding compound is plated
  • a pre-etched and post-sealed chip is mounted on a three-dimensional system-level metal circuit board structure, which comprises a metal substrate frame and a chip, and a pin is disposed in the metal substrate frame, and the chip is set by a conductive or non-conductive bonding substance
  • the front side of the chip and the front side of the lead are connected by a metal wire, and a conductive pillar is disposed on the front or back of the lead.
  • the area between the foot and the pin, the upper part of the pin, the area under the pin, and the chip, the metal wire and the conductive post are all encapsulated with a molding compound, and the molding compound is flush with the top of the conductive post.
  • the surface of the metal substrate, the leads and the conductive pillars exposing the molding compound is plated with anti-resistance Oxide layer or batch of antioxidant (OSP).
  • OSP anti-resistance Oxide layer or batch of antioxidant
  • the pin and the pin are connected to the passive device through a conductive bonding substance, and the passive device can be connected between the front surface of the pin and the front surface of the pin, or across the front surface of the pin and the electrostatic discharge ⁇ Between the front faces, or between the front surface of the electrostatic discharge port and the front surface of the island, an electrostatic discharge port is disposed between the base island and the pin, and between the front surface of the chip and the front surface of the electrostatic discharge port Connected by metal wires.
  • the conductive pillar has a plurality of turns.
  • a second chip is disposed on the front side of the chip by a conductive or non-conductive bonding material, and the front surface of the second chip is connected to the lead by a metal wire.
  • a second conductive post is disposed on the front side or the back side of the pin, and a second chip is mounted on the second conductive post by a conductive material, and the second conductive post and the second chip are inside the molding compound.
  • a second conductive post is disposed on the front side or the back side of the pin, and a passive device is mounted on the second conductive post, and the second conductive post and the passive device are inside the molding compound.
  • a method for pre-etching and post-sealing a chip to mount a three-dimensional system-level metal circuit board comprising the following steps:
  • Step one taking a metal substrate
  • Step 2 Pre-plating a copper layer on the surface of the metal substrate
  • Step 3 Applying a photoresist film
  • a photoresist film capable of being exposed and developed is attached to the front surface and the back surface of the metal substrate on which the pre-plated micro copper layer is completed;
  • Step 4 removing a part of the photoresist film on the front side of the metal substrate
  • step 3 Forming, exposing, developing and removing a portion of the patterned photoresist film on the front side of the metal substrate on which the photoresist film is applied in step 3 by using an exposure and developing device to expose a region pattern of the front surface of the metal substrate after being electrically discharged;
  • Step five electroplating the first metal circuit layer
  • Step six paste the photoresist film operation
  • step 5 the front surface of the metal substrate is pasted with a photoresist film that can be exposed and developed;
  • Step 7 Remove a portion of the photoresist film on the front side of the metal substrate.
  • the surface of the metal substrate on which the photoresist film is applied in step 6 is subjected to pattern exposure, development and removal of a portion of the patterned photoresist film by exposing the developing device to expose a region pattern of the front surface of the metal substrate which needs to be electrically operated;
  • Step eight electroplating the second metal circuit layer
  • Step IX Removing the photoresist film
  • Step 10 pressing the non-conductive film operation
  • Step XI grinding the surface of the non-conductive film
  • Step 12 Non-conductive film surface metallization pretreatment
  • Step XIII sticking photoresist film operation
  • step 12 the front and back sides of the metal substrate are pasted with a photoresist film capable of being exposed and developed; Step 14: removing a part of the photoresist film on the front side of the metal substrate
  • Step 16 Remove the photoresist film on the front side of the metal substrate
  • Step 17 Electroplating the third metal circuit layer Performing the plating operation of the third metal circuit layer on the front side of the metal substrate in step sixteen; Step 18: Applying the photoresist film
  • Step 19 removing a part of the photoresist film on the front surface of the metal substrate
  • Step 20 electroplating the fourth metal circuit layer
  • step 19 a fourth metal circuit layer is plated in a region of the front surface of the metal substrate from which a portion of the photoresist film is removed as a conductive pillar for connecting the third metal circuit layer and the fifth metal circuit layer; Step 21: Removing the photoresist Membrane
  • Step 22 pressing the non-conductive film operation
  • Step 23 Grinding the surface of the non-conductive film
  • Step 24 Non-conductive film surface metallization pretreatment
  • step 24 the front and back sides of the metal substrate are pasted with a photoresist film capable of being exposed and developed; Step 26: removing a portion of the photoresist film on the front side of the metal substrate
  • the surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by using an exposure developing device to expose a pattern of a region to be etched on the front surface of the metal substrate; Etching operation
  • Step 28 Removing the photoresist film on the front side of the metal substrate
  • Step twenty-nine electroplating the fifth metal circuit layer Performing a plating operation of the fifth metal circuit layer on the front surface of the metal substrate in the twenty-eighth step, and forming a corresponding island and a pin on the metal substrate after the fifth metal circuit layer is plated;
  • Step 30 paste the photoresist film operation
  • step 29 the front surface of the metal substrate is pasted with a photoresist film capable of being exposed and developed; Step 31: removing a part of the photoresist film on the back surface of the metal substrate
  • step 30 Forming, developing and removing a portion of the patterned photoresist film on the back surface of the metal substrate on which the photoresist film is applied in step 30 by using an exposure and developing device to expose a region pattern which is subsequently etched on the back surface of the metal substrate;
  • step 31 The region in which the back surface of the metal substrate is exposed and developed in step 31 is chemically etched and chemically etched until the metal wiring layer;
  • Step thirty-three paste the photoresist film operation
  • a photoresist film which can be exposed and developed is attached to the back surface of the metal substrate which is chemically etched in step 32;
  • Step 34 Removing a portion of the photoresist film on the back side of the metal substrate
  • Step 35 plating metal pillars
  • Step 36 Remove the photoresist film
  • Step 37 Coating the bonding substance
  • Step 38 Loading
  • Step 39 metal wire bonding Bonding the wire between the front side of the chip and the back side of the pin;
  • the back surface of the metal substrate in step 39 is plasticized with an epoxy resin (commonly known as a molding compound);
  • Step 40 Electroplating of the anti-oxidation metal layer or coating of antioxidant (OSP)
  • the metal exposed on the surface of the metal substrate after the completion of the step 41 is subjected to electroplating of an anti-oxidation metal layer or an emulsion (OSP).
  • OSP emulsion
  • the steps 6 through 17 can be repeated to form more layers of metal circuit layers.
  • the present invention has the following beneficial effects:
  • the metal lead frame is mechanically punched or chemically etched, and a multilayer metal circuit layer cannot be fabricated, and any object cannot be buried in the interlayer between the punched metal lead frames, and the three-dimensional object of the present invention
  • the metal line composite substrate can embed an object in a sandwich in the middle of the substrate.
  • the interlayer in the three-dimensional metal circuit composite substrate can be buried in the required position or area due to heat conduction or heat dissipation, and becomes a thermal performance system-level metal lead frame. (See Figure 87)
  • the interlayer in the three-dimensional metal circuit composite substrate can be embedded into the active component or component or passive component in the required position or area due to system and function requirements, and becomes a system-level metal lead frame.
  • the finished product of the three-dimensional metal circuit composite substrate itself is rich in various components. If the subsequent second packaging is not carried out, the three-dimensional metal circuit composite substrate is cut according to each cell, and itself It can be an ultra-thin package.
  • the three-dimensional metal circuit composite substrate can be secondarily packaged in addition to the embedded function of the object itself, and fully integrates the system functions. 7) The three-dimensional metal circuit composite substrate can be superimposed with different unit packages or system-level packages on the periphery of the package in addition to the embedded function of the embedded object, which fully realizes the dual-system or multi-system-level packaging technology capability. .
  • the three-dimensional metal circuit substrate can be applied to a multi-chip module (MCM) package (see Fig. 88 and Fig. 89), and the three-dimensional metal circuit substrate has lower cost and higher toughness than the conventional MCM substrate substrate.
  • MCM multi-chip module
  • 1 to 25 are schematic views showing the steps of a method for fabricating a three-dimensional system-level metal circuit board for a pre-etched and post-sealed chip.
  • Fig. 26 is a schematic view showing the first embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip in the present invention.
  • Fig. 27 is a schematic view showing the second embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip in the present invention.
  • Fig. 28 is a schematic view showing the third embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip in the present invention.
  • Fig. 29 is a schematic view showing the fourth embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip in the present invention.
  • Figure 30 is a schematic view showing the fifth embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip in the present invention.
  • FIG. 31 and FIG. 32 are schematic views showing Embodiment 6 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip.
  • Embodiment 7 of a three-dimensional system-level metal wiring board structure of a pre-etched and post-sealed chip.
  • Fig. 75 is a schematic view showing the seventh embodiment of the three-dimensional system-level metal circuit board structure of the pre-etched and post-sealed chip.
  • Fig. 76 is a schematic view showing the punching process in the basic manufacturing process of the conventional metal lead frame.
  • Fig. 77 is a schematic view showing a strip-shaped metal piece in a basic manufacturing process of a conventional metal lead frame.
  • Figure 78 is a schematic view of the front lead frame in the basic fabrication process of a conventional metal lead frame.
  • Figure 79 is a schematic view showing a cross section of a conventional metal lead frame subjected to exposure, development, windowing, etching, and the like.
  • Figure 80 is a schematic illustration of a front lead frame in a basic fabrication process of a conventional metal lead frame.
  • Figure 81 is a cross-sectional view showing the structure of a QFN in the basic manufacturing process of a conventional metal lead frame.
  • Figure 82 is a schematic view of a pre-filled lead frame in a basic fabrication process of a conventional metal lead frame.
  • Figure 83 is a schematic view showing the extrusion of the upper and lower cutters to form an extended metal region in the basic manufacturing process of the conventional metal lead frame.
  • Figure 84 is a schematic view showing the crack, break, and warp caused by the extrusion of the upper and lower cutters to form an extended metal region in the basic manufacturing process of the conventional metal lead frame.
  • Fig. 85 is a schematic view showing the basic manufacturing process of the conventional metal lead frame in which the upper and lower cutters are pressed to form a length of the lead metal frame which is less than 80% of the thickness of the lead frame.
  • Fig. 86 is a schematic view showing the difficulty in embedding an object in the basic manufacturing process of the conventional metal lead frame in which the upper and lower cutters are extruded to form an object which is less than 80% of the thickness of the lead frame.
  • Figure 87 is a schematic diagram of a sandwich in a three-dimensional metal-line composite substrate in which a heat-conducting or heat-dissipating object can be buried in a desired position or region due to heat conduction or heat dissipation.
  • Figure 88 is a schematic diagram of a three-dimensional metal circuit substrate applied to a multi-chip module (MCM) package.
  • Figure 89 is a plan view of Figure 88.
  • Metal substrate frame 1 base island 2, pin 3, conductive or non-conductive bonding substance 4, chip 5, metal wire 6, conductive pillar 7, molding compound 8, oxidation resistant layer or batch of antioxidant 9, passive device 10
  • the technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • the invention discloses a three-dimensional system-level metal circuit board structure and a process method for a pre-etched and post-sealed chip package: 3 ⁇ 4 under:
  • Embodiment 1 Single-layer line single-chip mounted single-pin pin
  • FIG. 26 it is a schematic structural view of a first embodiment of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, which comprises a metal substrate frame 1 in which a base island 2 and a pin are disposed.
  • the front side of the island 2 is provided with a chip 5 through a conductive or non-conductive bonding material 4, and the front surface of the chip 5 and the front surface of the pin 3 are connected by a metal wire 6, and the front side of the pin 3 is disposed
  • Conductive column 7, the area around the island 2, the area between the island 2 and the pin 3, the area between the pin 3 and the pin 3, the area of the island 2 and the upper part of the pin 3, the island 2 and the lower portion of the lead 3 and the chip 5, the metal wire 6 and the conductive post 7 are both encapsulated with a molding compound 8 which is flush with the top of the conductive post 7 on the metal substrate 1, the base
  • the surface of the island 2, the lead 3 and the conductive post 7 exposing the molding compound 8 is plated with an oxidation resistant layer or an overlying antioxidant (OSP) 9.
  • OSP overlying antioxidant
  • Step one taking a metal substrate
  • a metal substrate of suitable thickness is taken.
  • the purpose of the plate is only for the transition material used in the circuit fabrication and subsequent packaging support circuit layer structure.
  • the material of the plate is mainly metal material, and the metal material is mainly used.
  • the material can be copper, iron, plated, stainless steel, aluminum or metal or non-all metal materials that can achieve electrical conductivity.
  • Step 2 Pre-plating a copper layer on the surface of the metal substrate
  • a micro-copper layer is pre-plated on the surface of the metal substrate, and the thickness of the micro-copper layer is 2 to 10 micrometers, which can be thinned or thickened according to functional requirements, mainly for enabling the circuit layer and the metal substrate during subsequent circuit fabrication.
  • the plating can be performed by chemical deposition or electrolytic plating.
  • a photoresist film which can be exposed and developed is attached to the front and back surfaces of the metal substrate on which the pre-plated micro copper layer is completed, to protect the subsequent metal plating process, and the photoresist film may be a dry photoresist film. It may be a wet photoresist film.
  • Step 4 removing a part of the photoresist film on the back surface of the metal substrate
  • step 3 the back surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development, and removal of a portion of the pattern photoresist film by exposing the surface of the metal substrate to expose the area pattern to be electroplated.
  • Step five plating metal circuit layer
  • a metal wiring layer is plated in a region where a part of the photoresist film is removed from the back surface of the metal substrate, and the metal wiring layer material may be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold. (usually 5 ⁇ 20 microns, the thickness of the plating can be changed according to different characteristics), etc.
  • the plating method may be chemical deposition or electrolytic plating.
  • Step six paste the photoresist film operation
  • a photoresist film which can be exposed and developed is attached to the back surface of the metal substrate, and the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 7 Remove a part of the photoresist film on the back side of the metal substrate
  • the surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development, and removal of a portion of the patterned photoresist film by exposing the surface of the metal substrate to expose the area pattern of the subsequent plating.
  • Step 8 Electroplating a highly conductive metal circuit layer
  • a high-conductivity metal circuit layer is plated in a region where a part of the photoresist film is removed from the back surface of the metal substrate, and the material of the high-conductivity metal circuit layer may be copper, aluminum, nickel, silver, gold, copper, silver or nickel gold. , nickel palladium gold and other materials, of course, other conductive metal materials can be used, not limited to copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium and other metal materials, electroplating can make chemical deposition Or electrolytic plating. Step IX. Removing the photoresist film
  • the photoresist film on the surface of the metal substrate is removed.
  • the method of removing the photoresist film can be softened by chemical syrup and rinsed with high-pressure water to remove the photoresist film.
  • the surface of the metal circuit layer and the high-conductivity metal circuit layer on the back surface of the metal substrate is protected by an epoxy resin material.
  • the epoxy resin material can be selected according to the product characteristics with or without a filler.
  • the plastic sealing method can be adopted. Mold filling method, spraying equipment spraying method, film coating method or brushing method.
  • the surface of the epoxy resin is polished after the completion of the epoxy resin molding, in order to expose the high conductive metal circuit layer for the outer leg function to the surface of the plastic body and to control the thickness of the epoxy resin.
  • Step 12 Applying a photoresist film
  • a photoresist film which can be exposed and exposed is attached to the front and back surfaces of the metal substrate which is completed in step 11.
  • the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 13 Remove a portion of the photoresist film on the front side of the metal substrate.
  • the front surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose a region pattern which is subsequently etched on the front surface of the metal substrate.
  • the region in which the front side of the metal substrate is exposed and developed in step 13 is chemically etched, and chemically etched up to the metal wiring layer.
  • the etching solution may be copper chloride or ferric chloride or a chemically etchable syrup.
  • the metal layer is plated on the front surface of the metal substrate in step 14. After the metal layer is plated, the corresponding island upper portion and the upper portion of the lead are formed on the metal substrate.
  • the metal circuit layer material may be copper, aluminum or nickel. , silver, gold, copper silver, nickel gold, nickel palladium and other materials, of course, other conductive metal materials can be used, not limited to copper, aluminum, nickel, silver, gold, copper, silver, nickel Metal materials such as gold and nickel palladium can be electroplated or electroplated.
  • Step 16 Apply photoresist to the film
  • a photoresist film which can be exposed and exposed is attached to the front and back surfaces of the metal substrate of the fifteenth step.
  • the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 17 Remove a portion of the photoresist film on the front side of the metal substrate.
  • the front surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose the area pattern of the front surface of the metal substrate which needs to be plated.
  • Step 18 plating metal pillars
  • a portion of the photoresist film is partially plated with a metal pillar.
  • the material of the metal pillar may be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold.
  • Other materials of course, other conductive metal materials can be used, not limited to copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium and other metal materials, plating methods can be chemical deposition or electrolytic plating the way.
  • Step 19 remove the photoresist film
  • the photoresist film on the surface of the metal substrate is removed, and the method of removing the photoresist film can be softened by chemical syrup and washed by high-pressure water to remove the photoresist film.
  • a conductive or non-conductive bonding substance is applied to the front surface of the upper portion of the island formed in step fifteen, in order to bond the base island after the subsequent chip implantation.
  • the chip is implanted on the conductive or non-conductive bonding material of step twenty.
  • a bonding wire operation is performed between the front surface of the chip and the front surface of the lead.
  • the material of the metal wire is made of gold, silver, copper, aluminum or alloy.
  • the shape of the wire may be filament or It is a ribbon.
  • the front side of the metal substrate in step 22 is plastically sealed with a molding compound.
  • the sealing method may be a mold filling method, a spraying device spraying method or a film coating method, and the molding material may be an epoxy resin having a filler material or a filler-free material.
  • the surface of the epoxy resin is ground after the epoxy resin molding of step 23 is completed, in order to expose the metal pillar to the surface of the molding body and control the thickness of the epoxy resin.
  • Step 25 Electroplating of an Antioxidant Metal Layer or Coating Antioxidant (OSP)
  • the metal exposed on the surface of the metal substrate after the completion of step twenty-four is electroplated with an anti-oxidation metal layer to prevent metal oxidation such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP). .
  • an anti-oxidation metal layer to prevent metal oxidation such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP).
  • FIG. 27 is a schematic structural diagram of Embodiment 2 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, and Embodiment 2 differs from Embodiment 1 in that: the conductive pillar 7 has a plurality of turns.
  • the passive device 10 is connected by a conductive bonding substance, and an electrostatic discharge port 11 is disposed between the base island 2 and the pin 3, and the electrostatic discharge port 11 is front and the chip 5, the front side is connected by a metal line 6, the passive device 10 can be connected between the front side of the lead 3 and the front side of the lead 3, or across the front side of the lead 3 and the front side of the electrostatic discharge ⁇ 11, Or across the front of the island 2 and the front of the electrostatic discharge ⁇ 11.
  • FIG. 28 is a schematic structural diagram of Embodiment 3 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip.
  • the difference between Embodiment 3 and Embodiment 1 is that the base island 2 has a plurality of The base island 2 is provided with a chip 5 through a conductive or non-conductive bonding material 4, and the front surface of the chip 5 is connected to the front surface of the chip 5 by a metal wire 6.
  • Embodiment 4 single stack stacked multi-chip positive dress
  • FIG. 29 is a schematic structural diagram of Embodiment 4 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, and Embodiment 4 differs from Embodiment 1 in that: the front side of the chip 5 is electrically conductive or not.
  • the conductive bonding material 4 is provided with a second chip 12, and the front surface of the second chip 12 and the lead 3 are connected by a metal wire 6.
  • FIG. 30 is a schematic structural diagram of Embodiment 5 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, and Embodiment 5 is different from Embodiment 1 in that: A second conductive pillar 13 is mounted on the second conductive pillar 13 by a conductive material 14 and the second conductive chip 13 and the second chip 12 are inside the molding compound 8.
  • FIG. 31 is a schematic structural diagram of Embodiment 6 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, and Embodiment 6 is different from Embodiment 1 in that: the metal circuit board structure does not include The island 2, the chip 5 is disposed between the front side of the metal substrate 1 or the front side of the lead 3 and the front side of the lead 3 via a conductive or non-conductive bonding substance 4.
  • Embodiment 7 multi-layer line single-chip dressing single-turn pin
  • FIG. 75 is a schematic structural diagram of Embodiment 7 of a three-dimensional system-level metal circuit board structure of a pre-etched and post-sealed chip, and Embodiment 7 is different from Embodiment 1 in that: the base island 2 or the pin 3 includes a plurality of metal circuit layers, two adjacent metal circuit layers are connected by conductive pillars, and a back surface of the island 2 is provided with a chip 5 through a conductive or non-conductive bonding material 4, and a back surface of the pin 3 is disposed Conductive column 7.
  • Step one taking a metal substrate
  • a metal substrate of suitable thickness is used.
  • the purpose of the plate is only for the transition material used in the circuit fabrication and subsequent packaging support circuit layer structure.
  • the material of the plate is mainly metal material, and the metal material is mainly used.
  • the material can be copper, iron, plated, stainless steel, aluminum or metal or non-metallic materials that can achieve electrical conductivity.
  • Step 2 Pre-plating a copper layer on the surface of the metal substrate
  • a micro-copper layer is pre-plated on the surface of the metal substrate, and the thickness of the micro-copper layer is 2 to 10 micrometers, which can be thinned or thickened according to functional requirements, mainly for enabling the circuit layer and the metal substrate in the subsequent circuit fabrication.
  • the plating can be performed by chemical deposition or electrolytic plating.
  • Step 3 Applying a photoresist film
  • the front and back sides of the metal substrate on which the pre-plated micro copper layer is completed can be respectively attached.
  • the developed photoresist film is exposed to protect the subsequent plating metal layer process, and the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 4 removing a part of the photoresist film on the front side of the metal substrate
  • the front surface of the metal substrate to which the photoresist film is applied is subjected to pattern exposure, development, and removal of a portion of the pattern resist film by the exposure developing device to expose the area pattern of the front surface of the metal substrate to be electroplated.
  • Step five electroplating the first metal circuit layer
  • a first metal circuit layer is plated in a region where a portion of the photoresist film is removed from the front surface of the metal substrate, and the first metal circuit layer material may be copper, aluminum, nickel, silver, gold, copper silver, or nickel gold.
  • Nickel-palladium gold usually 5 ⁇ 20 microns, which can change the thickness of plating according to different characteristics, etc.
  • other conductive metal materials can be used, which are not limited to copper, aluminum, nickel, silver, gold, copper and silver.
  • Metal materials such as nickel gold and nickel palladium may be electroplated or electrolytically plated.
  • Step six paste the photoresist film operation
  • a photoresist film that can be exposed and developed is attached to the front surface of the metal substrate, and the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 7 Remove a portion of the photoresist film on the front side of the metal substrate.
  • step 6 the front surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development, and removal of a portion of the pattern photoresist film by exposing the surface of the metal substrate to expose the area pattern of the metal substrate.
  • Step eight electroplating the second metal circuit layer
  • a second metal wiring layer is plated in a region where a portion of the photoresist film is removed from the front surface of the metal substrate as a conductive pillar for connecting the first metal wiring layer and the third metal wiring layer, and a material of the metal wiring layer. It can be made of copper, nickel gold, nickel palladium gold, silver, gold or tin metal. Electroplating can be carried out by chemical deposition or electrolytic plating.
  • Step IX Removing the photoresist film
  • the photoresist film on the surface of the metal substrate is removed, and the purpose is to carry out the operation of the non-conductive film.
  • the method of removing the photoresist film can be softened by chemical water and washed by high-pressure water to remove the photoresist film.
  • Step 10 pressing the non-conductive film operation
  • a non-conductive film is pressed on the front surface of the metal substrate (the area having the circuit layer), and the purpose is to insulate the first metal circuit layer from the third metal circuit layer, and press the non-conductive film. It can be pressed by conventional rolling equipment or under vacuum to prevent air residue during the pressing process.
  • the non-conductive film is mainly thermosetting epoxy resin, and the epoxy resin can be used according to product characteristics. There is no filler or a non-conductive film with a filler. The color of the epoxy resin can be dyed according to the characteristics of the product.
  • Step XI grinding the surface of the non-conductive film
  • surface grinding is performed after the non-conductive film is pressed, in order to expose the second metal wiring layer, maintain the flatness of the non-conductive film and the second metal wiring layer, and control the thickness of the non-conductive film.
  • Step 12 Non-conductive film surface metallization pretreatment
  • the surface of the non-conductive film is subjected to metallization pretreatment, and a metallized polymer material is adhered on the surface thereof, so as to be a catalyst conversion which can be plated as a subsequent metal material, and the metallized polymer material can be attached. Spraying, plasma oscillating, roughening, etc. can be dried again;
  • Step XIII sticking photoresist film operation
  • a photoresist film which can be exposed and developed is attached to the front and back surfaces of the metal substrate to protect the subsequent plating process of the third metal circuit layer, and the photoresist film may be a dry photoresist film. It may be a wet photoresist film.
  • Step 14 Remove a portion of the photoresist film on the front side of the metal substrate.
  • the front surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose a region pattern which is subsequently etched on the front surface of the metal substrate.
  • Step fifteen etching operation Referring to FIG. 47, an etching operation is performed in the region after the window opening of the photoresist film is completed in step 14.
  • the purpose of etching is to clean the metal region other than the metal line to be preserved, and the etching may be copper chloride or ferric chloride. Or a process that can be chemically etched.
  • Step 16 Remove the photoresist film on the front side of the metal substrate
  • the photoresist film on the front side of the metal substrate is removed to expose a pattern of metal regions to be subsequently plated.
  • Step 17 Electroplating the third metal circuit layer
  • the third metal circuit layer is plated on the front side of the metal substrate in step 16.
  • the material of the third metal circuit layer may be copper, nickel gold, nickel palladium gold, silver, gold or tin metal. It may be chemical deposition plus electrolytic plating or all of the required thicknesses by chemical deposition.
  • Step 18 Applying a photoresist film
  • a photoresist film which can be exposed and developed is attached to the front surface of the metal substrate in step 17 for the purpose of fabricating a subsequent metal wiring layer.
  • the photoresist film may be a dry photoresist film or a wet photoresist film. .
  • Step 19 Removing a portion of the photoresist film on the front side of the metal substrate
  • the front surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose the area pattern of the front surface of the metal substrate which needs to be plated.
  • Step 20 electroplating the fourth metal circuit layer
  • a fourth metal circuit layer is plated in a region where a portion of the photoresist film is removed from the front surface of the metal substrate in step 19 as a conductive pillar for connecting the third metal wiring layer and the fifth metal wiring layer, and the metal wiring layer.
  • the material can be copper, nickel gold, nickel palladium gold, silver, gold or tin metal.
  • the plating method can be chemical deposition or electrolytic plating.
  • Step 21 remove the photoresist film
  • the photoresist film on the surface of the metal substrate is removed, and the purpose is to carry out the operation of the non-conductive film.
  • the method of removing the photoresist film can be softened by chemical syrup and washed by high-pressure water to remove the photoresist film. Step 22, pressing the non-conductive film operation
  • a non-conductive film is pressed on the front surface of the metal substrate (the area having the wiring layer), and the purpose is to insulate the third metal circuit layer from the fifth metal circuit layer, and press the non-conductive film. It can be pressed by conventional rolling equipment or under vacuum to prevent air residue during the pressing process.
  • the non-conductive film is mainly thermosetting epoxy resin, and the epoxy resin can be used according to product characteristics. There is no filler or a non-conductive film with a filler. The color of the epoxy resin can be dyed according to the characteristics of the product.
  • Step 23 Grinding the surface of the non-conductive film
  • surface grinding is performed after the non-conductive film is pressed, in order to expose the fourth metal circuit layer, maintain the flatness of the non-conductive film and the fourth metal circuit layer, and control the thickness of the non-conductive film.
  • Step 24 Non-conductive film surface metallization pretreatment
  • the surface of the non-conductive film is subjected to metallization pretreatment, and a metallized polymer material is adhered on the surface thereof, so as to be a catalyst conversion which can be plated by the subsequent metal material, and the metallized polymer material can be attached.
  • Spraying, plasma oscillating, roughening, etc. can be dried again;
  • a photoresist film capable of exposure and development is attached to the front and back surfaces of the metal substrate to protect the subsequent fifth metal circuit layer plating process, and the photoresist film may be a dry photoresist film. It can also be a wet photoresist film.
  • Step twenty-six removing part of the photoresist film on the front side of the metal substrate
  • the surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose the area pattern which needs to be etched on the front side of the metal substrate.
  • an etching operation is performed in the area after the photoresist film is opened in step 26.
  • the purpose of etching is to clean the metal region other than the metal line to be preserved, and the etching may be copper chloride or chlorination. Iron or a process that can be chemically etched.
  • Step 28 Removing the photoresist film on the front side of the metal substrate
  • the photoresist film on the front side of the metal substrate is removed to expose a pattern of metal regions to be subsequently plated.
  • Step twenty-nine electroplating the fifth metal circuit layer
  • the fifth metal circuit layer is plated on the front side of the metal substrate in step 28. After the fifth metal circuit layer is plated, the corresponding island and pin are formed on the metal substrate, and the fifth metal circuit layer is formed.
  • the material may be copper, nickel gold, nickel palladium gold, silver, gold or tin metal.
  • the plating method may be chemical deposition or electrolytic plating or all of the required thickness by chemical deposition.
  • Step 30 paste the photoresist film operation
  • the front surface of the metal substrate is coated with a photoresist film which can be exposed and developed.
  • the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 31 Removing a portion of the photoresist film on the back side of the metal substrate
  • the back surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose a region pattern which is subsequently etched on the back surface of the metal substrate.
  • the area of the back surface of the metal substrate in step 31 is chemically etched and chemically etched until the metal circuit layer.
  • the etching solution may be copper chloride or ferric chloride or a chemically etchable syrup. .
  • Step thirty-three paste the photoresist film operation
  • a photoresist film which can be exposed and developed is attached to the back surface of the metal substrate which is chemically etched in step 32.
  • the photoresist film may be a dry photoresist film or a wet photoresist film.
  • Step 34 Removing a portion of the photoresist film on the back side of the metal substrate
  • the back surface of the metal substrate on which the photoresist film is applied is subjected to pattern exposure, development and removal of a portion of the pattern photoresist film by the exposure developing device to expose the area pattern of the back surface of the metal substrate which needs to be plated.
  • Step 35 plating metal pillars
  • a metal pillar is plated in a region where a part of the photoresist film is removed from the back surface of the metal substrate, and the material of the metal pillar may be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium.
  • Gold and other materials of course, other conductive metal materials can be used, not limited to copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium and other metal materials, plating can make chemical deposition or electrolysis Plating method.
  • Step 36 Remove the photoresist film
  • the photoresist film on the surface of the metal substrate is removed, and the photoresist film can be removed by chemical water softening and high pressure water spray.
  • Step 37 Coating the bonding substance
  • the back side of the island formed in step 29 is coated with a conductive or non-conductive bonding substance for the purpose of bonding the base island after the subsequent chip implantation.
  • the chip is implanted on the back side of the island at step thirty-seven.
  • a bonding wire operation is performed between the front surface of the chip and the front surface of the lead.
  • the material of the metal wire is made of gold, silver, copper, aluminum or alloy.
  • the shape of the wire may be filamentary or It is a ribbon.
  • the back surface of the metal substrate in step 39 is plastically sealed by a molding compound
  • the plastic sealing method may be a mold filling method, a spraying device spraying method, a film coating method or a brushing method, and the molding material may be used. Epoxy resin with or without filler material.
  • the surface of the epoxy resin is ground after the epoxy resin molding of step 40 is completed, so that the metal pillar is exposed on the surface of the molding body and the thickness of the epoxy resin is controlled.
  • Step 42 Plating the oxidation resistant metal layer or coating the antioxidant (OSP)
  • the metal exposed on the surface of the metal substrate after the completion of the step 41 is electroplated with an anti-oxidation metal layer to prevent metal oxidation such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP). .
  • an anti-oxidation metal layer to prevent metal oxidation such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP).

Abstract

提供了一种先蚀后封芯片正装三维系统级金属线路板结构，其特征在于它包括金属基板框（1），在所述金属基板框（1）内设置有基岛（2）和引脚（3），在所述基岛（2）的正面设置有芯片（5），所述芯片（5）正面与引脚（3）正面之间用金属线（6）相连接，在所述引脚（3）正面或背面设置有导电柱子（7），所述基岛（2）外围的区域、基岛（2）和引脚（3）之间的区域、引脚（3）与引脚（3）之间的区域、基岛（2）和引脚（3）上部的区域、基岛（2）和引脚（3）下部的区域以及芯片（5）、金属线（6）和导电柱子（7）外均包封有塑封料（8），在所述金属基板框（1）、引脚（3）和导电柱子（7）露出塑封料（8）的表面镀有抗氧化层或被覆抗氧化剂（9）。所述结构能够解决传统金属引线框无法埋入物件而限制金属引线框的功能性和应用性能。还提供了一种先蚀后封芯片正装三维系统级金属线路板的工艺方法。

Description

先蚀后封芯片正装三维系统级金属线路板结构及工艺方法 本申请要求于 2013 年 08 月 06 日提交中国专利局、 申请号为 201310339322.4,发明名称为"先蚀后封芯片正装三维系统级金属线路板结 构及工艺方法 "的中国专利申请的优先权，其全部内容通过引用结合在本申 请中。 技术领域
本发明涉及一种先蚀后封芯片正装三维系统级金属线路板结构及工艺 方法。 属于半导体封装技术领域。 背景技术
传统金属引线框架的基本制作工艺方法有以下方式： 下或是由下而上进行沖切， 促使引线框架能在金属片内形成有承载芯片的 基岛以及信号传输用的内引脚与外界 PCB连接的外引脚，之后再进行内引 脚及 (或)基岛的某些区域进行金属电镀层被覆而形成真正可以使用的引线 框架（参见图 76~图 78 )。
2)取一金属片利用化学蚀刻的技术进行曝光、显影、开窗、化学蚀刻， 促使引线框架能在金属片内形成有承载芯片的基岛以及信号传输用的内引 脚与外界 PCB连接的外引脚， 之后再进行内引脚及 (或)基岛的某些区域进 行金属电镀层被覆而形成真正可以使用的引线框架（参见图 79~图 80 )。
3) 另一种方式就是以方法一或是方法二为基础，在已经附有芯片承载 的基岛、信号传输的内引脚、与外界 PCB连接的外引脚以及在内弓 I脚及 (或) 基岛的某些区域进行金属电镀层被覆形成的引线框背面再贴上一层可抗 260摄氏度的高温胶膜， 成为可以使用在四面无引脚封装以及缩小塑封体 积的封装用的引线框（参见图 81 )。
4) 另一种方式就是以方法一或是方法二， 将附有芯片承载的基岛、 信 号传输的内引脚、 与外界 PCB连接的外引脚以及在内引脚及 (或)基岛的某 些区域进行金属电镀层被覆所形成的引线框进行预包封， 在金属片被沖切 或是被化学蚀刻的区域填充热固型环氧树脂填充， 使其成为可以使用在四 面无引脚封装、 缩小塑封体积以及铜线键合能力封装用的预填料型引线框 (参见图 82 )。
传统工艺方法的缺点：
1)机械沖切式引线框：
a. 机械沖切是利用上下刀具由上而下或是由下而上进行沖切形成垂 直断面， 所以完全无法在引线框内部再进行其它功能或物件埋入的利用如 系统对象集成在金属引线框本身
b. 机械沖压是利用上下刀具将金属片边缘进行相互挤压而沿伸出金 属区域，而被挤压所沿伸出的金属区域长度最多只能是引线框厚度的 80%。 如果超过弓 I线框厚度 80%以上时， 其被挤压所延伸出的金属区域很容易发 生翘曲、 隐裂、 断裂、 不规则形状以及表面孔洞等问题， 而超薄引线框更 是容易产生以上问题（参见图 83~图 84 )。
c 机械沖压所沿伸出的金属区域长度如果比引线框厚度少于 80%以 区域内再放入相关对象 (尤其是厚度需要超薄的引线框更是无法做到） （参 见图 85 ~图 86 )。
2)化学蚀刻技术方式引线框：
a. 减法蚀刻可以采用半蚀刻技术将需要埋入物件的空间蚀刻出来， 但 是最大的缺点就是独刻深度尺寸与蚀刻后平面的平整度较难控制。
b. 金属板完成很多需要埋入物件的半蚀刻区域后， 引线框的结构强度 会变得相当的软， 会直接影响到后续再埋入对象所需要工作条件 (如取放、 运输、 高温、 高压以及热应力收缩)的难度。
c 化学蚀刻技术方式的引线框顶多只能呈现出引线框正面与背面的 外脚或是内脚型态 ， 完全无法承现出多层三维金属线路的系统级金属引 线框。 发明内容
本发明的目的在于克服上述不足， 提供一种先蚀后封芯片正装三维系 统级金属线路板结构及工艺方法， 它能够解决传统金属引线框无法埋入物 件而限制金属 ^ )线框的功能性和应用性能。
本发明的目的是这样实现的： 一种先蚀后封芯片正装三维系统级金属 线路板的工艺方法， 所述方法包括如下步骤：
步骤一、 取金属基板
步骤二、 金属基板表面预镀微铜层
步骤三、 贴光阻膜作业
在完成预镀微铜层的金属基板正面及背面分别贴上可进行曝光显影的 光阻膜；
步骤四、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板背面进行图 形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进行 电後的区域图形；
步骤五、 电镀金属线路层
在步骤四中金属基板背面去除部分光阻膜的区域内电镀上金属线路 层；
步骤六、 贴光阻膜作业
在步骤五中金属基板背面贴上可进行曝光显影的光阻膜；
步骤七、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板背面进行图 形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进行 电後的区域图形；
步骤八、 电镀高导电金属线路层
在步骤七中金属基板背面去除部分光阻膜的区域内电镀上高导电金属 线路层；
步骤九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤十、 环氧树脂塑封 在金属基板背面的金属线路层表面利用环氧树脂材料进行塑封保护； 步骤十一、 环氧树脂表面研磨
在完成环氧树脂塑封后进行环氧树脂表面研磨；
步骤十二、 贴光阻膜作业
在完成步骤十一的金属基板正面和背面贴上可进行曝光显影的光阻 膜；
步骤十三、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十二完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行蚀刻的区域图形；
步骤十四、 化学蚀刻
将步骤十三中金属基板正面完成曝光显影的区域进行化学蚀刻； 步骤十五、 电镀金属层
在完成步骤十四的金属基板正面电镀上金属层， 金属层电镀完成后即 在金属基板上形成相应的基岛上部和引脚上部；
步骤十六、 贴光阻膜作业
在完成步骤十五的金属基板正面和背面贴上可进行曝光显影的光阻 膜；
步骤十七、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十六完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行电镀的区域图形；
步骤十八、 电镀金属柱子
在步骤十七中金属基板正面去除部分光阻膜的区域内电镀上金属柱 子；
步骤十九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤二十、 涂覆粘结物质 在步骤十五形成的基岛上部正面涂覆导电或不导电粘结物质； 步骤二十一、 装片
在步骤二十的导电或不导电粘结物质上植入芯片；
步骤二十二、 金属线键合
在芯片正面与引脚正面之间进行键合金属线作业；
步骤二十三、 包封
将步骤二十二中的金属基板正面采用塑封料进行塑封；
步骤二十四、 环氧树脂表面研磨
在完成步骤二十三的环氧树脂塑封后进行环氧树脂表面研磨； 步骤二十五、 电镀抗氧化金属层或批覆抗氧化剂（OSP)
在完成步骤二十四后的金属基板表面棵露在外的金属进行电镀抗氧化 金属层或批覆抗氧化剂（OSP)。
所述步骤十五移动至步骤四和步骤五之间进行。
一种先蚀后封芯片正装三维系统级金属线路板结构， 它包括金属基板 框， 在所述金属基板框内设置有基岛和引脚， 在所述基岛的正面或背面通 过导电或不导电物质设置有芯片， 所述芯片正面与引脚正面之间用金属线 相连接， 在所述引脚正面或背面设置有导电柱子， 所述基岛外围的区域、 基岛和引脚之间的区域、 引脚与引脚之间的区域、基岛和引脚上部的区域、 基岛和引脚下部的区域以及芯片、 金属线和导电柱子外均包封有塑封料， 所述塑封料与导电柱子的顶部齐平， 在所述金属基板框、 引脚和导电柱子 露出塑封料的表面镀有抗氧化层或被覆抗氧化剂。
一种先蚀后封芯片正装三维系统级金属线路板结构， 它包括金属基板 框和芯片， 在所述金属基板框内设置内设置有引脚， 所述芯片通过导电或 不导电粘结物质设置于引脚正面或是引脚与引脚之间的塑封料上， 所述芯 片正面与引脚正面之间用金属线相连接， 在所述引脚正面或背面设置有导 电柱子， 所述引脚与引脚之间的区域、 引脚上部的区域、 引脚下部的区域 以及芯片、 金属线和导电柱子外均包封有塑封料， 所述塑封料与导电柱子 的顶部齐平， 在所述金属基板、 引脚和导电柱子露出塑封料的表面镀有抗 氧化层或批覆抗氧化剂（OSP)。
所述引脚与引脚之间通过导电粘结物质跨接无源器件， 所述无源器件 可以跨接于引脚正面与引脚正面之间， 或跨接于引脚正面与静电释放圏的 正面之间， 或跨接于静电释放圏的正面与基岛的正面之间， 在所述基岛与 引脚的之间设置有静电释放圏， 所述芯片正面与静电释放圏正面之间通过 金属线相连。
所述导电柱子有多圏。
在所述芯片正面通过导电或不导电粘结物质设置有第二芯片， 所述第 二芯片正面与引脚之间通过金属线相连。
在所述引脚正面或背面设置有第二导电柱子， 在所述第二导电柱子上 通过导电物质倒装有第二芯片， 所述第二导电柱子和第二芯片处于塑封料 的内部。
在所述引脚正面或背面设置有第二导电柱子， 在所述第二导电柱子上 装有无源器件， 所述第二导电柱子和无源器件处于塑封料的内部。
一种先蚀后封芯片正装三维系统级金属线路板的工艺方法， 所述方法 包括如下步骤：
步骤一、 取金属基板
步骤二、 金属基板表面预镀微铜层
步骤三、 贴光阻膜作业
在完成预镀微铜层的金属基板正面及背面分别贴上可进行曝光显影的 光阻膜；
步骤四、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图 形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进行 电後的区域图形；
步骤五、 电镀第一金属线路层
在步骤四中金属基板正面去除部分光阻膜的区域内电镀上第一金属线 路层； 步骤六、 贴光阻膜作业
在步骤五中金属基板正面贴上可进行曝光显影的光阻膜；
步骤七、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图 形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进行 电後的区域图形；
步骤八、 电镀第二金属线路层
在步骤七中金属基板正面去除部分光阻膜的区域内电镀上第二金属线 路层作为用以连接第一金属线路层与第三金属线路层的导电柱子；
步骤九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤十、 贴压不导电胶膜作业
在金属基板正面贴压一层不导电胶膜；
步骤十一、 研磨不导电胶膜表面
在完成不导电胶膜贴压后进行表面研磨；
步骤十二、 不导电胶膜表面金属化预处理
对不导电胶膜表面进行金属化预处理；
步骤十三、 贴光阻膜作业
在步骤十二中金属基板正面和背面贴上可进行曝光显影的光阻膜； 步骤十四、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行蚀刻的区域图形； 步骤十五、 蚀刻作业
在步骤十四完成光阻膜开窗后的区域进行蚀刻作业；
步骤十六、 金属基板正面去除光阻膜
去除金属基板正面的光阻膜， 以露出后续需要进行被电镀的金属区域 图形；
步骤十七、 电镀第三金属线路层 在步骤十六的金属基板正面进行第三金属线路层的电镀工作； 步骤十八、 贴光阻膜作业
在步骤十七的金属基板正面贴上可进行曝光显影的光阻膜； 步骤十九、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行电镀的区域图形；
步骤二十、 电镀第四金属线路层
在步骤十九中金属基板正面去除部分光阻膜的区域内电镀上第四金属 线路层作为用以连接第三金属线路层与第五金属线路层的导电柱子； 步骤二十一、 去除光阻膜
去除金属基板表面的光阻膜；
步骤二十二、 贴压不导电胶膜作业
在金属基板正面贴压一层不导电胶膜；
步骤二十三、 研磨不导电胶膜表面
在完成不导电胶膜贴压后进行表面研磨；
步骤二十四、 不导电胶膜表面金属化预处理
对不导电胶膜表面进行金属化预处理；
步骤二十五、 贴光阻膜作业
在步骤二十四中金属基板正面和背面贴上可进行曝光显影的光阻膜； 步骤二十六、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤二十五完成贴光阻膜作业的金属基板正面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要 进行蚀刻的区域图形； 步骤二十七、 蚀刻作业
在步骤二十六完成光阻膜开窗后的区域进行蚀刻作业；
步骤二十八、 金属基板正面去除光阻膜
去除金属基板正面的光阻膜；
步骤二十九、 电镀第五金属线路层 在步骤二十八的金属基板正面进行第五金属线路层的电镀工作， 第五 金属线路层电镀完成后即在金属基板上形成相应的基岛和引脚；
步骤三十、 贴光阻膜作业
在步骤二十九中金属基板正面贴上可进行曝光显影的光阻膜； 步骤三十一、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三十完成贴光阻膜作业的金属基板背面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进 行蚀刻的区域图形；
步骤三十二、 化学蚀刻
将步骤三十一中金属基板背面完成曝光显影的区域进行化学蚀刻， 化 学蚀刻直至金属线路层为止；
步骤三十三、 贴光阻膜作业
在步骤三十二中完成化学蚀刻的金属基板背面贴上可进行曝光显影的 光阻膜；
步骤三十四、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三十三完成贴光阻膜作业的金属基板背面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要 进行电镀的区域图形；
步骤三十五、 电镀金属柱子
在步骤三十四中金属基板背面去除部分光阻膜的区域内电镀上金属柱 子；
步骤三十六、 去除光阻膜
去除金属基板表面的光阻膜；
步骤三十七、 涂覆粘结物质
在完成步骤三十六的基岛背面涂覆导电或不导电粘结物质； 步骤三十八、 装片
在步骤三十七的导电或不导电粘结物质上植入芯片；
步骤三十九、 金属线键合 在芯片正面与引脚背面之间进行键合金属线作业；
步骤四十、 包封
将步骤三十九中的金属基板背面采用环氧树脂 (俗称塑封料)进行塑 封；
步骤四十一、 环氧树脂表面研磨
在完成步骤四十的环氧树脂塑封后进行环氧树脂表面研磨； 步骤四十二、 电镀抗氧化金属层或批覆抗氧化剂（OSP)
在完成步骤四十一后的金属基板表面棵露在外的金属进行电镀抗氧化 金属层或批覆抗氧化剂（OSP)。
所述步骤六到步骤十七可重复操作， 形成更多层的金属线路层。 与现有技术相比， 本发明具有以下有益效果：
1 )目前金属引线框均采用机械沖切或是化学蚀刻方式，无法制做出多 层金属线路层， 而沖切式金属引线框中间的夹层中无法埋入任何的对象， 而本发明的三维金属线路复合式基板可以在基板中间的夹层中埋入对象。
2 )三维金属线路复合式基板中的夹层可以因为导热或是散热需要而在 需要的位置或是区域内埋入导热或是散热对象， 成为一个热性能系统级的 金属引线框。 （参见图 87 )
3 )三维金属线路复合式基板中的夹层可以因为系统与功能的需要而在 需要的位置或是区域内埋入主动元件或是组件或是被动的组件， 成为一个 系统级的金属引线框。
4 )从三维金属线路复合式基板成品的外观完全看不出来内部夹层已埋 入了因系统或是功能需要的对象，尤其是硅材的芯片埋入连 X光都无法检 视， 充分达到系统与功能的隐密性及保护性。
5 )三维金属线路复合式基板成品本身就富含了各种的组件，如果不再 进行后续第二次封装的其况下， 只要将三维金属线路复合式基板依照每一 格单元切开， 本身就可成为一个超薄的封装体。
6 ) 三维金属线路复合式基板除了本身内含对象的埋入功能之外还可 以进行二次封装， 充分的达到系统功能的整合。 7 )三维金属线路复合式基板除了本身内含对象的埋入功能之外还可以 在封装体外围再叠加不同的单元封装或是系统级封装， 充分达到双系统或 是多系统级的封装技术能力。
8) 三维金属线路基板可以应用于多芯片模组（MCM )封装（参见图 88和图 89 ) , 且三维金属线路基板比常规的 MCM基板底材成本低、 韧性 大。 附图说明
相信通过以下结合附图对本发明具体实施方式的说明， 能够使人们更 好地了解本发明上述的特点、 优点和目的， 其中：
图 1~图 25为本发明先蚀后封芯片正装三维系统级金属线路板工艺方 法的各工序示意图。
图 26为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 1 的示意图。
图 27为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 2 的示意图。
图 28为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 3 的示意图。
图 29为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 4 的示意图。
图 30为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 5 的示意图。
图 31、 图 32为本发明先蚀后封芯片正装三维系统级金属线路板结构 实施例 6的示意图。
图 33 ~图 74为本发明先蚀后封芯片正装三维系统级金属线路板结构 实施例 7的工艺流程图。
图 75为本发明先蚀后封芯片正装三维系统级金属线路板结构实施例 7 的示意图。
图 76为传统金属引线框架的基本制作工艺方法中的沖切示意图。 图 77 为传统金属引线框架的基本制作工艺方法中条型金属片的示意 图。
图 78 为传统金属引线框架的基本制作工艺方法中正面引线框的示意 图。
图 79为传统金属引线框架经过曝光、 显影、 开窗、 蚀刻等的基本制 作工艺方法中剖面的示意图。
图 80为传统金属引线框架的基本制作工艺方法中正面引线框的示意 图。
图 81为传统金属引线框架的基本制作工艺方法中 QFN的剖面结构示 意图。
图 82 为传统金属引线框架的基本制作工艺方法中预填料型引线框的 示意图。
图 83 为传统金属引线框架的基本制作工艺方法中上下刀具挤压形成 延伸金属区域的示意图。
图 84 为传统金属引线框架的基本制作工艺方法中上下刀具挤压形成 延伸金属区域所产生的隐裂、 断裂、 翘曲的示意图。
图 85 为传统金属引线框架的基本制作工艺方法中上下刀具挤压形成 沿伸金属区域长度不足引线框厚度 80%的示意图。
图 86为传统金属引线框架的基本制作工艺方法中上下刀具挤压形成 沿伸金属区域长度不足引线框厚度的 80%所产生埋入对象困难的示意图。
图 87 为三维金属线路复合式基板中的夹层可以因为导热或是散热需 要而在需要的位置或是区域内埋入导热或是散热对象的示意图。
图 88为三维金属线路基板应用于多芯片模组 ( MCM )封装的示意图。 图 89为图 88的俯视图。
其中：
金属基板框 1、 基岛 2、 引脚 3、 导电或不导电粘结物质 4、 芯片 5、 金属线 6、 导电柱子 7、 塑封料 8、 抗氧化层或批覆抗氧化剂 9、 无源器件 10、 静电释放圏 11、 第二芯片 12、 第二导电柱子 13、 导电物质 14。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进 行详细地描述。 应当理解， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有做出创造性劳动的前提下所获得的所有其他实施例， 都属于本发明保护 的范围。 本发明一种先蚀后封芯片正装三维系统级金属线路板结构及工艺 方法: ¾口下：
实施例 1、 单层线路单芯片正装单圏引脚
参见图 26, 为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 1的结构示意图， 它包括金属基板框 1 , 在所述金属基板框 1 内设置 有基岛 2和引脚 3 , 所述基岛 2正面通过导电或不导电粘结物质 4设置有 芯片 5 , 所述芯片 5正面与引脚 3正面之间用金属线 6相连接， 在所述引 脚 3正面设置有导电柱子 7 , 所述基岛 2外围的区域、 基岛 2和引脚 3之 间的区域、 引脚 3与引脚 3之间的区域、 基岛 2和引脚 3上部的区域、 基 岛 2和引脚 3下部的区域以及芯片 5、 金属线 6和导电柱子 7外均包封有 塑封料 8, 所述塑封料 8与导电柱子 7的顶部齐平， 在所述金属基板 1、基 岛 2、 引脚 3和导电柱子 7露出塑封料 8的表面镀有抗氧化层或批覆抗氧 化剂（OSP)9。
其工艺方法如下：
步骤一、 取金属基板
参见图 1 , 取一片厚度合适的金属基板， 此板材使用的目的只是为线 路制作与后续封装支撑线路层结构所使用的过渡性材料， 此板材的材质主 要是以金属材料为主，而金属材料的材质可以是铜材、 铁材、 镀辞材、 不 锈钢材、 铝材或可以达到导电功能的金属物质或非全金属物质等。
步骤二、 金属基板表面预镀微铜层
参见图 2, 在金属基板表面预镀微铜层， 微铜层厚度在 2~10微米，依 据功能需要也可以减薄或是增厚，主要是为了后续线路制作时使线路层与 金属基板能够紧密接合,电镀的方式可以采用化学沉积或是电解电镀。 步骤三、 贴光阻膜作业
参见图 3 , 在完成预镀微铜层的金属基板正面及背面分别贴上可进行 曝光显影的光阻膜， 以保护后续的电镀金属层工艺作业， 光阻膜可以是干 式光阻膜也可以是湿式光阻膜。
步骤四、 金属基板背面去除部分光阻膜
参见图 4, 利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板 背面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后 续需要进行电镀的区域图形。
步骤五、 电镀金属线路层
参见图 5 , 在步骤四中金属基板背面去除部分光阻膜的区域内电镀上 金属线路层， 金属线路层材料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金 (通常 5~20微米， 可以根据不同特性变换电镀的厚度)等材料， 当然 其它可以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜 银、 镍金、 镍钯金等金属材料， 电镀方式可以是化学沉积或是电解电镀方 式。
步骤六、 贴光阻膜作业
参见图 6, 在步骤五中金属基板背面贴上可进行曝光显影的光阻膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤七、 金属基板背面去除部分光阻膜
参见图 7, 利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板 背面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后 续需要进行电镀的区域图形。
步骤八、 电镀高导电金属线路层
参见图 8, 在步骤七中金属基板背面去除部分光阻膜的区域内电镀高 导电金属线路层， 高导电金属线路层的材料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等材料， 当然其它可以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等金属材料， 电镀方 式可以使化学沉积或是电解电镀方式。 步骤九、 去除光阻膜
参见图 9, 去除金属基板表面的光阻膜， 去除光阻膜的方法可采用化 学药水软化并采用高压水沖洗的方式去除光阻膜。
步骤十、 环氧树脂塑封
参见图 10,在金属基板背面的金属线路层和高导电金属线路层表面利 用环氧树脂材料进行塑封保护， 环氧树脂材料可以依据产品特性选择有填 料或是没有填料的种类， 塑封方式可以采用模具灌胶方式、 喷涂设备喷涂 方式、 贴膜方式或是刷胶的方式。
步骤十一、 环氧树脂表面研磨
参见图 11 , 在完成环氧树脂塑封后进行环氧树脂表面研磨 ， 目的是 使外脚功能用的高导电金属线路层露出塑封体表面以及控制环氧树脂的 厚度。
步骤十二、 贴光阻膜作业
参见图 12,在完成步骤十一的金属基板正面和背面贴上可进行曝光显 影的光阻膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤十三、 金属基板正面去除部分光阻膜
参见图 13,利用曝光显影设备将步骤十二完成贴光阻膜作业的金属基 板正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面 后续需要进行蚀刻的区域图形。
步骤十四、 化学蚀刻
参见图 14,将步骤十三中金属基板正面完成曝光显影的区域进行化学 蚀刻， 化学蚀刻直至金属线路层为止， 蚀刻药水可以采用氯化铜或是氯化 铁或是可以进行化学蚀刻的药水。
步骤十五、 电镀金属层
参见图 15, 在完成步骤十四的金属基板正面电镀上金属层， 金属层电 镀完成后即在金属基板上形成相应的基岛上部和引脚上部， 金属线路层材 料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等材料， 当然其它可 以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜银、 镍 金、 镍钯金等金属材料， 电镀方式可以使化学沉积或是电解电镀方式。 步骤十六、 贴光阻膜作业
参见图 16,在完成步骤十五的金属基板正面和背面贴上可进行曝光显 影的光阻膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤十七、 金属基板正面去除部分光阻膜
参见图 17,利用曝光显影设备将步骤十六完成贴光阻膜作业的金属基 板正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面 后续需要进行电镀的区域图形。
步骤十八、 电镀金属柱子
参见图 18,在步骤十七中金属基板正面去除部分光阻膜的区域内电镀 上金属柱子， 金属柱子的材料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等材料， 当然其它可以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等金属材料， 电镀方式可以使化学 沉积或是电解电镀方式。
步骤十九、 去除光阻膜
参见图 19, 去除金属基板表面的光阻膜， 去除光阻膜的方法可采用化 学药水软化并采用高压水沖洗的方式去除光阻膜。
步骤二十、 涂覆粘结物质
参见图 20,在步骤十五形成的基岛上部正面涂覆导电或不导电粘结物 质， 目的是为后续芯片植入后与基岛的接合。
步骤二十一、 装片
参见图 21 , 在步骤二十的导电或不导电粘结物质上植入芯片。
步骤二十二、 金属线键合
参见图 22, 在芯片正面与引脚正面之间进行键合金属线作业， 所述金 属线的材料采用金、 银、 铜、 铝或是合金的材料， 金属丝的形状可以是丝 状也可以是带状。
步骤二十三、 包封
参见图 23 , 将步骤二十二中的金属基板正面采用塑封料进行塑封， 塑 封方式可以采用模具灌胶方式、 喷涂设备喷涂方式或是用贴膜方式， 所述 塑封料可以采用有填料物质或是无填料物质的环氧树脂。
步骤二十四、 环氧树脂表面研磨
参见图 24,在完成步骤二十三的环氧树脂塑封后进行环氧树脂表面研 磨 ， 目的是使金属柱子露出塑封体表面以及控制环氧树脂的厚度。
步骤二十五、 电镀抗氧化金属层或是被覆抗氧化剂（OSP)
参见图 25 ,在完成步骤二十四后的金属基板表面棵露在外的金属进行 电镀抗氧化金属层， 防止金属氧化， 如金、 镍金、 镍钯金、 锡或是被覆抗 氧化剂（OSP)。
实施例 2、 多圏单芯片正装 +无源器件 +静电释放圏
参见图 27, 为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 2的结构示意图， 实施例 2与实施例 1的不同之处在于： 所述导电柱 子 7有多圏，所述引脚 3与引脚 3之间通过导电粘结物质跨接无源器件 10, 在所述基岛 2与引脚 3之间设置有静电释放圏 11 , 所述静电释放圏 11正 面与芯片 5正面之间通过金属线 6相连接，所述无源器件 10可以跨接于引 脚 3正面与引脚 3正面之间，或跨接于引脚 3正面与静电释放圏 11正面之 间， 或跨接于基岛 2正面与静电释放圏 11正面之间。
实施例 3、 单圏多基岛平铺多芯片正装
参见图 28, 为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 3的结构示意图， 实施例 3与实施例 1的不同之处在于： 所述基岛 2 有多个， 在所述基岛 2上均通过导电或不导电粘结物质 4设置有芯片 5 , 所述芯片 5正面与芯片 5正面之间通过金属线 6相连接。
实施例 4、 单圏堆叠多芯片正正装
参见图 29,为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 4的结构示意图， 实施例 4与实施例 1的不同之处在于： 在所述芯片 5正面通过导电或不导电粘结物质 4设置有第二芯片 12,所述第二芯片 12 正面与引脚 3之间通过金属线 6相连。
实施例 5、 单圏堆叠多芯片正倒装 参见图 30,为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 5的结构示意图， 实施例 5与实施例 1的不同之处在于： 在所述引脚 3正面设置有第二导电柱子 13 , 在所述第二导电柱子 13上通过导电物质 14倒装有第二芯片 12,所述第二导电柱子 13和第二芯片 12处于塑封料 8 的内部。
实施例 6、 无基岛单芯片正装
参见图 31、 32, 为本发明先蚀后封芯片正装三维系统级金属线路板结 构实施例 6的结构示意图， 实施例 6与实施例 1的不同之处在于： 所述金 属线路板结构不包括基岛 2, 所述芯片 5通过导电或不导电粘结物质 4设 置于金属基板 1正面或引脚 3正面与引脚 3正面之间。
实施例 7、 多层线路单芯片正装单圏引脚
参见图 75 ,为本发明先蚀后封芯片正装三维系统级金属线路板结构实 施例 7的结构示意图， 实施例 7与实施例 1的不同之处在于： 所述基岛 2 或引脚 3包括多层金属线路层， 相邻两层金属线路层之间通过导电柱子相 连接， 所述基岛 2背面通过导电或不导电粘结物质 4设置有芯片 5 , 在所 述引脚 3背面设置有导电柱子 7。
其工艺方法如下：
步骤一、 取金属基板
参见图 33 , 取一片厚度合适的金属基板， 此板材使用的目的只是为线 路制作与后续封装支撑线路层结构所使用的过渡性材料， 此板材的材质主 要是以金属材料为主，而金属材料的材质可以是铜材、 铁材、 镀辞材、 不 锈钢材、 铝材或可以达到导电功能的金属物质或非金属物质等。
步骤二、 金属基板表面预镀微铜层
参见图 34,在金属基板表面预镀微铜层，微铜层厚度在 2~10微米，依 据功能需要也可以减薄或是增厚,主要是为了后续线路制作时使线路层与 金属基板能够紧密接合,电镀的方式可以采用化学沉积或是电解电镀。
步骤三、 贴光阻膜作业
参见图 35 ,在完成预镀微铜层的金属基板正面及背面分别贴上可进行 曝光显影的光阻膜， 以保护后续的电镀金属层工艺作业， 光阻膜可以是干 式光阻膜也可以是湿式光阻膜。
步骤四、 金属基板正面去除部分光阻膜
参见图 36,利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板 正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后 续需要进行电镀的区域图形。
步骤五、 电镀第一金属线路层
参见图 37,在步骤四中金属基板正面去除部分光阻膜的区域内电镀上 第一金属线路层， 第一金属线路层材料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、镍钯金 (通常 5~20微米，可以根据不同特性变换电镀的厚度)等材料， 当然其它可以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等金属材料， 电镀方式可以是化学沉积或是电解电镀 方式。
步骤六、 贴光阻膜作业
参见图 38, 在步骤五中金属基板正面贴上可进行曝光显影的光阻膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤七、 金属基板正面去除部分光阻膜
参见图 39,利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板 正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后 续需要进行电镀的区域图形。
步骤八、 电镀第二金属线路层
参见图 40,在步骤七中金属基板正面去除部分光阻膜的区域内电镀上 第二金属线路层作为用以连接第一金属线路层与第三金属线路层的导电柱 子， 金属线路层的材质可采用铜、 镍金、 镍钯金、 银、 金或是锡金属， 电 镀方式可以使化学沉积或是电解电镀方式。
步骤九、 去除光阻膜 参见图 41 , 去除金属基板表面的光阻膜， 目的是为后续进行不导电胶 膜作业， 去除光阻膜的方法可采用化学药水软化并采用高压水沖洗的方式 去除光阻膜。
步骤十、 贴压不导电胶膜作业
参见图 42,在金属基板正面（有线路层的区域）贴压一层不导电胶膜， 目的是要为第一金属线路层与第三金属线路层进行绝缘， 贴压不导电胶膜 的方式可以采用常规的滚压设备， 或在真空的环境下进行贴压， 以防止贴 压过程产生空气的残留， 不导电胶膜主要是热固型环氧树脂， 而环氧树脂 可以依据产品特性采用没有填料或是有填料的不导电胶膜， 环氧树脂的颜 色可以依据产品特性进行染色处理。
步骤十一、 研磨不导电胶膜表面
参见图 43 , 在完成不导电胶膜贴压后进行表面研磨， 目的是要露出第 二金属线路层， 维持不导电胶膜与第二金属线路层的平整度以及控制不导 电胶膜的厚度。
步骤十二、 不导电胶膜表面金属化预处理
参见图 44, 对不导电胶膜表面进行金属化预处理， 使其表面附着上一 层金属化高分子材料， 目的是作为后续金属材料能够镀上去的触媒转换， 附着金属化高分子材料可以采用喷涂、 等离子震荡、 表面粗化等再行烘干 即可；
步骤十三、 贴光阻膜作业
参见图 45 , 在步骤十二中金属基板正面和背面贴上可进行曝光显影的 光阻膜， 以保护后续的第三金属线路层的电镀工艺作业， 光阻膜可以是干 式光阻膜也可以是湿式光阻膜。
步骤十四、 金属基板正面去除部分光阻膜
参见图 46, 利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基 板正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面 后续需要进行蚀刻的区域图形。
步骤十五、 蚀刻作业 参见图 47, 在步骤十四完成光阻膜开窗后的区域进行蚀刻作业， 其目 的是将要保留的金属线路以外的金属区域腐蚀干净， 进行蚀刻的方法可以 是氯化铜或是氯化铁或是可以进行化学蚀刻的药水的工艺方式。
步骤十六、 金属基板正面去除光阻膜
参见图 48, 去除金属基板正面的光阻膜， 以露出后续需要进行被电镀 的金属区域图形。
步骤十七、 电镀第三金属线路层
参见图 49, 在步骤十六的金属基板正面进行第三金属线路层的电镀 工作， 第三金属线路层的材质可以是铜、 镍金、 镍钯金、 银、 金或是锡金 属， 电镀方式可以是化学沉积加电解电镀或是全部使用化学沉积方式镀出 需要的厚度。
步骤十八、 贴光阻膜作业
参见图 50, 在步骤十七的金属基板正面贴上可进行曝光显影的光阻 膜， 目的是为后续金属线路层的制作， 光阻膜可以是干式光阻膜也可以是 湿式光阻膜。
步骤十九、 金属基板正面去除部分光阻膜
参见图 51 ,利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基 板正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面 后续需要进行电镀的区域图形。
步骤二十、 电镀第四金属线路层
参见图 52,在步骤十九中金属基板正面去除部分光阻膜的区域内电镀 上第四金属线路层作为用以连接第三金属线路层与第五金属线路层的导 电柱子， 金属线路层的材质可采用铜、 镍金、 镍钯金、 银、 金或是锡金属， 电镀方式可以使化学沉积或是电解电镀方式。
步骤二十一、 去除光阻膜
参见图 53 , 去除金属基板表面的光阻膜， 目的是为后续进行不导电胶 膜作业， 去除光阻膜的方法可采用化学药水软化并采用高压水沖洗的方式 去除光阻膜。 步骤二十二、 贴压不导电胶膜作业
参见图 54,在金属基板正面（有线路层的区域）贴压一层不导电胶膜， 目的是要为第三金属线路层与第五金属线路层进行绝缘， 贴压不导电胶膜 的方式可以采用常规的滚压设备， 或在真空的环境下进行贴压， 以防止贴 压过程产生空气的残留， 不导电胶膜主要是热固型环氧树脂， 而环氧树脂 可以依据产品特性采用没有填料或是有填料的不导电胶膜， 环氧树脂的颜 色可以依据产品特性进行染色处理。
步骤二十三、 研磨不导电胶膜表面
参见图 55 , 在完成不导电胶膜贴压后进行表面研磨， 目的是要露出第 四金属线路层， 维持不导电胶膜与第四金属线路层的平整度以及控制不导 电胶膜的厚度。
步骤二十四、 不导电胶膜表面金属化预处理
参见图 56, 对不导电胶膜表面进行金属化预处理， 使其表面附着上一 层金属化高分子材料， 目的是作为后续金属材料能够镀上去的触媒转换， 附着金属化高分子材料可以采用喷涂、 等离子震荡、 表面粗化等再行烘干 即可；
步骤二十五、 贴光阻膜作业
参见图 57, 在步骤二十四中金属基板正面和背面贴上可进行曝光显影 的光阻膜， 以保护后续的第五金属线路层的电镀工艺作业， 光阻膜可以是 干式光阻膜也可以是湿式光阻膜。
步骤二十六、 金属基板正面去除部分光阻膜
参见图 58, 利用曝光显影设备将步骤二十五完成贴光阻膜作业的金属 基板正面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正 面后续需要进行蚀刻的区域图形。
步骤二十七、 蚀刻作业
参见图 59, 在步骤二十六完成光阻膜开窗后的区域进行蚀刻作业， 其 目的是将要保留的金属线路以外的金属区域腐蚀干净， 进行蚀刻的方法可 以是氯化铜或是氯化铁或是可以进行化学蚀刻的药水的工艺方式。 步骤二十八、 金属基板正面去除光阻膜
参见图 60, 去除金属基板正面的光阻膜， 以露出后续需要进行被电镀 的金属区域图形。
步骤二十九、 电镀第五金属线路层
参见图 61 , 在步骤二十八的金属基板正面进行第五金属线路层的电 镀工作， 第五金属线路层电镀完成后即在金属基板上形成相应的基岛和引 脚， 第五金属线路层的材质可以是铜、 镍金、 镍钯金、 银、 金或是锡金属， 电镀方式可以是化学沉积加电解电镀或是全部使用化学沉积方式镀出需 要的厚度。
步骤三十、 贴光阻膜作业
参见图 62,在步骤二十九中金属基板正面贴上可进行曝光显影的光阻 膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤三十一、 金属基板背面去除部分光阻膜
参见图 63 , 利用曝光显影设备将步骤三十完成贴光阻膜作业的金属基 板背面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面 后续需要进行蚀刻的区域图形。
步骤三十二、 化学蚀刻
参见图 64,将步骤三十一中金属基板背面完成曝光显影的区域进行化 学蚀刻， 化学蚀刻直至金属线路层为止， 蚀刻药水可以采用氯化铜或是氯 化铁或是可以进行化学蚀刻的药水。
步骤三十三、 贴光阻膜作业
参见图 65 ,在步骤三十二中完成化学蚀刻的金属基板背面贴上可进行 曝光显影的光阻膜， 光阻膜可以是干式光阻膜也可以是湿式光阻膜。
步骤三十四、 金属基板背面去除部分光阻膜
参见图 66,利用曝光显影设备将步骤三十三完成贴光阻膜作业的金属 基板背面进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背 面后续需要进行电镀的区域图形。
步骤三十五、 电镀金属柱子 参见图 67,在步骤三十四中金属基板背面去除部分光阻膜的区域内电 镀上金属柱子， 金属柱子的材料可以是铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等材料， 当然其它可以导电的金属物质都可以使用， 并不局限铜、 铝、 镍、 银、 金、 铜银、 镍金、 镍钯金等金属材料， 电镀方式可以使化学 沉积或是电解电镀方式。
步骤三十六、 去除光阻膜
参见图 68, 去除金属基板表面的光阻膜， 可采用化学药水软化并采用 高压水喷除的方式去除光阻膜。
步骤三十七、 涂覆粘结物质
参见图 69,在步骤二十九形成的基岛背面涂覆导电或是不导电的粘结 物质， 目的是为后续芯片植入后与基岛的接合。
步骤三十八、 装片
参见图 70, 在步骤三十七的基岛背面植入芯片。
步骤三十九、 金属线键合
参见图 71 , 在芯片正面与引脚正面之间进行键合金属线作业， 所述金 属线的材料采用金、 银、 铜、 铝或是合金的材料， 金属丝的形状可以是丝 状也可以是带状。
步骤四十、 包封
参见图 72, 将步骤三十九中的金属基板背面采用塑封料进行塑封， 塑 封方式可以采用模具灌胶方式、 喷涂设备喷涂方式、 用贴膜方式或是刷胶 的方式， 所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。
步骤四十一、 环氧树脂表面研磨
参见图 73 , 在完成步骤四十的环氧树脂塑封后进行环氧树脂表面研 磨， 目的是使金属柱子露出塑封体表面以及控制环氧树脂的厚度。
步骤四十二、 电镀抗氧化金属层或是被覆抗氧化剂（OSP)
参见图 74, 在完成步骤四十一后的金属基板表面棵露在外的金属进行 电镀抗氧化金属层， 防止金属氧化， 如金、 镍金、 镍钯金、 锡或是被覆抗 氧化剂（OSP)。

Claims

权 利 要 求
1、 一种先蚀后封芯片正装三维系统级金属线路板的工艺方法， 所述 方法包括如下步骤：
步骤一、 取金属基板
步骤二、 金属基板表面预镀微铜层
步骤三、 贴光阻膜作业
在完成预镀微铜层的金属基板正面及背面分别贴上可进行曝光显影 的光阻膜；
步骤四、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板背面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进 行电镀的区域图形；
步骤五、 电镀金属线路层
在步骤四中金属基板背面去除部分光阻膜的区域内电镀上金属线路 层；
步骤六、 贴光阻膜作业
在步骤五中金属基板背面贴上可进行曝光显影的光阻膜；
步骤七、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板背面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进 行电镀的区域图形；
步骤八、 电镀高导电金属线路层
在步骤七中金属基板背面去除部分光阻膜的区域内电镀上高导电金 属线路层；
步骤九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤十、 环氧树脂塑封
在金属基板背面的金属线路层表面利用环氧树脂材料进行塑封保护； 步骤十一、 环氧树脂表面研磨
在完成环氧树脂塑封后进行环氧树脂表面研磨；
步骤十二、 贴光阻膜作业
在完成步骤十一的金属基板正面和背面贴上可进行曝光显影的光阻 膜；
步骤十三、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十二完成贴光阻膜作业的金属基板正面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要 进行蚀刻的区域图形；
步骤十四、 化学蚀刻
将步骤十三中金属基板正面完成曝光显影的区域进行化学蚀刻； 步骤十五、 电镀金属层
在完成步骤十四的金属基板正面电镀上金属层， 金属层电镀完成后即 在金属基板上形成相应的基岛上部和引脚上部；
步骤十六、 贴光阻膜作业
在完成步骤十五的金属基板正面和背面贴上可进行曝光显影的光阻 膜；
步骤十七、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十六完成贴光阻膜作业的金属基板正面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要 进行电镀的区域图形；
步骤十八、 电镀金属柱子
在步骤十七中金属基板正面去除部分光阻膜的区域内电镀上金属柱 子；
步骤十九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤二十、 涂覆粘结物质
在步骤十五形成的基岛上部正面涂覆导电或不导电粘结物质； 步骤二十一、 装片
在步骤二十的导电或不导电物质上植入芯片；
步骤二十二、 金属线键合
在芯片正面与引脚正面之间进行键合金属线作业；
步骤二十三、 包封
将步骤二十二中的金属基板正面采用塑封料进行塑封；
步骤二十四、 环氧树脂表面研磨
在完成步骤二十三的环氧树脂塑封后进行环氧树脂表面研磨； 步骤二十五、 电镀抗氧化金属层或被覆抗氧化剂
在完成步骤二十四后的金属基板表面棵露在外的金属进行电镀抗氧 化金属层或被覆抗氧化剂。
2、 一种由权利要求 1 制成的先蚀后封芯片正装三维系统级金属线路 板结构， 其特征在于它包括金属基板框（1), 在所述金属基板框（1 ) 内 设置有基岛 （2)和引脚（3), 在所述基岛 （2) 的正面或背面通过或导电 或不导电物质 （4)设置有芯片 （5), 所述芯片 （5) 正面与引脚（3) 正 面之间用金属线（6)相连接， 在所述引脚（3) 正面或背面设置有导电柱 子（7), 所述基岛 （2)外围的区域、 基岛 （2)和引脚（3)之间的区域、 引脚（3) 与引脚（3)之间的区域、 基岛 （2)和引脚（3)上部的区域、 基岛 （2)和引脚（3) 下部的区域以及芯片 （5)、 金属线 （6) 和导电柱 子 （7)外均包封有塑封料（8), 所述塑封料（8) 与导电柱子 （7) 的顶 部齐平， 在所述金属基板框（1)、 引脚（3)和导电柱子（7)露出塑封料 (8) 的表面镀有抗氧化层或被覆抗氧化剂 （9)。
3、 一种由权利要求 1 制成的先蚀后封芯片正装三维系统级金属线路 板结构， 其特征在于它包括金属基板框（1 )和芯片 （5), 在所述金属基 板框（1) 内设置有引脚（3), 所述芯片 （5)通过导电或不导电粘结物质 (4)设置于引脚（3) 正面或是通过导电或不导电粘结物质 （4)设置于 引脚（3)与引脚（3)之间， 所述芯片 （5) 正面与引脚（3) 正面之间用 金属线（6)相连接， 在所述引脚（3)正面或背面设置有导电柱子（7), 所述引脚（3)与引脚（3)之间的区域、 引脚（3)上部的区域、 引脚（3) 下部的区域以及芯片 （5)、 金属线（6)和导电柱子（7)外均包封有塑封 料（8), 所述塑封料（8)与导电柱子（7) 的顶部齐平， 在所述金属基板 框（1)、 引脚（3) 和导电柱子 （7) 露出塑封料（8) 的表面镀有抗氧化 层或被覆抗氧化剂 （9)。
4、 根据权利要求 2或 3提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于所述引脚（3)与引脚（3)之间通过导电粘结物质 跨接无源器件（10), 所述无源器件（10)可以跨接于引脚（3)正面与引 脚（3) 正面之间， 也可以跨接于引脚（3) 背面与引脚（3) 背面之间。
5、 根据权利要求 2或 3提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于所述导电柱子 （7)有多圏。
6、 根据权利要求 4提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述导电柱子（7)有多圏。
7、 根据权利要求 2提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述引脚（3)与引脚（3)之间通过导电粘结物质跨接 无源器件（ 10 ), 所述无源器件（ 10 )可以跨接于引脚（ 3 )正面与引脚（ 3 ) 正面之间， 也可以跨接于引脚（3) 背面与引脚（3) 背面之间。
8、 根据权利要求 2或 7提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于在所述基岛 （1)与引脚（2) 的之间设置有静电释 放圏 （11), 所述芯片 （6)正面与静电释放圏 （11)正面之间通过金属线 (6)相连。
9、 根据权利要求 7提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述导电柱子（7)有多圏。
10、 根据权利要求 8提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述导电柱子（7)有多圏。
11、 根据权利要求 2或 7提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于所述基岛 （2)有多个， 在所述多个基岛 （2)上均 通过导电或不导电粘结物质 （4)设置有芯片 （5), 所述芯片 （5)正面与 芯片 （5) 正面之间通过金属线（6)相连接。
12、 根据权利要求 8提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述基岛 （2)有多个， 在所述多个基岛 （2)上均通过 导电或不导电粘结物质（4)设置有芯片 （5) , 所述芯片 （5)正面与芯片 (5) 正面之间通过金属线 （ 6 )相连接。
13、 根据权利要求 9提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述基岛 （2)有多个， 在所述多个基岛 （2)上均通过 导电或不导电粘结物质（4)设置有芯片 （5) , 所述芯片 （5)正面与芯片
(5) 正面之间通过金属线 （6)相连接。
14、根据权利要求 10提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于所述基岛 （2)有多个， 在所述多个基岛 （2)上均通过 导电或不导电粘结物质（4)设置有芯片 （5) , 所述芯片 （5)正面与芯片 (5) 正面之间通过金属线 （6)相连接。
15、 根据权利要求 2或 7提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于在所述芯片 （5) 正面通过导电或不导电粘结物质
(4)设置有第二芯片 （12) , 所述第二芯片 （12) 正面与引脚（3)之间 通过金属线 （6)相连。
16、 根据权利要求 8提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于在所述芯片 （5) 正面通过导电或不导电粘结物质 （4) 设置有第二芯片 （12) , 所述第二芯片 （ 12) 正面与引脚（3)之间通过 金属线（6)相连。
17、 根据权利要求 9提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于在所述芯片 （5) 正面通过导电或不导电粘结物质 （4) 设置有第二芯片 （12) , 所述第二芯片 （ 12) 正面与引脚（3)之间通过 金属线（6)相连。
18、 根据权利要求 10提供的先蚀后封芯片正装三维系统级金属线路 板结构， 其特征在于在所述芯片 （5)正面通过导电或不导电粘结物质（4) 设置有第二芯片 （12) , 所述第二芯片 （ 12) 正面与引脚（3)之间通过 金属线（6)相连。
19、 根据权利要求 2或 7提供的先蚀后封芯片正装三维系统级金属线 路板结构， 其特征在于在所述引脚（3) 正面或背面设置有第二导电柱子
( 13), 在所述第二导电柱子 （13)上通过导电物质 （14)倒装有第二芯 片 （ 12 ) , 所述第二导电柱子 （ 13 )和第二芯片 （ 12 )处于塑封料（ 8 ) 的内部。
20、 根据权利要求 8提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于在所述引脚（ 3 )正面或背面设置有第二导电柱子（ 13 ) , 在所述第二导电柱子（ 13 )上通过导电物质（ 14 )倒装有第二芯片 （ 12 ) , 所述第二导电柱子（13)和第二芯片 （12)处于塑封料（8) 的内部。
21、 根据权利要求 9提供的先蚀后封芯片正装三维系统级金属线路板 结构， 其特征在于在所述引脚（ 3 )正面或背面设置有第二导电柱子（ 13 ), 在所述第二导电柱子（ 13 )上通过导电物质（ 14 )倒装有第二芯片 （ 12 ) , 所述第二导电柱子（13)和第二芯片 （12)处于塑封料（8) 的内部。
22、 根据权利要求 10提供的先蚀后封芯片正装三维系统级金属线路 板结构，其特征在于在所述引脚（ 3 )正面或背面设置有第二导电柱子（ 13 ), 在所述第二导电柱子（13)上通过导电物质 （14)倒装有第二芯片 （12), 所述第二导电柱子（13)和第二芯片 （12)处于塑封料（8) 的内部。
23、 根据权利要求 10提供的先蚀后封芯片正装三维系统级金属线路 板结构，其特征在于在所述引脚（ 3 )正面或背面设置有第二导电柱子（ 13 ), 在所述第二导电柱子（ 13 )上装有无源器件（ 10 ),所述第二导电柱子（ 13 ) 和无源器件 （10)处于塑封料（8) 的内部。
24、 根据权利要求 1所述的先蚀后封芯片正装三维系统级金属线路板 的工艺方法， 其特征在于所述步骤十五移动至步骤四和步骤五之间进行。
25、 一种先蚀后封芯片正装三维系统级金属线路板的工艺方法， 其特 征在于所述方法包括如下步骤：
步骤一、 取金属基板
步骤二、 金属基板表面预镀微铜层 步骤三、 贴光阻膜作业
在完成预镀微铜层的金属基板正面及背面分别贴上可进行曝光显影 的光阻膜；
步骤四、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行电镀的区域图形；
步骤五、 电镀第一金属线路层
在步骤四中金属基板正面去除部分光阻膜的区域内电镀上第一金属 线路层；
步骤六、 贴光阻膜作业
在步骤五中金属基板正面贴上可进行曝光显影的光阻膜；
步骤七、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行电镀的区域图形；
步骤八、 电镀第二金属线路层
在步骤七中金属基板正面去除部分光阻膜的区域内电镀上第二金属线 路层作为用以连接第一金属线路层与第三金属线路层的导电柱子；
步骤九、 去除光阻膜
去除金属基板表面的光阻膜；
步骤十、 贴压不导电胶膜作业
在金属基板正面贴压一层不导电胶膜；
步骤十一、 研磨不导电胶膜表面
在完成不导电胶膜贴压后进行表面研磨；
步骤十二、 不导电胶膜表面金属化预处理
对不导电胶膜表面进行金属化预处理；
步骤十三、 贴光阻膜作业 在步骤十二中金属基板正面和背面贴上可进行曝光显影的光阻膜； 步骤十四、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基板正面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要进 行蚀刻的区域图形；
步骤十五、 蚀刻作业
在步骤十四完成光阻膜开窗后的区域进行蚀刻作业；
步骤十六、 金属基板正面去除光阻膜
去除金属基板正面的光阻膜， 以露出后续需要进行被电镀的金属区域 图形；
步骤十七、 电镀第三金属线路层
在步骤十六的金属基板正面进行第三金属线路层的电镀工作； 步骤十八、 贴光阻膜作业
在步骤十七的金属基板正面贴上可进行曝光显影的光阻膜； 步骤十九、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基板正面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要 进行电镀的区域图形；
步骤二十、 电镀第四金属线路层
在步骤十九中金属基板正面去除部分光阻膜的区域内电镀上第四金 属线路层作为用以连接第三金属线路层与第五金属线路层的导电柱子； 步骤二十一、 去除光阻膜
去除金属基板表面的光阻膜；
步骤二十二、 贴压不导电胶膜作业
在金属基板正面贴压一层不导电胶膜；
步骤二十三、 研磨不导电胶膜表面
在完成不导电胶膜贴压后进行表面研磨；
步骤二十四、 不导电胶膜表面金属化预处理 对不导电胶膜表面进行金属化预处理；
步骤二十五、 贴光阻膜作业
在步骤二十四中金属基板正面和背面贴上可进行曝光显影的光阻膜； 步骤二十六、 金属基板正面去除部分光阻膜
利用曝光显影设备将步骤二十五完成贴光阻膜作业的金属基板正面进 行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板正面后续需要 进行蚀刻的区域图形；
步骤二十七、 蚀刻作业
在步骤二十六完成光阻膜开窗后的区域进行蚀刻作业；
步骤二十八、 金属基板正面去除光阻膜
去除金属基板正面的光阻膜；
步骤二十九、 电镀第五金属线路层
在步骤二十八的金属基板正面进行第五金属线路层的电镀工作， 第五 金属线路层电镀完成后即在金属基板上形成相应的基岛和引脚；
步骤三十、 贴光阻膜作业
在步骤二十九中金属基板正面贴上可进行曝光显影的光阻膜； 步骤三十一、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三十完成贴光阻膜作业的金属基板背面进行 图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需要进 行蚀刻的区域图形；
步骤三十二、 化学蚀刻
将步骤三十一中金属基板背面完成曝光显影的区域进行化学蚀刻， 化 学蚀刻直至金属线路层为止；
步骤三十三、 贴光阻膜作业
在步骤三十二中完成化学蚀刻的金属基板背面贴上可进行曝光显影的 光阻膜；
步骤三十四、 金属基板背面去除部分光阻膜
利用曝光显影设备将步骤三十三完成贴光阻膜作业的金属基板背面 进行图形曝光、 显影与去除部分图形光阻膜， 以露出金属基板背面后续需 要进行电镀的区域图形；
步骤三十五、 电镀金属柱子
在步骤三十四中金属基板背面去除部分光阻膜的区域内电镀上金属 柱子；
步骤三十六、 去除光阻膜
去除金属基板表面的光阻膜；
步骤三十七、 涂覆粘结物质
在完成步骤三十六后的基岛背面涂覆导电或是不导电的粘结物质； 步骤三十八、 装片
在步骤三十七的导电或不导电物质上植入芯片；
步骤三十九、 金属线键合
在芯片正面与引脚背面之间进行键合金属线作业；
步骤四十、 包封
将步骤三十九中的金属基板背面采用塑封料进行塑封；
步骤四十一、 环氧树脂表面研磨
在完成步骤四十的环氧树脂塑封后进行环氧树脂表面研磨； 步骤四十二、 电镀抗氧化金属层或被覆抗氧化剂
在完成步骤四十一后的金属基板表面棵露在外的金属进行电镀抗氧 化金属层或被覆抗氧化剂。
26、根据权利要求 25所述的先蚀后封芯片正装三维系统级金属线路板 的工艺方法， 其特征在于所述步骤六到步骤十七可重复操作， 形成更多层 的金属线路层。
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