CN102176448A - 扇出系统级封装结构 - Google Patents
扇出系统级封装结构 Download PDFInfo
- Publication number
- CN102176448A CN102176448A CN2011100699775A CN201110069977A CN102176448A CN 102176448 A CN102176448 A CN 102176448A CN 2011100699775 A CN2011100699775 A CN 2011100699775A CN 201110069977 A CN201110069977 A CN 201110069977A CN 102176448 A CN102176448 A CN 102176448A
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- Prior art keywords
- layer
- wiring
- protective layer
- encapsulation structure
- mounts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
Claims (10)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110069977.5A CN102176448B (zh) | 2011-03-22 | 2011-03-22 | 扇出系统级封装结构 |
PCT/CN2012/072766 WO2012126375A1 (en) | 2011-03-22 | 2012-03-22 | Fan-out high-density packaging methods and structures |
US13/984,889 US9040347B2 (en) | 2011-03-22 | 2012-03-22 | Fan-out high-density packaging methods and structures |
US14/693,995 US9287205B2 (en) | 2011-03-22 | 2015-04-23 | Fan-out high-density packaging methods and structures |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110069977.5A CN102176448B (zh) | 2011-03-22 | 2011-03-22 | 扇出系统级封装结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102176448A true CN102176448A (zh) | 2011-09-07 |
CN102176448B CN102176448B (zh) | 2015-08-05 |
Family
ID=44519593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110069977.5A Active CN102176448B (zh) | 2011-03-22 | 2011-03-22 | 扇出系统级封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102176448B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012126375A1 (en) * | 2011-03-22 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | Fan-out high-density packaging methods and structures |
CN103928416A (zh) * | 2014-03-24 | 2014-07-16 | 三星半导体(中国)研究开发有限公司 | 具有无源器件的半导体封装件及其堆叠方法 |
CN106783779A (zh) * | 2016-12-02 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | 一种高堆叠扇出型系统级封装结构及其制作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN2664198Y (zh) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | 多芯片封装结构 |
US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
CN101330068A (zh) * | 2007-06-18 | 2008-12-24 | 海力士半导体有限公司 | 模制重配置晶片、使用其的叠置封装及该封装的制造方法 |
-
2011
- 2011-03-22 CN CN201110069977.5A patent/CN102176448B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN2664198Y (zh) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | 多芯片封装结构 |
US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
CN101330068A (zh) * | 2007-06-18 | 2008-12-24 | 海力士半导体有限公司 | 模制重配置晶片、使用其的叠置封装及该封装的制造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012126375A1 (en) * | 2011-03-22 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | Fan-out high-density packaging methods and structures |
CN103928416A (zh) * | 2014-03-24 | 2014-07-16 | 三星半导体(中国)研究开发有限公司 | 具有无源器件的半导体封装件及其堆叠方法 |
CN103928416B (zh) * | 2014-03-24 | 2016-09-07 | 三星半导体(中国)研究开发有限公司 | 具有无源器件的半导体封装件及其堆叠方法 |
CN106783779A (zh) * | 2016-12-02 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | 一种高堆叠扇出型系统级封装结构及其制作方法 |
CN106783779B (zh) * | 2016-12-02 | 2019-06-14 | 华进半导体封装先导技术研发中心有限公司 | 一种高堆叠扇出型系统级封装结构及其制作方法 |
Also Published As
Publication number | Publication date |
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CN102176448B (zh) | 2015-08-05 |
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SE01 | Entry into force of request for substantive examination | ||
C53 | Correction of patent of invention or patent application | ||
CB03 | Change of inventor or designer information |
Inventor after: Shi Lei Inventor after: Tao Yujuan Inventor before: Tao Yujuan Inventor before: Shi Lei |
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COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: TAO YUJUAN SHI LEI TO: SHI LEI TAO YUJUAN |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee | ||
CP03 | Change of name, title or address |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |