CN1357911A - 用于球栅阵列封装的薄膜组合上的倒装芯片 - Google Patents
用于球栅阵列封装的薄膜组合上的倒装芯片 Download PDFInfo
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- CN1357911A CN1357911A CN01137477A CN01137477A CN1357911A CN 1357911 A CN1357911 A CN 1357911A CN 01137477 A CN01137477 A CN 01137477A CN 01137477 A CN01137477 A CN 01137477A CN 1357911 A CN1357911 A CN 1357911A
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Abstract
本发明揭示一种球栅阵列或连接头栅阵列塑封集成电路(IC)器件100的结构和方法,该器件具有金突起于芯片接触压头105上,诸压头从中心到中心彼此间隔小于100μm,并以倒装芯片附加于薄膜塑料基片101上。遮盖模塑封装料109对接触连到外部另外的焊球提供稳定性。任选的作为突起下填物使用的非导电的聚合物粘结剂提供额外的封装刚度。
Description
技术领域
本发明涉及的领域一般讲与半导体器件及工艺有关,更为具体而言,则与薄膜组合(Film assembly)上具有倒装芯片(flip-chip assembly)的球栅阵列(ball grid array)封装的结构和工艺有关。
背景技术
硅集成电路(IC)制作工艺流程中倒装芯片组合的日渐及普及是由以下几个事实加以驱动的。首先,当与常规的丝键合(Wire Bonding)互连技术相关的寄生电感得以减小时可改善半导体器件的电学性能。其次,与丝键合相比,倒装芯片组合提供芯片与封装之间更高的互连密度。第三,倒装芯片组合比丝键合消耗更少的硅片“真实所有地”并因而有助于节约硅片面积和降低成本。以及第四,当采用整体联动键合(gang-bonding)技术而非接连的单个键合步骤时可使制作成本降低。
常规的制作工艺采用焊球及其回流技术作为球键合的标准方法。虽已广泛采用铅/锡合金作为焊球的材料,但为使焊球成功地达到冶金学上的接触,IC芯片的接触压头必须接受特殊的金属化处理。金属化焊料的结构和制备以及关于接触的可靠性方面已有很多出版物加以介绍,最为突出的是在IBM J/Res.Develop.Vol.13,pp226-296,1969,226-296中定义所谓“C-4”技术的一组开拓论文:P.A.Totta等的“SLT器件冶金学及其整体延伸”,L.F.Miller的“受控的倒塌式回流芯片连接”,L.S.Goldmann的“受控的倒塌互连的几何最佳化”,K.C.Norris等的“受控的倒塌式互连之可靠性”,S.Oktay的“用受控的倒塌式技术连接的芯片中温度分布图之参数研究”,B.S.Berry等的“SLT芯片接头的冶金学研究”。
然而在已有技术中可达到的突起节距(bump pitch)是受到限止的。对于焊接材料,目前突起或焊球限于160μm的节距。这些限制使能在可用芯片表面上制作的连接数目大受约束,且限止了倒装芯片技术对具有小IC芯片器件的采用。
后来有人企图用金突起替代焊基互连球。借助于所谓的“带式自动键合”(TAB)技术,在接触金属引线(例如铜或镀锡的铜)至金突起方面取得了许多进步。然而,该技术和常规丝球键合或焊料回流键合相比,由于其相对高的成本而只得到有限的接受。借助改良过的丝球技术束获得金突起的努力并未使制造成本明显降低。在该技术中允许突起保留一小的“尾巴”,后者是在自由空气球业已形成并对着衬底加压成“突起”之后当金丝被切换时形成的。对于金柱突起或镀金突起,目前在生产中25μm的直径是器件用的较低值。
在以后数年,欲把IC芯片倒装键合上的基片业已从陶瓷变为诸如印刷电路板一类的有机体(例如FR-4或聚合物基薄片、在1999.6.27公布的美国专利号5,928,458(Aschenbrenner等)“用非导电粘合剂的倒装芯片键合”)中描述有一种方法,该片把在上述丝球法的基础上加以改良过的金突起技术和倒装总组合用的柔性有机芯片相结合。采用由热固性或热塑性混合物制成的非导电性粘合剂来稳定金突起对温度循环试验中所遇到的机械应力。由于该“突起”一个接着一个产生,故该片对于大批量生产的成本上是不合算的。同样它也并不轻易地适用于小的芯片级器件。
因此急需一种相容而且低价的组装高引脚数但仍为芯片级器件的方法,所述芯片级器件相似于球栅阵列封装那样,可被用来焊接至电路版上。该器件还应具有优良的电学性能,机械的稳定性以及高的产品可靠性。这种制作方法应灵活到足以适用于不同的半导体产品系数和宽广的设计及工艺变化种类。更为可取的是,这些革新应在缩短生产周期时间和增加产量以及采用现有设备基础从而无需投资新制造机器的情况下加以完成。
发明内容
描述球栅阵列或连接头栅阵列(Land-Gvid Array)塑封IC器件的结构和方法,该器件在其芯片接触压头上具有金突起,其中心到中心的间隔小于100μm,并把倒装的芯片附加至薄膜塑料基片上。遮盖模压(over mold)封装对连接到外部另件的焊球提供稳定性。用作突起下填物的一任选非导电性聚合物粘结剂提供额外的封装刚度。
本发明描述一种半导体器件,它包括:具有外形、有源和无源表面的芯片,和包括在有源表面上多个细节距接触压头在内的诸有源元件。该器件还包括多个附加至接触压头的电学耦合构件(耦合构件由以下组成的系列选择:金突起,铜突起,铜/镍/钯突起以及Z-轴导电环氧)。该器件进一步包括:具有第一和第二表面的电绝缘薄膜间隔层,多个全部在第一表面的导电连接,多个延伸穿过间隔层的导电路径,使之接触导电连线,并在所述第二表面上形成引出端点。间隔层具有一与芯片外形基本上相同的外形。
芯片耦合构件附加接触到导电连线,使得芯片覆盖住第一间隔层表面的平地部分。最后封装材料保持无源的芯片表面和至少未被附加上的芯片覆盖住的第一间隔层表面的部分。
在本发明的一个实施例中,器件作为连接头栅阵列或压头栅阵列封装加以制作。通过进一步附加上焊球到第二间隔层表面上的引出端点,该器件变变成为提供给本发明第二实施例的球栅阵列封装。虽然本发明适用于任何尺寸的器件,但某些小几何尺寸的器件则适配于芯片级和芯片尺寸封装一类的范畴。
在本发明的第3实施例中,该器件具有一非导电聚合物的粘合剂,它从下面充填于附加至少芯片底下导电连线的芯片耦合构件之间的任何空间,这一特征进一步对器件增强稳定性。
本发明的一个方面在于以总的薄剂面封装高引脚数的芯片级器件提供一低价的方法和系统。
本发明的另一个方面在于通过采用热压键合用的整体联动键合技术来提供一高的生产能力。
在发明的再一个方面是通过使寄生电阻和电感减至最小来改进电气产品的性能。
本发明的又一个方面是在不增加成本的情况下通过工艺内部控制来提供高的质量控制和可靠性保证。
在发明的再一个目的在于为薄剖面和可靠性引入诸组半概念,它们是灵活的,俾能使之适用于半导体产品的许多系列,并且是普遍的,俾能使之适用于半导体产品未来的若干代。
本发明的另一个目的在于使设备中投资的成本以及另件和产品的移动减至最少。
这些方面业已通过在发明有关适合于大量生产设计概念和工艺流程的进授而加以达到。已成历采用各种不同的改进以满足产品几何尺寸和材料的不同选择。
由本发明所代表的技术进步以及它们的目的当结合附图以及在所附权利要求中提出诸新的特征加以考虑时,将从以下本发明诸优选实施例的描述中变得明朗起来。
附图说明
图1为按本发明球栅阵列器件简化了的截面示意。
图2A-2E表示按本发明连接头栅阵列器件在其组装工艺的诸重要步骤中的顶视和截面示意。
图2A示出带有金突起的IC芯片。
图2B示出薄膜间隔层。
图2C示出附加具有突起的芯片至间隔层的工艺过程。
图2D示出借助遮盖模塑进行的封装工艺。
图2E示出借助球顶进行的封装工艺。
具体实施方式
图1以示意性和简化了的形式示出按本发明通过通常在球栅阵列封装的配置图中标以100的-器件之横截面。然而,本发明是发展的,这意味着在工艺(下述)中略加变动就可特指该器件为连接头栅阵列,压头栅阵列,或改良过的引脚-栅-阵列。
器件100是作为具有底剖面封装加以描述的。正此处所定义的那样,术语“剖面”系指集成电路封装的厚度或高度。该定义的确包括在其被回流接触至印刷电路板之前焊球的高度在内。本发明适用于任何外形的器件,包括那些具有芯片级或芯片尺寸的封装外形在内。正如此处所定义,术语“外形”涉及本发明之集成电路封装的整个宽度和长度。封装的外形同样也指封装的轨迹,因它限定封装将要占据的丝键合成组装板上的表面区域。本发明涉及所有尺寸或者芯片外形封装形之比的封装口。因此,本发明同样涉及诸如所谓的芯片级和芯片尺寸封装一类的小外形封装。
在图1中示出球栅阵列芯片级器件100,其结构相似于美国Texas,Dallas的TI所制的“MicroSkr JuniorTM”封装。该封装的重要部分乃为薄膜间隔层101。该基线聚合物膜101(例如聚酰亚胺)以适应用以连接至外部另件之“焊球”、“连接头”接触数所需的外形加以穿孔。对某些器件,这意味着典型地增加小于20%的硅芯片面积之外形。对另外一些器件,基线膜片能不得不显著大于芯片外形以适应高引脚数的芯片。该基线膜101由诸如聚酰亚胺一类电绝缘材料制成,厚度范围最为在大约40至80μm,在某些例子中可能还要厚些。其它合适的材料包括:KaptonTM,UpilexTM,PCB环氧,FR-4(一种环氧树脂),或者氰酸盐酯环氧(有时用编织的玻璃织物加强之)。这些材料通常可由若干产地取得,例如在美国包括3M,杜邦,以及Sheldahl在内的诸公司;在日本则包括Shinko,Shindo,Sumitomo和Mitsui,以及Ube工业有限公司;在香港则为Compass。
间隔层101具有第一表面101和第二表面101b。在表面101上为一粘结剂层102,上面粘结的是金属箔103。从箔103上形成多条导电连线。此外,可以该箔上形成其它的无源电气元件结构。例如电阻,电感,分布元件以及无源元件和互连结构的网络。这是在本发明的范围以内,即至少可将这些无源结构的部分(例如电感和电容)放置在IC芯片的下面。
金属箔103的厚度最好大约介于15和40μm之间,优选的箔材料包括铜,铜合金,金,银,钯铂以及镍/金和镍/钯的叠层。粘合剂层102的厚度典型也介于8和15μm之间。显然,金属连线乃随附加至芯片接触压头上耦合构件的数量和节距而变。或金属连线由衍形成,则腐蚀是最好的生产方法。若金属连线沉积而成,则镀敷工艺是有利的。
IC芯片104具有的外形和剖面最先决定器件100的外形和剖面。芯片剖面(厚度)可在130至375μm间变化,目前大多数的芯片落在250-375μm的厚度范围。芯片外形可在大约0.2至22mm之间变化。封装外形可在大约每边1.5mm至50mm(对正方形芯片)之间变化;长方形或矩形芯片和封装是普遍的。
芯片104具有有源表面104a和无源表面104b。把形成IC的有源元件制作在有源表面104a上,其中包括多个接触压头105。接触压头的数量变化很广,从3个到3000个以上,视在发明所适用的许多不同半导体器件类型而定。目前大多数芯片所具有的接触压头数范围在30至600个。
虽然可将本发明适用于接触压头105和任何节距,但对本发明而言,将接触压头105从中心至中心彼此间隔100μm以下乃是重要的。换言之,虽然本发明适用于任何一种器件,即使引脚数相对少的器件也适用,但本发明的全部效果和优点在引脚数相对多和十分多的器件种类中才更为显得出来。在倒装芯片配置中这些接触压头可利用整个芯片面积作为输入/输出目的。由于这些细节距接触压头的原故,即使对大数量的输入/输出,也可使所需芯片的面积保持在最小。
附加至这些接触压头上的电气耦合构件106为了小的压头节距而加以调整。较可取的是,耦合构件为金属突起,它们由以下组成的系列中选出:金,铜,铜合金,或成层的铜/镍/钯。另外一种选择是Z-轴上导电的环氧。突想可具有各种形状,例如,矩形,正方形,圆形,或半圆顶。图1中突起的横截面适用于这些耦合构件的若干种形状选择。
文献上已对常规芯片接触压头的铝金属化沉积金突起的方法有所描述。最普通的方法是电镀;然而,也使用无电极沉积。在最近芯片接触压头的铜金属化上沉积突起的方法最好是诸如铜/镍/钯一类成层的突起。以下的美国专利申请已对成功的技术加以描述:02/18/2000提出的#60/183,405(Stierman等,“供铜金属化IC键合压头用的结构和方法”)和07/07/2000提出的#09/611,623(Shen等,“在有源电路上带有键合层的集成电路”。这些申请的方法此处通过引证加以结合。
正如已在先前带式自动键(TAB)制作法中加以实践过的那样,附加该耦合构件106至导电连线103的方法是基于金属内部扩散的热压键合技术。对本发明优选的技术是供阵列组合用的整体联动键合技术。该技术具有快速和低成本运作的优点,而同时获得高质量和可靠的接触。自动化的装置通常可由日本的Shinkawa公司提供。
正如图1所指出的,电绝缘薄膜间隔层101具有多个导电路径107,后者从其第一表面101延伸穿通间隔层101至其第二表面101b。这些路径借助于通过间隔层101开出通孔(采用腐蚀,激光或冲孔技术),并填交以或者焊接金属或者焊料而加以获得。在10/31/2000提出的美国专利申请TI-31014(Pritchelt等,“具有集成无源元件和塑料芯片级封装”)中已对合合的制造方法有所描述,此处通过引证加以结合。
导电路径107在介面107a处接触导电连线103。在间隔层101的第二表面101b路径107形成引出端点107b。正如图1所示,对于球栅-阵列器件,可有焊球108附加接触至这些引出端点107b。对于连接头栅阵列器件,这些焊球将是不必要的。
正如这里所定义的,术语焊“球”并不一定意味着焊焊接触必须是球形的。它们可以具有各种不同的形式,诸如半球形,半圆顶,截锥,或者一般的突起。直实的形状随沉积技术(诸如蒸发,电镀,或预制件),回流技术(诸如红外,或辐射热)以及材料组成而变,焊球可选自以上组成的系列:纯锡,包括锡/铜、锡/铟、锡/银、锡/铋、锡/铅在内的锡合金,以及导电的粘合剂混合物。
正如图1所示,通过封装芯片104和至少间隔层103的邻近部分而产生具有刚度的组合结构乃是本发明的一个重要方面。图1实施例示出一遮盖模塑器件的例子。采用众所周知的传递模塑模塑混合物(通常为具有合适聚合物特性、玻璃转化温度、和稳定化无机填料的环氧基材料),带有适应于整个器件所希剖面之厚度的封装109使得以产生。对于连接头栅阵列封装,器件剖面大约处在0.1至11.0mm的范围,对于球栅阵列封装,正如图1所示,必须加上所附焊接材料的厚度。
在图1的实施例中,封装环绕并保持芯片104的无源表面104b和第一间隔层表面101a的全部面积及其上集成的导电连线103。在图2E所示本发明的另一实施例中,一球顶封装只覆盖住器件的中心部分,但其面积足以对器件提供稳定性。
图1示出选择以材料110从下面充填附加有突起的芯片。对下填材料110较可取的选择是作导电的粘结聚合物,诸如绝缘的粘结剂,不加导电充填物/料五的热塑/热固化混合物。一个例子是可由诸如全为日本的Hitachi化学,Toshiba化学以及Namics一类卖主获得的环氧基罐装材料。
图2A-2E示意性地说明本发明实施例中连接头栅阵列结构的制作方法。每个重要的工艺步骤均由(简化了的)顶视和(简化了的)横截面两者加以示出。
图2A描述的是带有附加耦合构件202(例如金突起)的IC芯片201之顶视和横截面。图2A所述芯片已由许多工业上良好建立因而没有示出的先前工艺加以形成。这些工艺步骤均在一晶圆片制造厂的整条半导体晶圆片线上加以完成。对于本发明下列工艺步骤尤为重要:
*沉积金,铜,或铜/镍/钯的电气耦合构件于晶圆片上每一IC芯片的每个接触压头,每一芯片具有的压头从中心至中心彼此间隔小于100μm。IC接触压头位于芯片的有源表面201a上;
*安装半导体晶圆片于安装带上,后者紧密地保持在固体架上,以备芯片切割(锯切);
*锯切晶圆片为分立的芯片;以及
*紫外处理安装带以便从安装带上取下所切锯的芯片。
图2B描述的一按上述材料和工艺步骤加以制备的片绝缘薄膜间隔层之顶视和横截面。具体而言,电绝缘膜210具有多个从第一表面210a至第2表面210b直通间隔层厚度的导电路径211,另外在第一表面上还有多条导电连线212。在间隔层的第一表面上还具有多个作成图案的接触点213,后者与IC芯片上诸耦合构件(金突起)的图案相匹配。薄膜间隔层的制作步骤包括以下几个主要步骤:
*在间隔层第一表面210a上沉积和制作多个导电连线212和接触点213;以及
*形成多个穿通间隔层的导电路径211。这些路径211与第一间隔层表面(211a)上的导电连线相接触,并在第二间隔层表面(211b)上形成引出端点(107b)。
图2C示出IC芯片的组装工艺步骤和间隔层。图2C的顶视图示出组装至间隔层210之后芯片的无源表面201b,而有源芯片表面201则面对间隔层第一表面210a(倒装芯片组合)。这一重要工艺步骤包括:
*组装有源芯片表面201a至第一间隔层表210a上,俾使每个芯片耦合构件202与间隔层相应的接触点213相互对准并保持接触;以及
*系用整体联动的热压键合,使所有接触联结通过金属内扩散面从根本上同时产生。这样间隔层的芯片尺寸部分就由所组装上的芯片201加以覆盖。
一任选的工艺包括:
下填粘结剂聚合物220于芯片底下芯片诸耦合构件202之间的任何空间;这些空间已由组装芯片201至间隔层210的工艺步骤加以形成。下填材料使该组合得以强化。
以上述工艺流程的一个变动中,施加下填材料可在热压键工艺步骤之前进行。
图2D和2E示出封装所组装器件的重要工艺步骤从获得具有刚度的组合结构。该工艺步骤包括:
*用一聚合混合物封装芯片的无源表面210b和至少未被所附加芯片覆盖住的第一间隔层表面210a的部分。
**若采用传送模塑法,则模塑混合物231混合保持第一间隔层表面210a(图2D)。这样模塑混合物的外形就限定了器件的外形。包括模塑混合物固化在内的传递模塑是较为可取的方法,因为它是被良好建立而又低成本(批量工艺)的工艺技术。
**若采用球顶保护法,则聚合物材料232只覆盖住未被所附加芯片盖住的第一间隔层表面210a的部分。在图2E中该表面部分标以240。球顶可以是圆形,如图2E所示,或者具有任何所希的其它外形(例如正方形或矩形)。
在封装步骤之后接下来的步骤:
*分离得到的组合结构成为分立的单元。较可取的是锯切。得到的器件外形可以是那种新一代的球栅阵列器件,或者更为明确的芯片级或芯片尺寸器件。
如图2D和2E中所示的最终器件属于连接头栅阵列器件的类型。为了制作球栅阵列器件,尚需如下的额外工艺步骤:
*在第二间隔层表面210上的附加焊球至引出端点211b。这一工艺步骤最好在执行上述分离步骤之前进行。
以下诸工艺步骤对于已知的制作技术都是类似的:
●打标记;
●试验;
●目视/机械检查;
●间隔层剪辑;
●包装;以及
●交货。
虽然为了说明诸实施例,以文献形成叙述了本发明,但这一叙述并非企图以有限的意义加以解释。对该技术熟练的人员而言,当参考这一叙述时,将会明白所述实施例的各种不同改良和联合以及本发明的其它实施例。作为一个例子,提供金突起至IC芯片以连接间隔层的方法可用一提供Z-轴导电环氧的方法加以替代作为另一例子,该间隔层可包括2或3层片绝缘的和导电的材料。而作为又一个例子,半导体芯片材料可以是硅,硅锗,砷化镓,或者任何用于大量生产的其它半导体材料。因此,所述的权利要求企图包括任何这样的改良或实施例。
Claims (16)
1.一种半导体器件,其特征在于,包括:
集成电路芯片,它具有外形、有源和无源表面以及包括在所述有源表面上从中心至中心彼此间隔小于100μm的多个接触压头在内的有源元件,
附加到所述接触压头的多个电气耦合构件,所述耦合构件由以下组成的系列选择:金突起,铜突起,铜/镍/钯突起,以及Z轴导电环氧,
电绝缘的薄膜间隔层,它具有第一和第二表面,多条集成在所述第一表面的导电连线,多个延伸穿通所述间隔层的导电路径,与所述导电连线接触并在所述第二表面上形成引出端点,
附加到所述导电连线的所述芯片耦合构件覆盖所述第一间隔层表面的部分面积,以及
封装材料,它保持所述无源芯片表面和至少未被所述附加芯片覆盖的所述第一间隔层表面的部分。
2.如权利要求1所述的器件,其特征在于,还包括
附加到所述第二间隔层表面上所述引出端点的焊球。
3.如权利要求1所述的器件,其特征在于,还包括
非导电的粘结聚合物,它从下面充填于附加到所述芯片下面所述导电连线的所述芯片耦合构件间的任何空间。
4.如权利要求1所述的器件,其特征在于,
所述间隔为聚酰亚胺膜。
5.如权利要求1所述的器件,其特征在于,
所述间隔层具有大于所述芯片外形的外形。
6.如权利要求1所述的器件,其特征在于,
所述导电连线由以下组成的系列材料选择制成:
铜,铜合金,或镀以锡的铜,锡合金,银或者金。
7.如权利要求1所述的器件,其特征在于,
所述耦合构件接触由热压键合的金属内扩散提供。
8.如权利要求1所述的器件,其特征在于,
所述封装材料为模塑混合物。
9.如权利要求8所述的器件,其特征在于,
所述模塑混合物具有与所述间隔层相同的外形。
10.一种半导体器件,其特征在于,包含:
集成电路芯片,它具有外形、有源和无源表面以及包括在所述有源表面上多个接触压头在内的有源元件,
多个附加到所述接触压头的导电耦合构件,所述耦合构件由以下组成的系列选择:金突起,铜突起,铜/镍/钯突起,以及Z轴导电环氧,
电绝缘的薄膜间隔层,它具有第一和第二表面,集成在所述第一表面的多条导电连线,延伸穿过所述间隔层的多个导电路径,与所述导电连线接触并在所述第二表面上形成引出端点,
附加到所述导电连线的所述芯片耦合构件覆盖所述第一间隔层表面的部分面积,以及
封装材料,它保持所述无源芯片表面和至少未被所述附加芯片覆盖的所述第一间隔层表面的部分。
11.一种组装集成电路器件的方法,其特征在于,包括以下步骤:
沉积金,铜,或铜/镍/钯的电气耦合构件于芯片的每一接触压头上,所述压头从中心到中心彼此间隔小于100μm,
沉积形成电绝缘的薄膜间隔层,并在其第一表面上制作多个导电连线的图案,
制作多个延伸穿过所述间隔层的导电路径,在所述第一表面上接触连接所述导电连线,并在所述间隔层的第二表面上形成引出端点,
在所述第一间隔层表面上组装所述芯片的有源表面,使得每一所述耦合构件分别附加接触到所述连线之一,从而覆盖住所述第一间隔层表面的部分面积,
用聚合物混合物封装所述芯片的无源表面以及至少未被所述附加上的芯片盖住的所述间隔层的部分,从而获得具有刚性的组合结构,以及
将得到的组合结构分离成分立的单元。
12.如权利要求11所述的方法,其特征在于,还包括以下步骤:
将非导电的粘结聚合物从下面充填到所述芯片下面所述芯片耦合构件之间的任何空间,并通过组装所述的芯片于所述的间隔层之上而形成,从而强化所述的组合。
13.如权利要求11所述的方法,其特征在于,还包含以下步骤:
在完成所述封装步骤之后和所述分离步骤之前,在所述第二间隔层表面附加焊球到所述的引出端点。
14.如权利要求11所述的方法,其特征在于,
所述沉积步骤包括镀敷,电镀,溅射或者蒸发。
15.如权利要求11的方法,其特征在于,
所述分离步骤包括切割,修正以及形成所述组合结构的步骤。
16.如权利要求11所述的方法,其特征在于,
所述组装步骤包括整体联动热压键合所述芯片耦合构件于所述间隔层连线之上的方法。
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EP (1) | EP1207555A1 (zh) |
JP (1) | JP2002170901A (zh) |
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CN1315186C (zh) * | 2004-05-01 | 2007-05-09 | 江苏长电科技股份有限公司 | 微型倒装晶体管的制造方法 |
CN100350608C (zh) * | 2004-01-09 | 2007-11-21 | 日月光半导体制造股份有限公司 | 多芯片封装体 |
CN102034777A (zh) * | 2009-09-25 | 2011-04-27 | 联发科技股份有限公司 | 半导体倒装芯片封装 |
CN102412224A (zh) * | 2010-07-26 | 2012-04-11 | 宇芯(毛里求斯)控股有限公司 | 用于半导体封装的连接芯片焊盘的引线框架 |
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KR20040060123A (ko) * | 2002-12-30 | 2004-07-06 | 동부전자 주식회사 | 반도체 소자 패키징 방법 |
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- 2001-11-15 JP JP2001350450A patent/JP2002170901A/ja active Pending
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CN100350608C (zh) * | 2004-01-09 | 2007-11-21 | 日月光半导体制造股份有限公司 | 多芯片封装体 |
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CN102034777A (zh) * | 2009-09-25 | 2011-04-27 | 联发科技股份有限公司 | 半导体倒装芯片封装 |
CN102412224A (zh) * | 2010-07-26 | 2012-04-11 | 宇芯(毛里求斯)控股有限公司 | 用于半导体封装的连接芯片焊盘的引线框架 |
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