JP4305502B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4305502B2 JP4305502B2 JP2006319910A JP2006319910A JP4305502B2 JP 4305502 B2 JP4305502 B2 JP 4305502B2 JP 2006319910 A JP2006319910 A JP 2006319910A JP 2006319910 A JP2006319910 A JP 2006319910A JP 4305502 B2 JP4305502 B2 JP 4305502B2
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- wiring
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- copper foil
- semiconductor device
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Description
前記配線形成用銅箔をパターニングして配線を形成する工程と、
半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する半導体構成体の外部接続用電極を前記配線にボンディングする工程と、
前記半導体構成体全体および前記配線の少なくとも一部を封止材で覆う工程と、
前記ベース板および前記剥離層を除去する工程と、を有し
前記封止材を形成する工程は、前記半導体構成体と前記剥離層との間にアンダーフィル材を充填すると共に前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、第2の封止材形成用シートおよび銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記封止材上に前記銅箔を固着する工程を含むことを特徴とするものである。
請求項2に記載の発明に係る半導体装置の製造方法は、請求項1に記載の発明において、前記封止材上に固着された前記銅箔を除去する工程を有することを特徴とするものである。
請求項3に記載の発明に係る半導体装置の製造方法は、請求項1に記載の発明において、前記封止材上に固着された前記銅箔により放熱層を形成する工程を有することを特徴とするものである。
請求項4に記載の発明に係る半導体装置の製造方法は、請求項1に記載の発明において、前記第1、第2の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とするものである。
請求項5に記載の発明に係る半導体装置の製造方法は、請求項1〜4のいずれかに記載の発明において、前記第2の封止材形成用シートは下側上下導通部を有すると共に前記半導体構成体に対応する部分に開口部を有し、前記封止材を形成する工程は、該第2の封止材形成用シート上に、第3の封止材形成用シートおよび下面に上側上下導通部を有する上層配線形成用銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記半導体構成体の周囲における前記封止材中に前記下側上下導通部および前記上側上下導通部からなる上下導通部を形成し、さらに、前記封止材上に前記上層配線形成用銅箔を前記上下導通部を介して前記配線に接続させて固着する工程を含むことを特徴とするものである。
請求項6に記載の発明に係る半導体装置の製造方法は、請求項5に記載の発明において、前記封止材上に固着された前記上層配線形成用銅箔をパターニングして上層配線を形成する工程を有することを特徴とするものである。
請求項7に記載の発明に係る半導体装置の製造方法は、請求項6に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜を形成する工程を有することを特徴とするものである。
請求項8に記載の発明に係る半導体装置の製造方法は、請求項5に記載の発明において、前記第1、第2、第3の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とするものである。
図1はこの発明の方法により製造された半導体装置の第1の例の断面図を示す。この半導体装置はソルダーレジスト等からなる平面方形状の下層絶縁膜1を備えている。下層絶縁膜1の上面には銅箔からなる複数の配線2が設けられている。配線2の一端部の接続パッド部上面には錫メッキからなる表面処理層3が設けられている。配線2の他端部の接続パッド部に対応する部分における下層絶縁膜1には開口部4が設けられている。下層絶縁膜1の開口部4内およびその下方には半田ボール5が配線2の他端部の接続パッド部に接続されて設けられている。
次に、この半導体装置の製造方法の参考実施形態について説明する。まず、図2に示すように、図1に示す配線2を形成するための配線形成用銅箔21の下面にポリイミドフィルム等からなる剥離層22が設けられ、剥離層22の下面に銅箔からなるベース板23が設けられたものを用意する。この場合、この用意したもののサイズは、図1に示す完成された半導体装置を複数個形成することが可能なサイズとなっている。そして、図2において、符号24で示す領域は個片化するための切断ラインに対応する領域である。
次に、図1に示された半導体装置の製造方法を示すこの発明の実施形態1について説明する。この場合、図6に示す工程後に、図11に示すように、半導体構成体6の周囲における配線2を含む剥離層22の上面に、格子状の第1の封止材形成用シート25をピン等で位置決めしながら配置する。
図13はこの発明の方法により製造された半導体装置の第2の例の断面図を示す。この半導体装置において、図1に示す半導体装置と異なる点は、半導体構成体6上に置ける封止材14の上面に銅箔からなる放熱層15を設け、放熱層15により、半導体基板7から発生する熱の放熱性を良くした点である。この場合、放熱層15は、例えば、図12に示す保護用銅箔27をフォトリソグラフィ法によりパターニングすると、形成することができるので、上側の加熱加圧板28の下面にエポキシ系樹脂等からなる熱硬化性樹脂が不要に付着するのを防止するための保護用銅箔27を有効に利用することができる。
図14はこの発明の方法により製造された半導体装置の第3の例の断面図を示す。この半導体装置において、図1に示す半導体装置と大きく異なる点は、封止材14の上面に上層配線31を設け、上層配線31の一端部を半導体構成体6の周囲における封止材14中に設けられた上下導通部32を介して配線2の他端部上面に接続させた点である。
次に、図14に示された半導体装置の製造方法を示すこの発明の実施形態2について説明する。この場合、図6に示す工程後に、図15に示すように、半導体構成体6の周囲における配線2を含む剥離層22の上面に、格子状の第1、第2の封止材形成用シート41、42をピン等で位置決めしながら配置し、その上に第3の封止材形成用シート43および上層配線形成用銅箔44を配置する。
2 配線
3 表面処理層
4 開口部
5 半田ボール
6 半導体構成体
7 シリコン基板
8 接続パッド
9 絶縁膜
10 開口部
11 下地金属層
12 突起電極
13 アンダーフィル材
14 封止材
15 放熱層
21 配線形成用銅箔
22 剥離層
23 ベース板
24 切断ライン
25 第1の封止材形成用シート
26 第2の封止材形成用シート
27 保護用銅箔
31 上層配線
32 上下導通部
38 オーバーコート膜
41 第1の封止材形成用シート
42 第2の封止材形成用シート
43 第3の封止材形成用シート
44 上層配線形成用銅箔
Claims (8)
- 配線形成用銅箔の下面に剥離層およびベース板が設けられたものを用意する工程と、
前記配線形成用銅箔をパターニングして配線を形成する工程と、
半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する半導体構成体の外部接続用電極を前記配線にボンディングする工程と、
前記半導体構成体全体および前記配線の少なくとも一部を封止材で覆う工程と、
前記ベース板および前記剥離層を除去する工程と、を有し
前記封止材を形成する工程は、前記半導体構成体と前記剥離層との間にアンダーフィル材を充填すると共に前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、第2の封止材形成用シートおよび銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記封止材上に前記銅箔を固着する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の発明において、前記封止材上に固着された前記銅箔を除去する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記封止材上に固着された前記銅箔により放熱層を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記第1、第2の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とする半導体装置の製造方法。
- 請求項1〜4のいずれかに記載の発明において、前記第2の封止材形成用シートは下側上下導通部を有すると共に前記半導体構成体に対応する部分に開口部を有し、前記封止材を形成する工程は、該第2の封止材形成用シート上に、第3の封止材形成用シートおよび下面に上側上下導通部を有する上層配線形成用銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記半導体構成体の周囲における前記封止材中に前記下側上下導通部および前記上側上下導通部からなる上下導通部を形成し、さらに、前記封止材上に前記上層配線形成用銅箔を前記上下導通部を介して前記配線に接続させて固着する工程を含むことを特徴とする半導体装置の製造方法。
- 請求項5に記載の発明において、前記封止材上に固着された前記上層配線形成用銅箔をパターニングして上層配線を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項6に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項5に記載の発明において、前記第1、第2、第3の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とする半導体装置の製造方法。
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JP2006319910A JP4305502B2 (ja) | 2006-11-28 | 2006-11-28 | 半導体装置の製造方法 |
US11/986,698 US7790515B2 (en) | 2006-11-28 | 2007-11-26 | Semiconductor device with no base member and method of manufacturing the same |
TW096144880A TWI371095B (en) | 2006-11-28 | 2007-11-27 | Semiconductor device and method of manufacturing the same |
KR1020070121487A KR100930156B1 (ko) | 2006-11-28 | 2007-11-27 | 반도체장치 및 그 제조방법 |
CN2007101928794A CN101192587B (zh) | 2006-11-28 | 2007-11-28 | 半导体器件的制造方法 |
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JP4596053B2 (ja) * | 2008-07-22 | 2010-12-08 | カシオ計算機株式会社 | 半導体装置の製造方法および半導体構成体組立体 |
TWI420622B (zh) * | 2008-11-07 | 2013-12-21 | Unimicron Technology Corp | 嵌埋半導體元件之封裝結構及其製法 |
US8474824B2 (en) * | 2008-11-10 | 2013-07-02 | Eaton Corporation | Pressure sensing module having an integrated seal plate and method of assembling pressure sensing module |
JP4972633B2 (ja) | 2008-12-11 | 2012-07-11 | 日東電工株式会社 | 半導体装置の製造方法 |
CN102047404B (zh) | 2008-12-16 | 2013-07-10 | 松下电器产业株式会社 | 半导体装置和倒装芯片安装方法及倒装芯片安装装置 |
US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
JP5563814B2 (ja) * | 2009-12-18 | 2014-07-30 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
CN103378044A (zh) * | 2012-04-25 | 2013-10-30 | 鸿富锦精密工业(深圳)有限公司 | 芯片组装结构及芯片组装方法 |
WO2015022808A1 (ja) * | 2013-08-13 | 2015-02-19 | 株式会社村田製作所 | 複合電子部品 |
JP6524526B2 (ja) * | 2015-09-11 | 2019-06-05 | 大口マテリアル株式会社 | 半導体素子実装用基板及び半導体装置、並びにそれらの製造方法 |
US9896330B2 (en) | 2016-01-13 | 2018-02-20 | Texas Instruments Incorporated | Structure and method for packaging stress-sensitive micro-electro-mechanical system stacked onto electronic circuit chip |
JP6477971B2 (ja) * | 2016-05-09 | 2019-03-06 | 日立化成株式会社 | 半導体装置の製造方法 |
KR102039710B1 (ko) | 2017-10-19 | 2019-11-01 | 삼성전자주식회사 | 유기 인터포저를 포함하는 반도체 패키지 |
US10861741B2 (en) | 2017-11-27 | 2020-12-08 | Texas Instruments Incorporated | Electronic package for integrated circuits and related methods |
US11538767B2 (en) | 2017-12-29 | 2022-12-27 | Texas Instruments Incorporated | Integrated circuit package with partitioning based on environmental sensitivity |
CN116525555A (zh) * | 2022-01-20 | 2023-08-01 | 长鑫存储技术有限公司 | 一种半导体封装结构及其制备方法 |
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JP3316532B2 (ja) | 1995-07-19 | 2002-08-19 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
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JP4392157B2 (ja) | 2001-10-26 | 2009-12-24 | パナソニック電工株式会社 | 配線板用シート材及びその製造方法、並びに多層板及びその製造方法 |
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JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP3925809B2 (ja) * | 2004-03-31 | 2007-06-06 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP2006059992A (ja) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
US7456493B2 (en) | 2005-04-15 | 2008-11-25 | Alps Electric Co., Ltd. | Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein |
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US7790515B2 (en) | 2010-09-07 |
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JP2008135521A (ja) | 2008-06-12 |
KR100930156B1 (ko) | 2009-12-07 |
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