CN102024711B - 一种提高plcc封装集成电路合格率的方法 - Google Patents
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Abstract
本发明涉及一种提高塑料PLCC封装集成电路合格率的方法,包括下列步骤:减薄;绷膜;划片;粘片;键合;模封;固化;电镀;其特征在于,在上述键合和模封步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封。采用了上述的技术解决方案,即增加一步硅片覆层步骤,本发明可以缓解封装应力导致的集成电路线路参数漂移失效,在不改变现有设计和工艺的基础上提高芯片性能,明显提高了合格率。
Description
技术领域
本发明涉及一种提高PLCC封装集成电路合格率的方法。
背景技术
现有一般集成电路,大多采用塑料封装形式,最典型的封装形式为塑料有引线芯片载体(PLCC)。封装主要是考虑器件的功率、重量、引脚数、尺寸、密度、电响应、可靠性、热耗散等等。对于器件的功能和合格率一般不是封装技术考虑的因素。
现有技术中,PLCC封装的主要工艺流程如下:
1:减薄(Back grinding):指将晶圆通过背面打磨使之厚度控制在一定的范围。
2:绷膜(Wafer Mounting):绷膜主要是给晶圆的背面贴上一层有弹性和一定粘性的蓝膜,并固定在一个直径稍大的金属框架上。为了避免粘贴不牢靠而造成划片的过程中的飞片问题,在绷膜的过程中要加热60-80度的温度。
3:划片(Wafer Sawing):划片的目的是将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来。如果前面绷膜的时候晶圆粘贴不牢靠或者有气泡存在,切割开来的硅片(Die)就会从蓝膜上飞出来,称作飞片。
4:粘片(Die Attach):粘片是通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上。根据器件的封装类型不同,载体也有区别。常规封装,所用的载体是引线框架。对于集成电路,一般选用的焊接材料为银胶(Epoxy Glue),在粘片的过程中,引线框架不需要加热。银胶是一种导电材料和其他化学物质的混合物,在粘片之后,引线框架要放置到固化炉(Curing Oven)中一定时间,使银胶固化。
5:键合(Wire Bonding):用金属线将硅片上的电气连接点(bond pad)和引线框架上的管脚(lead)或者基板上的焊盘连接起来。
6:模封(Molding):使用固态环氧树脂模封材料(EPOXY MOLDINGCOMPOUND)的移转注模成型制程。
7:固化(Curing):在一定温度下使固态环氧树脂模封材料固化成型。
8:电镀(Plating):采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性。
9:切筋成型(Trimming Forming):将成型的器件切开并且排列好。
10:测试/分选(Testing/Binning):对于器件进行简单的开短路测试,把封装过程中的失效器件删选掉。
封装完成后的器件如图1所示,在粘片1上层的粘片粘胶2上放置硅片3,用金属线5将硅片3上的电气连接点与框架上的管脚4相连,用固态环氧树脂模封材料6固化成型。
在上述的封装过程中,由于部分集成电路芯片(Die)的设计中采用了一些特殊设计,集成电路芯片中的DMOS对于器件的封装应力比较敏感,从而导致器件在特定的应用场合会造成部分功能的偏差;尤其针对通讯类专用集成电路产品,采用普通的PLCC封装,由于设计上存在未考虑周到的问题,导致该器件存在一定的集成电路设计不均匀,从而造成一定比例的器件功能失效,造成在PLCC封装以后半导体器件的合格率大幅下降。
发明内容
为了克服上述现有技术存在的不足,本发明旨在通过改进PLCC封装大规模集成电路的封装工艺,解决由于集成电路的特殊线路设计问题造成的集成电路合格率影响。
本发明所述的一种提高塑料PLCC封装集成电路合格率的方法,包括下列步骤:
第一,减薄,即将晶圆通过背面打磨使之厚度控制在规定的范围内:;
第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;
第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;
第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;
第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;
第六,模封,即使用固态环氧树脂模封材料注模成型;
第七,固化,即在规定温度下使固态环氧树脂模封材料固化成型;
第八,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性;
在上述加工的第五和第六步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封;
所述的第一步骤中,晶圆的厚度控制在350~390um的范围内。
在上述的提高PLCC封装集成电路合格率的方法中,所述的第一步骤包括在温度为40℃的条件下,先在所述晶圆背面贴膜,再对该贴膜修边,减薄后将所述晶圆带膜冲水,最后在温度为45℃的条件下揭膜。
采用了上述的技术解决方案,本发明在现有的PLCC封装方法中,增加一步硅片覆层步骤,即采用覆层材料在硅片表面均匀涂覆后再模封。由于在封装过程中,产生应力是不可避免的,从而会造成集成电路芯片中DMOS的不匹配,本发明可以缓解封装应力导致的集成电路线路参数漂移失效,在不改变现有设计和工艺的基础上提高芯片性能,明显提高了合格率。
附图说明
图1是现有PLCC封装器件纵向剖面示意图;
图2是本发明PLCC封装器件纵向剖面示意图。
具体实施方式
本发明,一种提高塑料PLCC封装集成电路合格率的方法,包括下列步骤:
第一,减薄,在温度为40℃的条件下,先在晶圆背面贴膜,再对该贴膜修边,晶圆通过背面打磨使之厚度控制在350~390um的范围内,减薄后将所述晶圆带膜冲水,最后在温度为45℃的条件下揭膜;
第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;
第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;
第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;
第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;
第六,硅片覆层,即采用涂层材料在硅片表面均匀涂覆后再模封;
第七,模封,即使用固态环氧树脂模封材料注模成型;
第八,固化,即在规定温度下使固态环氧树脂模封材料固化成型;
第九,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性。
封装完成后的器件如图2所示,在粘片1上层的粘片粘胶2上放置硅片3,在硅片表面均匀涂覆涂层7,用金属线5将硅片3上的电气连接点与框架上的管脚4相连,用固态环氧树脂模封材料6固化成型。
本发明在当前流行的PLCC封装工艺中,改进了一般的封装流程,在现有工艺第五步和第六步之间增加一步标准的Die coating(硅片覆层)工艺,即采用涂层材料在硅片表面均匀涂覆后再模封。这步工艺的特点在于可以缓解封装应力导致的集成电路线路参数漂移失效。
以上结合附图实施例对本发明进行了详细说明,本领域中普通技术人员可根据上述说明对本发明做出种种变化例。因而,实施例中的某些细节不应构成对本发明的限定,本发明将以所附权利要求书界定的范围作为本发明的保护范围。
Claims (1)
1.一种提高塑料PLCC封装集成电路合格率的方法,包括下列步骤:
第一,减薄,即将晶圆通过背面打磨使之厚度控制在规定的范围内;
第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;
第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;
第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;
第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;
第六,模封,即使用固态环氧树脂模封材料注模成型;
第七,固化,即在规定温度下使固态环氧树脂模封材料固化成型;
第八,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性;
其特征在于,
在上述加工的第五和第六步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封;
所述的第一步骤中,晶圆的厚度控制在350~390um的范围内,
所述的第一步骤包括在温度为40℃的条件下,先在所述晶圆背面贴膜,再对该贴膜修边,减薄后将所述晶圆带膜冲水,最后在温度为45℃的条件下揭膜。
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CN101290891A (zh) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | 晶片级芯片尺寸封装方法 |
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JP2002170901A (ja) * | 2000-11-16 | 2002-06-14 | Texas Instruments Inc | 半導体集積回路デバイスおよびその組立て方法 |
CN1755908A (zh) * | 2004-09-29 | 2006-04-05 | 上海贝岭股份有限公司 | 一种提高塑料封装集成电路合格率的方法 |
CN101290891A (zh) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | 晶片级芯片尺寸封装方法 |
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