CN204441277U - 一种采用预置胶膜工艺封装的智能卡模块 - Google Patents

一种采用预置胶膜工艺封装的智能卡模块 Download PDF

Info

Publication number
CN204441277U
CN204441277U CN201420871556.3U CN201420871556U CN204441277U CN 204441277 U CN204441277 U CN 204441277U CN 201420871556 U CN201420871556 U CN 201420871556U CN 204441277 U CN204441277 U CN 204441277U
Authority
CN
China
Prior art keywords
chip
smart card
adhesive film
card module
preset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201420871556.3U
Other languages
English (en)
Inventor
杨辉峰
沈建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHANGHAI INESA INTELLIGENT ELECTRONICS Co Ltd
Original Assignee
SHANGHAI INESA INTELLIGENT ELECTRONICS Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHANGHAI INESA INTELLIGENT ELECTRONICS Co Ltd filed Critical SHANGHAI INESA INTELLIGENT ELECTRONICS Co Ltd
Priority to CN201420871556.3U priority Critical patent/CN204441277U/zh
Application granted granted Critical
Publication of CN204441277U publication Critical patent/CN204441277U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

本实用新型公开了一种采用预置胶膜工艺封装的智能卡模块,该智能卡模块,包括绝缘智能卡载带、芯片和封装体,芯片安装在载带的芯片承载区域,芯片的功能焊盘和载带的焊盘采用引线焊接导通,封装体将芯片和引线包封起来,形成可靠地保护体,芯片安装到载带的芯片承载区域是通过预置的胶膜层来实现可靠安装。本方案可以省去设备点胶的工序,大大提高了生产效率,同时避免了由于点胶制程产生的不良率,有效降低了产品成本,整个生产过程可以延用现有设备进行大批量生产。

Description

一种采用预置胶膜工艺封装的智能卡模块
技术领域
本实用新型涉及一种集成电路封装技术,特别涉及一种智能卡模块的封装技术。
背景技术
随着集成电路封装技术的不断进步,集成电路的集成度日益提高,功能越来越丰富。对于不断出现的新应用需求,要求集成电路封装企业能设计出新型的封装形式来配合新的需求。
目前,在半导体封装领域,固晶的方式大都采用银浆点胶固晶的方式;特别是在智能卡模块封装领域,传统的智能卡模块无一例外的都采用银浆固晶的方式将芯片安装到载带上,通过加热将银浆固化,再进行后续的引线焊接、封装、测试等工序。采用银浆点胶的工艺,存在生产工艺繁琐、材料成本高、材料损耗大,生产效率低等缺点。
为此,开发新的生产工艺和新的技术,是本领域亟需要解决的问题,行业内也出现了采用倒封装的工艺来替代传统的引线焊接工艺实现智能卡模块的生产,但是这种方式有它的局限性,比如载带的通用性不强,每种芯片必须配套设计专用的智能卡载带,载带上的焊盘和芯片必须一一对应,更换芯片必须同时更换载带,这种方式对于中小批量,多型号的生产非常不利。
实用新型内容
针对现有智能卡模块所存在的生产工艺繁琐、生产成本高且生产效率低等问题,本实用新型的目的在于提供一种采用预置胶膜工艺封装的智能卡模块。该智能卡模块能够可以有效简化智能卡模块的生产流程,提高生产效率,更降低了产品的生产成本。
为了达到上述目的,本实用新型采用如下的技术方案:
采用预置胶膜工艺封装的智能卡模块,包括绝缘智能卡载带、芯片和封装 体,芯片安装在载带的芯片承载区域,芯片的功能焊盘和载带的焊盘采用引线焊接导通,封装体将芯片和引线包封在绝缘智能卡载带上,所述的芯片与载带的芯片承载区域之间通过预置的胶膜层进行安装。
在智能卡模块的优选方案中,所述的胶膜层预置在智能卡载带的芯片承载区域内。
优选的,所述的胶膜层预置在芯片的电路层反面。
优选的,所述的胶膜层具有随温度变化而产生状态和粘性变化的特性,常温下胶膜层呈固态,加热后胶膜层融化,并产生较强的粘结力,胶膜层的融化温度在50-100℃之间。
优选的,所述的胶膜层常温下呈固态,50-100℃低温加热后胶膜层具备较强粘性,此状态可以提供芯片上座固定的要求,后经过100-200℃快速烘烤达到最终固化,再次烘烤加热不能融化,具有不可回溯的特性。
优选的,所述的胶膜层经过一次加热融化后常温固化,在二次加热时不再融化。
优选的,所述的胶膜层经多次加热后可以多次融化。
优选的,所述的胶膜层厚度为5~30um。
优选的,所述的载带是连续长条形并无限延长的结构。
优选的,所述封装体为采用紫外线封装体或者模塑封装体。
本实用新型提供的方案可以省去固晶过程中的银浆点胶的工艺,部分情况下更可以省去了加热固化的制程,大大节约了生产时间,提高了生产效率,同时也降低了由于点胶调试而浪费的原材料损耗,并彻底解决了点胶过程中的不良率问题,为产品的批量生产提供了技术保障。
本实用新型提供的方案能够适应智能卡模块领域的封装要求,更适合在智能卡模块领域的创新应用,将极大地推动全球智能卡模块封装行业发展,具有较好的应用前景。
附图说明
以下结合附图和具体实施方式来进一步说明本实用新型。
图1为本实用新型的采用载带预置胶膜层及紫外线封装体的智能卡模块剖 面图;
图2为本实用新型的预置了胶膜层的连续载带示意图;
图3为本实用新型的预置了胶膜层的芯片示意图;
图4为本实用新型的采用芯片预置胶膜层及模塑封装体的智能卡模块剖面图;
图5为智能卡载带芯片安装面示意图;
图6为智能卡载带导电层面示意图。
具体实施方式
为了使本实用新型实现的技术手段、创作特征、达成目的与功效易于明白了解,下面结合具体图示,进一步阐述本实用新型。
参见图1和图4,其所示为本实用新型提供的采用预置胶膜工艺封装的智能卡模块的结构示意图。
由图可知,本实用新型提供的智能卡模块主要包括绝缘智能卡载带1、芯片6和封装体,芯片6安装在载带的芯片承载区域,芯片与载带的芯片承载区域之间通过预置的胶膜层5进行可靠的粘结安装;芯片6的功能焊盘和载带的焊盘采用引线7焊接导通,封装体8将芯片和引线包封在绝缘智能卡载带上。
其中,胶膜层5可预先设置在智能卡载带的芯片承载区域内或设置在芯片的电路层反面,可根据实际需求而定。
该胶膜层5厚度均匀,厚度为5~30um。
再者,该胶膜层具有随温度变化而产生状态和粘性变化的特性,常温下胶膜层呈固态,加热后胶膜层融化,并产生较强的粘结力,胶膜层的融化温度在50-100℃之间。
进一步的,该胶膜层在常温下呈固态,50-100℃低温加热后胶膜层具备较强粘性,此状态可以提供芯片上座固定的要求,后经过100-200℃快速烘烤达到最终固化,再次烘烤加热不能融化,具有不可回溯的特性。
作为替代方案,该胶膜层可采用经过一次加热融化后常温固化,在二次加热时不再融化的胶膜层。
作为另一替代方案,该胶膜层可采用经多次加热后可以多次融化的胶膜 层。
本智能卡模块中的用于封装固定的封装体8,具体可采用紫外线封装体或者模塑封装体,可根据实际需求而定。
以下通过具体实例来进一步的说明本方案的方案:
实施例一:
参见图5和图6,其所示为本实例中智能卡载带的芯片安装面示意图和导电层面示意图,在载带1的长边设置了若干个均匀排列的齿孔2,用于设备步进使载带向前移动。在载带的芯片安装面中部,设置了若干个引线焊接孔4,用于将芯片上的功能焊盘和载带上的导电图形连通。引线焊接孔4的中心区域为芯片承载区域。在导电层面,设置了导电图形。
参见图2,载带1在其上的每个芯片承载区域内都预置有相应的胶膜层5,该胶膜层5与芯片承载区域相配合,覆盖住芯片承载区域的表面。胶膜层5的厚度均匀,具体大小可根据实际需求而定,为了保证粘结的可靠性和不影响最终模块的尺寸,一般为5~30um。
基于该载带1在进行封装形成智能卡模块时,参见图1和图2,首先通过全自动芯片上座设备将芯片6安装到载带1的芯片承载区域内预置的胶膜层5上;同时使载带底部受热,加热温度为80℃,使芯片6和载带1之间的胶膜层5融化。
接着,通过载带1上的齿孔2引导载带向前步进,载带步进后离开加热区域,通过自然冷却,使得融化的胶膜层5固化,从而使芯片和载带牢固地粘结在一起。
再接着,通过全自动引线焊接设备将芯片6上的功能焊盘和载带1上相应的焊盘连接起来,引线7连接芯片上的焊盘和导电层3的引线焊接孔4处的连接点,使芯片上的功能焊盘延伸到载带上。
再接着,将焊接好引线的半成品,通过自动点胶设备将紫外线固化型环氧树脂胶8把引线和芯片包封起来,并采用紫外线照射使胶体固化,形成可靠地封装体8。
最后,将封装好的模块通过自动化芯片测试设备对模块进行电性能测试,将不合格品标示出来,合格品进行入库,完成模块的生产过程。
实施例二:
参见图5和图6,其所示为本实例中智能卡载带的芯片安装面示意图和导电层面示意图,在载带1的长边设置了若干个均匀排列的齿孔2,用于设备步进使载带向前移动。在载带的芯片安装面中部,设置了若干个引线焊接孔4,用于将芯片上的功能焊盘和载带上的导电图形连通。引线焊接孔4的中心区域为芯片承载区域。在导电层面,设置了导电图形。
参见图3,其所示为本实例中的芯片6的结构示意图。由图可知,本实例中芯片6在其电路层的反面预置有相应的胶膜层5,该胶膜层5与芯片6电路层的反面相配合,完全覆盖住芯片6电路层的反面。其厚度均匀,具体大小可根据实际需求而定,为了保证粘结的可靠性和不影响最终模块的尺寸,一般为5~30um。
基于上述的载带1和预置胶膜层的芯片6在进行封装形成智能卡模块时,参见图3和图4,通过全自动芯片上座设备将预置了胶膜层的芯片6安装到载带1的芯片承载区域上;同时使载带底部受热,加热温度为60℃,使芯片6和载带1之间的胶膜层5融化。
接着,通过载带1上的齿孔2引导载带向前步进,载带步进后离开加热区域,进行180℃快速烘烤,达到最终固化。该胶膜层5具有再次烘烤加热不能融化及不可回溯特性,这样能够解决引线焊接时由于加热胶层融化或软化引起芯片晃动造成焊接不良,封装过程中受热引发胶层与芯片硅层或条带表面孔洞及分层问题,从而避免影响后续产品可靠性。胶膜层的固化使芯片和载带牢固地粘结在一起。
再接着,通过全自动引线焊接设备将芯片6上的功能焊盘和载带1上相应的焊盘连接起来,引线7连接芯片上的焊盘和导电层3的引线焊接孔4处的连接点,使芯片上的功能焊盘延伸到载带上。
再接着,将焊接好引线的半成品,采用模塑封装工艺,在高温模具内将固体模塑料液化后包封住引线和芯片,待脱模后即形成可靠地封装体引线和芯片包封起来,形成可靠地封装体8。
最后,将封装好的模块通过自动化芯片测试设备对模块进行电性能测试,将不合格品标示出来,合格品进行入库,完成模块的生产过程。
通过上述实例可知,利用本实用新型提供的方案进行智能卡模块的生产,可以省去设备点胶的工序,这样不仅能够使生产制程简化,更重要的是避免了由于点胶制程产生的不良率的问题,提高了产品的合格率和生产效率,有效降低了产品成本,并且整个生产过程可以延用现有设备进行大批量生产。
以上显示和描述了本实用新型的基本原理、主要特征和本实用新型的优点。本行业的技术人员应该了解,本实用新型不受上述实施例的限制,上述实施例和说明书中描述的只是说明本实用新型的原理,在不脱离本实用新型精神和范围的前提下,本实用新型还会有各种变化和改进,这些变化和改进都落入要求保护的本实用新型范围内。本实用新型要求保护范围由所附的权利要求书及其等效物界定。

Claims (9)

1.采用预置胶膜工艺封装的智能卡模块,包括绝缘智能卡载带、芯片和封装体,芯片安装在载带的芯片承载区域,芯片的功能焊盘和载带的焊盘采用引线焊接导通,封装体将芯片和引线包封在绝缘智能卡载带上,其特征在于,所述的芯片与载带的芯片承载区域之间通过预置的胶膜层进行安装。
2.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层预置在智能卡载带的芯片承载区域内或预置在芯片的电路层反面。
3.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层具有随温度变化而产生状态和粘性变化的特性,常温下胶膜层呈固态,加热后胶膜层融化,并产生粘结力,胶膜层的融化温度在50-100℃之间。
4.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层常温下呈固态,50-100℃低温加热后胶膜层具备较强粘性,此状态可以提供芯片上座固定的要求,后经过100-200℃快速烘烤达到最终固化,再次烘烤加热不能融化,具有不可回溯的特性。
5.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层经过一次加热融化后常温固化,在二次加热时不再融化。
6.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层经多次加热后可以多次融化。
7.根据权利要求1至6中任一项所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的胶膜层厚度为5~30um。
8.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述的载带是连续长条形并无限延长的结构。
9.根据权利要求1所述的采用预置胶膜工艺封装的智能卡模块,其特征在于,所述封装体为采用紫外线封装体或者模塑封装体。
CN201420871556.3U 2014-12-30 2014-12-30 一种采用预置胶膜工艺封装的智能卡模块 Active CN204441277U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420871556.3U CN204441277U (zh) 2014-12-30 2014-12-30 一种采用预置胶膜工艺封装的智能卡模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420871556.3U CN204441277U (zh) 2014-12-30 2014-12-30 一种采用预置胶膜工艺封装的智能卡模块

Publications (1)

Publication Number Publication Date
CN204441277U true CN204441277U (zh) 2015-07-01

Family

ID=53609110

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420871556.3U Active CN204441277U (zh) 2014-12-30 2014-12-30 一种采用预置胶膜工艺封装的智能卡模块

Country Status (1)

Country Link
CN (1) CN204441277U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617052A (zh) * 2014-12-30 2015-05-13 上海仪电智能电子有限公司 一种采用预置胶膜工艺封装的智能卡模块及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617052A (zh) * 2014-12-30 2015-05-13 上海仪电智能电子有限公司 一种采用预置胶膜工艺封装的智能卡模块及其封装方法

Similar Documents

Publication Publication Date Title
CN104617051A (zh) 一种预置胶膜的芯片及其实现方法
CN104124216A (zh) 一种基板片式载体csp封装件及其制造方法
CN104241218A (zh) 一种带有散热结构的倒装芯片塑封结构及制造方法
US11735435B2 (en) Quad flat no lead package and method of making
CN104617052A (zh) 一种采用预置胶膜工艺封装的智能卡模块及其封装方法
CN102231372B (zh) 多圈排列无载体ic芯片封装件及其生产方法
CN103985692A (zh) Ac-dc电源电路的封装结构及其封装方法
CN204441277U (zh) 一种采用预置胶膜工艺封装的智能卡模块
CN104617076A (zh) 一种预置胶膜的智能卡载带及其实现方法
CN102097340A (zh) 用cob灌胶封装制作smd的方法
CN203720871U (zh) 一种智能卡
CN203871320U (zh) Ac-dc电源电路的封装结构
CN104600044A (zh) 一种微型智能卡及封装方法
CN204348709U (zh) 一种微型智能卡
CN204441272U (zh) 一种预置胶膜的芯片
CN204348714U (zh) 一种预置胶膜的智能卡载带
CN103985693A (zh) 无刷直流电机集成驱动电路的封装结构及其封装方法
CN205211727U (zh) 一种指纹识别多芯片封装结构
CN106373935A (zh) 一种无基岛框架封装工艺及其封装结构
CN204441273U (zh) 半导体器件以及半导体封装体
CN106935520A (zh) 一种内绝缘封装结构及其制造工艺
CN208444808U (zh) 一种塑封小型固态继电器
CN206250189U (zh) 一种无基岛框架封装结构
CN104538378A (zh) 一种圆片级封装结构及其工艺方法
CN105590904A (zh) 一种指纹识别多芯片封装结构及其制备方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant