CN102097340A - 用cob灌胶封装制作smd的方法 - Google Patents

用cob灌胶封装制作smd的方法 Download PDF

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CN102097340A
CN102097340A CN2010105858453A CN201010585845A CN102097340A CN 102097340 A CN102097340 A CN 102097340A CN 2010105858453 A CN2010105858453 A CN 2010105858453A CN 201010585845 A CN201010585845 A CN 201010585845A CN 102097340 A CN102097340 A CN 102097340A
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emc
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陈�光
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Kodenshi Corp
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Kodenshi Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

本发明属芯片封装技术领域，尤其涉及一种用COB灌胶封装制作SMD的方法，它包括如下步骤：（1）芯片固晶，将芯片粘接在PCB上的指定位置；（2）金线绑定，将芯片与相应的PCB上的金属焊盘用金线键合进行电气连接；（3）注胶边框粘接，在功能区边沿用边框围住，以准备下一步的注胶操作；（4）注胶并固化，向边框区域内注入液态的EMC，注胶完毕后加热使EMC固化；（5）分离，将各个制品进行分离。本发明兼容性好，EMC封装无需特定模具，EMC注入工序作业简单，无需太高尺寸精度，封装后，制品表面平整度高。

Description

用COB灌胶封装制作SMD的方法
技术领域
本发明属芯片封装技术领域，尤其涉及一种用COB灌胶封装制作SMD的方法。
背景技术
用COB技术封装的裸芯片是芯片主体和I/O端子在晶体上方，在焊接时将此裸芯片用导电/导热胶粘接在PCB上，凝固后，用 Bonder 机将金属丝(Al或Au)在超声、热压的作用下，分别连接在芯片的I/O端子焊区和PCB相对应的焊盘上，测试合格后，再封上树脂胶。
现有技术COB灌装SMD产品，在具体工艺上大致存在两种情况：（1）采用自由形状点胶方式，这种方式是直接把液态的EMC点滴到PCB上芯片和金线的位置，依靠重力及EMC的表面张力来形成一个水滴状的EMC。采用这种方式，势必造成SMD成品的EMC表面呈现不规则形状；（2）封装后留有边框的方式，这种方式是每个制品都有一个边框，在边框中填注EMC，这种方式，因为边框最终是跟制品一体的，所以粘接边框是对机械精度要求很高而且因为注入EMC的数量较小，其表面有明显的凸面或凹面。
发明内容
本发明旨在克服现有技术的不足之处而提供一种兼容性好，EMC封装无需特定模具，EMC注入工序作业简单，无需太高尺寸精度，封装后，制品表面平整度高的用COB灌胶封装制作SMD的方法。
为达到上述目的，本发明是这样实现的。
一种用COB灌胶封装制作SMD的方法，它包括如下步骤：（1）芯片固晶，将芯片粘接在PCB上的指定位置；（2）金线绑定，将芯片与相应的PCB上的金属焊盘用金线键合进行电气连接；（3）注胶边框粘接，在功能区边沿用边框围住，以准备下一步的注胶操作；（4）注胶并固化，向边框区域内注入液态的EMC，注胶完毕后加热使EMC固化；（5）分离，将各个制品进行分离。
作为一种优选方案，本发明在步骤（3）中，注胶前使用填充物把PCB上的过孔塞住以防止胶液向背面渗漏。
作为另一种优选方案，本发明在步骤（5）中，使用划片机完成制品分离。
本发明兼容性好，EMC封装无需特定模具，EMC注入工序作业简单，无需太高尺寸精度，封装后，制品表面平整度高。
本发明因为边框的存在，能够形成一个十分规则的平面。另外，由于本发明的边框最终是要除掉的，所以对其粘接的机型精度要求较低，而其因为是多个制品区域作为一个整体来注胶的，一次注胶的量相对较大，最终胶液的表面能够较容易的控制其平整度。
附图说明
下面结合附图和具体实施方式对本发明作进一步说明。
图1为本发明的制成品整体结构示意图。
图2为本发明图1的仰视图。
图3为本发明分割作业工序示意图。
图中：1为EMC层；2为芯片；3为PCB层；4为焊盘；5为金线。
具体实施方式
参见图1～3，用COB灌胶封装制作SMD的方法，它包括如下步骤：（1）芯片固晶，将芯片粘接在PCB上的指定位置；（2）金线绑定，将芯片与相应的PCB上的金属焊盘用金线键合进行电气连接；（3）注胶边框粘接，在功能区边沿用边框围住，以准备下一步的注胶操作；注胶前使用填充物把PCB上的过孔塞住以防止胶液向背面渗漏；（4）注胶并固化，向边框区域内注入液态的EMC，注胶完毕后加热使EMC固化；（5）分离，使用划片机完成制品分离。
如图1所示，用COB灌胶封装方法制作SMD的成品，它包括EMC层1、芯片2、PCB层3及固接于PCB层3上的焊盘4；所述芯片2与PCB层3固定粘接；所述芯片2经金线5与焊盘4键合连接；所述EMC层1与PCB层固定封接；所述EMC层1的表面呈平面。
可以理解地是，以上关于本发明的具体描述，仅用于说明本发明而并非受限于本发明实施例所描述的技术方案，本领域的普通技术人员应当理解，仍然可以对本发明进行修改或等同替换，以达到相同的技术效果；只要满足使用需要，都在本发明的保护范围之内。

Claims (3)

1.一种用COB灌胶封装制作SMD的方法，其特征在于，包括如下步骤：
（1）芯片固晶，将芯片粘接在PCB上的指定位置；
（2）金线绑定，将芯片与相应的PCB上的金属焊盘用金线键合进行电气连接；
（3）注胶边框粘接，在功能区边沿用边框围住，以准备下一步的注胶操作； 
（4）注胶并固化，向边框区域内注入液态的EMC，注胶完毕后加热使EMC固化；
（5）分离，将各个制品进行分离。
2.根据权利要求1所述的用COB灌胶封装制作SMD的方法，其特征在于：在步骤（3）中，注胶前使用填充物把PCB上的过孔塞住以防止胶液向背面渗漏。
3.根据权利要求2所述的用COB灌胶封装制作SMD的方法，其特征在于：在步骤（5）中，使用划片机完成制品分离。
CN2010105858453A 2010-12-14 2010-12-14 用cob灌胶封装制作smd的方法 Pending CN102097340A (zh)

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Cited By (5)

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Publication number Priority date Publication date Assignee Title
CN103258934A (zh) * 2012-04-09 2013-08-21 东莞市久祥电子有限公司 晶片型led线路板运用刷油墨防止封装过程溢胶的方法
CN105611750A (zh) * 2015-12-21 2016-05-25 台州市日昌晶灯饰有限公司 彩灯控制电路板的制作工艺
CN108090267A (zh) * 2017-12-11 2018-05-29 广州全界通讯科技有限公司 一种pcb版图结构
CN109659241A (zh) * 2018-12-11 2019-04-19 沈阳中光电子有限公司 一种在引线框架上连接两种类型芯片的方法
CN114326192A (zh) * 2021-12-29 2022-04-12 深圳市晶惠迪电子有限公司 一种宽视角fstn cog液晶显示屏的制作方法

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103258934A (zh) * 2012-04-09 2013-08-21 东莞市久祥电子有限公司 晶片型led线路板运用刷油墨防止封装过程溢胶的方法
CN103258934B (zh) * 2012-04-09 2017-03-22 东莞市久祥电子有限公司 晶片型led线路板运用刷油墨防止封装过程溢胶的方法
CN105611750A (zh) * 2015-12-21 2016-05-25 台州市日昌晶灯饰有限公司 彩灯控制电路板的制作工艺
CN108090267A (zh) * 2017-12-11 2018-05-29 广州全界通讯科技有限公司 一种pcb版图结构
CN108090267B (zh) * 2017-12-11 2022-02-11 广州全界通讯科技有限公司 一种pcb版图结构
CN109659241A (zh) * 2018-12-11 2019-04-19 沈阳中光电子有限公司 一种在引线框架上连接两种类型芯片的方法
CN109659241B (zh) * 2018-12-11 2021-05-11 沈阳中光电子有限公司 一种在引线框架上连接两种类型芯片的方法
CN114326192A (zh) * 2021-12-29 2022-04-12 深圳市晶惠迪电子有限公司 一种宽视角fstn cog液晶显示屏的制作方法
CN114326192B (zh) * 2021-12-29 2023-06-30 深圳市晶惠迪电子有限公司 一种宽视角fstn cog液晶显示屏的制作方法

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Application publication date: 20110615