CN103985692A - Ac-dc电源电路的封装结构及其封装方法 - Google Patents

Ac-dc电源电路的封装结构及其封装方法 Download PDF

Info

Publication number
CN103985692A
CN103985692A CN201410212841.9A CN201410212841A CN103985692A CN 103985692 A CN103985692 A CN 103985692A CN 201410212841 A CN201410212841 A CN 201410212841A CN 103985692 A CN103985692 A CN 103985692A
Authority
CN
China
Prior art keywords
chip
lead frame
island
control
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410212841.9A
Other languages
English (en)
Inventor
阮怀其
王士勇
汪银凤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Original Assignee
ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd filed Critical ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Priority to CN201410212841.9A priority Critical patent/CN103985692A/zh
Publication of CN103985692A publication Critical patent/CN103985692A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及一种AC-DC电源电路的封装结构，包括引线框架，控制IC芯片、输出开关管芯片、高压启动电阻均粘接在引线框架的基岛上且与引线框架电性连接，控制IC芯片、输出开关管芯片、高压启动电阻与引线框架通过包封塑料包封固化。本发明还公开了一种AC-DC电源电路的封装结构的封装方法。本发明采用的控制IC芯片相对于采用高压制造工艺的IC芯片价格便宜，降低了IC芯片的成本；本发明电路在应用时，PCB板外围搭配的器件较少，首先减少了应用的成本，其次减小了PCB板的体积，有利于产品的小型化，再者也提高了应用时的生产效率。

Description

AC-DC电源电路的封装结构及其封装方法
 
技术领域
本发明涉及集成电路封装技术领域，尤其是一种AC-DC电源电路的封装结构及其封装方法。
 
背景技术
目前，LED照明领域使用的AC-DC电源电路基本采用高压制造工艺的IC芯片来封装，但是这种电路存在着如下缺点：第一，采用高压制造工艺的IC芯片，由于工艺比较复杂，芯片制造成本较高；第二，采用高压制造工艺的IC芯片封装的AC-DC电源电路在应用时PCB板外围搭配的器件较多，首先导致应用成本较高，其次导致PCB板体积较大，不利于产品的小型化，再者也影响了应用时的生产效率。
发明内容
本发明的首要目的在于提供一种体积小、成本低、提高生产线效率的AC-DC电源电路的封装结构。
为实现上述目的，本发明采用了以下技术方案：一种AC-DC电源电路的封装结构，包括引线框架，控制IC芯片、输出开关管芯片、高压启动电阻均粘接在引线框架的基岛上且与引线框架电性连接，控制IC芯片、输出开关管芯片、高压启动电阻与引线框架通过包封塑料包封再后固化。
所述引线框架的一侧上设置供控制IC芯片粘接的小基岛，小基岛的外围布置第一、二、三、四引脚，小基岛与第二引脚一体成型；所述引线框架的另一侧上设置供输出开关管芯片粘接的大基岛，大基岛的外围布置第五、六、七、八引脚，大基岛与第五、六、七、八引脚一体成型；所述小基岛、大基岛之间布置中间引脚，高压启动电阻的一端粘接在大基岛上，另一端粘接在中间引脚上。
所述包封塑料采用环氧树脂。
所述控制IC芯片与输出开关管芯片之间、所述控制IC芯片与中间引脚之间、所述控制IC芯片与第一、二、三、四引脚之间均通过键合导线连接。
所述控制IC芯片、输出开关管芯片、高压启动电阻均通过芯片粘接剂粘接在引线框架的基岛上，所述芯片粘接剂为银胶。
所述键合导线采用金线或铜线。
本发明的另一目的在于提供一种AC-DC电源电路的封装结构的封装方法，该方法包括下列顺序的步骤：
（1）利用自动粘片机将控制IC芯片、输出开关管芯片、高压启动电阻通过芯片粘接剂粘接在引线框架的基岛上；
（2）利用自动键合机使控制IC芯片与输出开关管芯片、中间引脚、第一、二、三、四引脚之间电性连接；
（3）利用注塑压机对粘接有控制IC芯片、输出开关管芯片和高压启动电阻的引线框架进行包封，然后再后固化。
将粘接好控制IC芯片、输出开关管芯片和高压启动电阻的引线框架放入充有氮气的烘箱内进行高温烘烤，使芯片粘接剂固化，再进行自动键合。
在包封后固化后，利用电镀机将引线框架外侧的引脚镀上锡层，锡层厚度为5～15um。
由上述技术方案可知，本发明采用的控制IC芯片相对于采用高压制造工艺的IC芯片价格便宜，降低了IC芯片的成本；本发明电路在应用时，PCB板外围搭配的器件较少，首先减少了应用的成本，其次减小了PCB板的体积，有利于产品的小型化，再者也提高了应用时的生产效率。
 
附图说明
图1为本发明中引线框架的结构示意图；
图2为本发明中控制IC芯片、输出开关管芯片和高压启动电阻粘接在引线框架后的示意图；
图3为本发明的键合打线示意图；
图4为本发明的封装外形俯视图；
图5为本发明的封装外形侧视图；
图6为本发明的封装外形正视图。
具体实施方式
一种AC-DC电源电路的封装结构，包括引线框架1，控制IC芯片5、输出开关管芯片6、高压启动电阻7均粘接在引线框架1的基岛上且与引线框架1电性连接，控制IC芯片5、输出开关管芯片6、高压启动电阻7与引线框架1通过包封塑料包封再后固化，如图1至6所示。
如图2所示，所述引线框架1的一侧上设置供控制IC芯片5粘接的小基岛2，小基岛2的外围布置第一、二、三、四引脚，第一、二、三、四引脚分别对应图2中的PIN1、PIN2、PIN3、PIN4，小基岛2与第二引脚一体成型；所述引线框架1的另一侧上设置供输出开关管芯片6粘接的大基岛3，大基岛3的外围布置第五、六、七、八引脚，第五、六、七、八引脚分别对应图2中的PIN5、PIN6、PIN7、PIN8，大基岛3与第五、六、七、八引脚一体成型；所述小基岛2、大基岛3之间布置中间引脚4，高压启动电阻7的一端粘接在大基岛3上，另一端粘接在中间引脚4上。所述控制IC芯片5、输出开关管芯片6、高压启动电阻7均通过芯片粘接剂粘接在引线框架1的基岛上，所述芯片粘接剂为银胶。
如图3所示，所述控制IC芯片5与输出开关管芯片6之间、所述控制IC芯片5与中间引脚4之间、所述控制IC芯片5与第一、二、三、四引脚之间均通过键合导线连接，所述键合导线采用金线或铜线。
本发明在封装时，首先，利用自动粘片机将控制IC芯片5、输出开关管芯片6、高压启动电阻7通过芯片粘接剂粘接在引线框架1的基岛上，将粘接好控制IC芯片5、输出开关管芯片6和高压启动电阻7的引线框架1放入充有氮气的烘箱内进行高温烘烤，使芯片粘接剂固化，再进行自动键合；其次，利用自动键合机使控制IC芯片5与输出开关管芯片6、中间引脚4、第一、二、三、四引脚之间电性连接；最后利用注塑压机对粘接有控制IC芯片5、输出开关管芯片6和高压启动电阻7的引线框架1进行包封，然后再后固化，所述包封塑料采用环氧树脂，本发明中的包封材料为汉高华威的KL4000-1TF型号塑封料，该塑封料的后固化温度为175℃，需要加热4个小时；在包封后固化后，利用电镀机将引线框架1外侧的引脚镀上锡层，锡层厚度为5～15um，图6两端引出的引线是镀锡的引脚；通过自动激光打标机，在塑封体表面打上产品型号、批号等信息；通过自动切筋打弯机，对整个封装结构进行切筋打弯成型。
综上所述，本发明将控制IC芯片5、输出开关管芯片6和高压启动电阻7封装在一起，相对于采用高压制造工艺的IC价格便宜，且减少了PCB板外围器件和体积，降低了成本； 便于生产，提高了生产效率。

Claims (9)

1.一种AC-DC电源电路的封装结构，其特征在于：包括引线框架，控制IC芯片、输出开关管芯片、高压启动电阻均粘接在引线框架的基岛上且与引线框架电性连接，控制IC芯片、输出开关管芯片、高压启动电阻与引线框架通过包封塑料包封再后固化。
2.根据权利要求1所述的AC-DC电源电路的封装结构，其特征在于：所述引线框架的一侧上设置供控制IC芯片粘接的小基岛，小基岛的外围布置第一、二、三、四引脚，小基岛与第二引脚一体成型；所述引线框架的另一侧上设置供输出开关管芯片粘接的大基岛，大基岛的外围布置第五、六、七、八引脚，大基岛与第五、六、七、八引脚一体成型；所述小基岛、大基岛之间布置中间引脚，高压启动电阻的一端粘接在大基岛上，另一端粘接在中间引脚上。
3.根据权利要求1所述的AC-DC电源电路的封装结构，其特征在于：所述包封塑料采用环氧树脂。
4.根据权利要求2所述的AC-DC电源电路的封装结构，其特征在于：所述控制IC芯片与输出开关管芯片之间、所述控制IC芯片与中间引脚之间、所述控制IC芯片与第一、二、三、四引脚之间均通过键合导线连接。
5.根据权利要求2所述的AC-DC电源电路的封装结构，其特征在于：所述控制IC芯片、输出开关管芯片、高压启动电阻均通过芯片粘接剂粘接在引线框架的基岛上，所述芯片粘接剂为银胶。
6.根据权利要求4所述的AC-DC电源电路的封装结构，其特征在于：所述键合导线采用金线或铜线。
7.根据权利要求1至6中任一项所述封装结构的封装方法，该方法包括下列顺序的步骤：
（1）利用自动粘片机将控制IC芯片、输出开关管芯片、高压启动电阻通过芯片粘接剂粘接在引线框架的基岛上；
（2）利用自动键合机使控制IC芯片与输出开关管芯片之间、控制IC芯片与中间引脚之间、控制IC芯片与第一、二、三、四引脚之间均通过键合导线连接；
（3）利用注塑压机对粘接有控制IC芯片、输出开关管芯片和高压启动电阻的引线框架进行包封，然后再后固化。
8.根据权利要求7所述的封装方法，其特征在于：将粘接好控制IC芯片、输出开关管芯片和高压启动电阻的引线框架放入充有氮气的烘箱内进行高温烘烤，使芯片粘接剂固化，再进行自动键合。
9.根据权利要求7所述的封装方法，其特征在于：在包封后固化后，利用电镀机将引线框架外侧的引脚镀上锡层，锡层厚度为5～15um。
CN201410212841.9A 2014-05-20 2014-05-20 Ac-dc电源电路的封装结构及其封装方法 Pending CN103985692A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410212841.9A CN103985692A (zh) 2014-05-20 2014-05-20 Ac-dc电源电路的封装结构及其封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410212841.9A CN103985692A (zh) 2014-05-20 2014-05-20 Ac-dc电源电路的封装结构及其封装方法

Publications (1)

Publication Number Publication Date
CN103985692A true CN103985692A (zh) 2014-08-13

Family

ID=51277604

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410212841.9A Pending CN103985692A (zh) 2014-05-20 2014-05-20 Ac-dc电源电路的封装结构及其封装方法

Country Status (1)

Country Link
CN (1) CN103985692A (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331657A (zh) * 2017-06-28 2017-11-07 河南索泰克照明股份有限公司 一种ic与可控硅芯片一体化封装及其制作方法
CN108735724A (zh) * 2017-04-18 2018-11-02 深圳市德润达光电股份有限公司 一种led线性驱动电源的微型集成模块
CN108962857A (zh) * 2018-09-10 2018-12-07 无锡豪帮高科股份有限公司 一种融合smt的sip集成电路封装结构
CN109119393A (zh) * 2018-09-10 2019-01-01 无锡豪帮高科股份有限公司 一种融合smt的mcm集成电路封装结构
CN109378307A (zh) * 2018-12-07 2019-02-22 无锡豪帮高科股份有限公司 一种多芯片的模块式封装结构
CN110572909A (zh) * 2019-09-12 2019-12-13 山东晶导微电子股份有限公司 Led照明电路及其芯片封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201655805U (zh) * 2010-04-26 2010-11-24 日银Imp微电子有限公司 一种半桥驱动电路芯片
CN202231011U (zh) * 2011-08-26 2012-05-23 深圳市力生美半导体器件有限公司 开关电源用集成电路
CN203871320U (zh) * 2014-05-20 2014-10-08 安徽国晶微电子有限公司 Ac-dc电源电路的封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201655805U (zh) * 2010-04-26 2010-11-24 日银Imp微电子有限公司 一种半桥驱动电路芯片
CN202231011U (zh) * 2011-08-26 2012-05-23 深圳市力生美半导体器件有限公司 开关电源用集成电路
CN203871320U (zh) * 2014-05-20 2014-10-08 安徽国晶微电子有限公司 Ac-dc电源电路的封装结构

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735724A (zh) * 2017-04-18 2018-11-02 深圳市德润达光电股份有限公司 一种led线性驱动电源的微型集成模块
CN107331657A (zh) * 2017-06-28 2017-11-07 河南索泰克照明股份有限公司 一种ic与可控硅芯片一体化封装及其制作方法
CN108962857A (zh) * 2018-09-10 2018-12-07 无锡豪帮高科股份有限公司 一种融合smt的sip集成电路封装结构
CN109119393A (zh) * 2018-09-10 2019-01-01 无锡豪帮高科股份有限公司 一种融合smt的mcm集成电路封装结构
CN108962857B (zh) * 2018-09-10 2023-11-10 无锡豪帮高科股份有限公司 一种融合smt的sip集成电路封装结构的生产方法
CN109119393B (zh) * 2018-09-10 2024-03-29 无锡豪帮高科股份有限公司 一种融合smt的mcm集成电路封装结构
CN109378307A (zh) * 2018-12-07 2019-02-22 无锡豪帮高科股份有限公司 一种多芯片的模块式封装结构
CN109378307B (zh) * 2018-12-07 2023-11-10 无锡豪帮高科股份有限公司 一种多芯片的模块式封装结构的生产方法
CN110572909A (zh) * 2019-09-12 2019-12-13 山东晶导微电子股份有限公司 Led照明电路及其芯片封装结构

Similar Documents

Publication Publication Date Title
CN103985692A (zh) Ac-dc电源电路的封装结构及其封装方法
CN203871320U (zh) Ac-dc电源电路的封装结构
CN203720871U (zh) 一种智能卡
CN201655787U (zh) 半导体封装结构
CN103985693A (zh) 无刷直流电机集成驱动电路的封装结构及其封装方法
CN102097340A (zh) 用cob灌胶封装制作smd的方法
CN103606539A (zh) 一种基于框架采用开孔优化技术的扁平封装件及其制作工艺
CN103050451A (zh) 一种双排引脚四面扁平无引脚封装件及其绝缘处理方法
CN205211727U (zh) 一种指纹识别多芯片封装结构
CN203871321U (zh) 无刷直流电机集成驱动电路的封装结构
CN104009026A (zh) 胎压传感器电路的封装结构及其封装方法
CN105489741A (zh) 一种led倒装芯片的压模封装工艺
CN201829490U (zh) 芯片区打孔集成电路引线框架
CN104617002A (zh) 一种半导体封装方法及结构
CN104617052A (zh) 一种采用预置胶膜工艺封装的智能卡模块及其封装方法
CN209515637U (zh) 一种功率模块结构
CN105590904A (zh) 一种指纹识别多芯片封装结构及其制备方法
CN102738009A (zh) 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺
CN203536411U (zh) 一种半导体封装结构
CN105470213A (zh) 一次封装成型的光距离传感器封装结构及其制造方法
CN201514940U (zh) 一种集成电路封装用引线框架结构
CN104600044A (zh) 一种微型智能卡及封装方法
CN203481191U (zh) 一种基于框架采用预塑封优化技术的aaqfn封装件
CN203882999U (zh) 胎压传感器电路的封装结构
CN204348709U (zh) 一种微型智能卡

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140813

WD01 Invention patent application deemed withdrawn after publication