CN1755908A - 一种提高塑料封装集成电路合格率的方法 - Google Patents

一种提高塑料封装集成电路合格率的方法 Download PDF

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CN1755908A
CN1755908A CNA2004100668480A CN200410066848A CN1755908A CN 1755908 A CN1755908 A CN 1755908A CN A2004100668480 A CNA2004100668480 A CN A2004100668480A CN 200410066848 A CN200410066848 A CN 200410066848A CN 1755908 A CN1755908 A CN 1755908A
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聂纪平
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Shanghai Beiling Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

一种提高塑料封装集成电路合格率的方法,包含下列步骤:减薄→绷膜→划片→粘片→键合→模封→固化→电镀,其特点是,在上述键合和模封步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封。采用了上述的技术解决方案,即采用覆层材料在硅片表面均匀涂覆后再模封,从而缓解由于设计或者工艺缺陷造成的器件应力相关的失效。本发明可以有效地提高很多集成电路器件由于设计缺陷造成的失效,在不改变现有设计和工艺的基础上改进器件性能。

Description

一种提高塑料封装集成电路合格率的方法
技术领域
本发明涉及一种提高塑料封装集成电路合格率的方法。
背景技术
现有一般集成电路,大多采用塑料封装形式,主要封装形式有:塑料双列直插封装壳(PDIP)、塑料有引线芯片载体(PLCC)、四边扁平封装(QFP)、小外形封装(SOP)、TSOP(薄小外形封装)、SSOP(缩小型SOP)、TSSOP(薄的缩小型SOP),等。
封装主要是考虑器件的功率、重量、引脚数、尺寸、密度、电响应、可靠性、热耗散等等。对于器件的功能和合格率一般不是封装技术考虑的因素。
塑料封装的主要工艺流程如下:
1:减薄(Back grinding):指将晶圆通过背面打磨使之厚度控制在一定的范围。
2:绷膜(Wafer Mounting):绷膜主要是给晶圆的背面贴上一层有弹性和一定粘性的蓝膜,并固定在一个直径稍大的金属框架上。为了避免粘贴不牢靠而造成划片的过程中的飞片问题,在绷膜的过程中要加热60~80度的温度。
3:划片(Wafer Sawing):划片的目的是将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来。如果前面绷膜的时候晶圆粘贴不牢靠或者有气泡存在,切割开来的硅片(Die)就会从蓝膜上飞出来,称作飞片。
4:粘片(Die Attach):粘片是通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上。根据器件的封装类型不同,载体也有区别。常规封装,所用的载体是引线框架。对于集成电路,一般选用的焊接材料为银胶(Epoxy Glue),在粘片的过程中,引线框架不需要加热。银胶是一种导电材料和其他化学物质的混合物,在粘片之后,引线框架要放置到固化炉(CuringOven)中一定时间,使银胶固化。
5:键合(Wire Bonding):用金属线将硅片上的电气连接点(bond pad)和引线框架上的管脚(lead)或者基板上的焊盘连接起来。
6:模封(Molding):使用固态环氧树脂模封材料(EPOXY MOLDINGCOMPOUND)的移转注模成型制程。
7:固化(Curing):在一定温度下使固态环氧树脂模封材料固化成型。
8:电镀(Plating):采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性。
9:切筋成型(Trimming Forming):将成型的器件切开并且排列好。
10:测试/分选(Testing/Binning):对于器件进行简单的开短路测试,把封装过程中的失效器件删选掉。
封装完成后的器件如图1所示,在粘片1上层的粘片粘胶2上放置硅片3,用金属线5将硅片3上的电气连接点与框架上的管脚4相连,用固态环氧树脂模封材料6固化成型。
在上述的封装过程中,由于集成电路芯片(Die)和塑封材料(EPOXYMOLDING COMPOUND)的热系数不同,有可能会在固化和SMT(表面贴装)之后造成和封装相关的失效,造成在塑料封装以后半导体器件的合格率大幅下降。这种失效一般是在集成电路设计和工艺中未充分考虑封装材料热应力造成的。
发明内容
本发明的目的在于通过改进塑料封装大规模集成电路的封装方法,提高塑料封装集成电路合格率。
本发明所提供的一种提高塑料封装集成电路合格率的方法,包括下列步骤:第一,减薄,即将晶圆通过背面打磨使之厚度控制在规定的范围内;第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;第六,模封,即使用固态环氧树脂模封材料注模成型;第七,固化,即在规定温度下使固态环氧树脂模封材料固化成型;第八,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性;其特征在于:在上述加工的第五和第六步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封。
采用了上述的技术解决方案,本发明在现有的塑料封装方法中,增加一步硅片覆层步骤,即采用覆层材料在硅片表面均匀涂覆后再模封,从而缓解由于设计或者工艺缺陷造成的器件应力相关的失效。本发明可以有效地提高很多集成电路器件由于设计缺陷造成的失效,在不改变现有设计和工艺的基础上改进器件性能。
附图说明
图1是现有塑封器件纵向剖面示意图;
图2是本发明塑封器件纵向剖面示意图。
具体实施方式
本发明,即一种提高塑料封装集成电路合格率的方法,包括下列步骤:
第一,减薄,即将晶圆通过背面打磨使之厚度控制在规定的范围内;
第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;在绷膜的过程中要。
第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;
第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;
第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;
第六,覆层,即采用涂层材料在硅片表面均匀涂覆后再模封。
第七,模封,即使用固态环氧树脂模封材料注模成型;
第八,固化,即在规定温度下使固态环氧树脂模封材料固化成型;
第九,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性。
封装完成后的器件如图2所示,在粘片1上层的粘片粘胶2上放置硅片3,在硅片表面均匀涂覆涂层7,用金属线5将硅片3上的电气连接点与框架上的管脚4相连,用固态环氧树脂模封材料6固化成型。
本发明在现有的塑料封装工艺中,改进了一般的封装流程,在现有工艺步骤5和6之间增加一步标准的Die coating(硅片涂层)工艺,即采用coating(涂层)材料在硅片(Die)表面均匀涂覆后再模封。这步工艺的特点在于可以缓解由于设计或者工艺缺陷造成的器件应力相关的失效。通过封装工艺改进解决了设计或者工艺问题。
本发明对于通讯类专用集成电路产品,采用普通的PLCC封装,由于设计上存在未考虑周到的问题,导致该器件存在一定的由于应力不均匀造成的大量失效。采用Die coating封装改进后,可以大大解决该失效。明显提高了合格率。

Claims (1)

1.一种提高塑料封装集成电路合格率的方法,包括下列步骤:
第一,减薄,即将晶圆通过背面打磨使之厚度控制在规定的范围内;
第二,绷膜,即加热至60~80度的温度,给晶圆的背面贴上一层有弹性和粘性的蓝膜,并固定在一金属框架上;
第三,划片,即将整个晶圆上每一个独立的电路通过高速旋转的金刚石刀片切割开来;
第四,粘片,即通过机械臂驱动真空吸嘴将切割完成的硅片(Die)放置并焊接在载体上;
第五,键合,即用金属线将硅片上的电气连接点和引线框架上的管脚或者基板上的焊盘连接起来;
第六,模封,即使用固态环氧树脂模封材料注模成型;
第七,固化,即在规定温度下使固态环氧树脂模封材料固化成型;
第八,电镀,采用电镀方法给封装成型的器件引脚电镀,以增强器件的可焊性;
其特征在于:
在上述加工的第五和第六步骤之间增加一硅片覆层步骤,即采用涂层材料在硅片表面均匀涂覆后再模封。
CNA2004100668480A 2004-09-29 2004-09-29 一种提高塑料封装集成电路合格率的方法 Pending CN1755908A (zh)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194708A (zh) * 2010-03-19 2011-09-21 万国半导体有限公司 一种薄型封装的工艺
CN102024711B (zh) * 2009-09-23 2012-06-27 上海贝岭股份有限公司 一种提高plcc封装集成电路合格率的方法
CN109473361A (zh) * 2018-10-24 2019-03-15 深圳赛意法微电子有限公司 半导体功率器件的并行测试方法
CN109817533A (zh) * 2017-11-22 2019-05-28 东莞市广信知识产权服务有限公司 一种基于芯片级封装外壳的半导体器件的制作方法
CN113140467A (zh) * 2019-07-31 2021-07-20 深圳宏芯宇电子股份有限公司 集成电路封装方法及半导体器件
CN114623955A (zh) * 2021-10-18 2022-06-14 胡耿 微小极间距电容式力敏传感器及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024711B (zh) * 2009-09-23 2012-06-27 上海贝岭股份有限公司 一种提高plcc封装集成电路合格率的方法
CN102194708A (zh) * 2010-03-19 2011-09-21 万国半导体有限公司 一种薄型封装的工艺
CN109817533A (zh) * 2017-11-22 2019-05-28 东莞市广信知识产权服务有限公司 一种基于芯片级封装外壳的半导体器件的制作方法
CN109473361A (zh) * 2018-10-24 2019-03-15 深圳赛意法微电子有限公司 半导体功率器件的并行测试方法
CN113140467A (zh) * 2019-07-31 2021-07-20 深圳宏芯宇电子股份有限公司 集成电路封装方法及半导体器件
CN114623955A (zh) * 2021-10-18 2022-06-14 胡耿 微小极间距电容式力敏传感器及其制造方法

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