CN103681613A - 具有离散块的半导体器件 - Google Patents

具有离散块的半导体器件 Download PDF

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Publication number
CN103681613A
CN103681613A CN201310071610.6A CN201310071610A CN103681613A CN 103681613 A CN103681613 A CN 103681613A CN 201310071610 A CN201310071610 A CN 201310071610A CN 103681613 A CN103681613 A CN 103681613A
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Prior art keywords
semiconductor device
tube core
contiguous block
layer
interconnection layer
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CN201310071610.6A
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CN103681613B (zh
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萧景文
陈承先
张纬森
胡延章
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了半导体器件及其制造方法。具体地，提供具有形成在其中的通孔和/或集成无源器件的诸如离散连接块的使用块的半导体器件。诸如本发明中所公开的实施例可以用于PoP应用中。在实施例中，半导体器件包括封装在模塑料中的管芯和连接块。互连层可以形成在管芯、连接块以及模塑料的表面上。一个或多个管芯和/或封装件可以附接至互连层。本发明还提供了具有离散块的半导体器件。

Description

具有离散块的半导体器件
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件及其形成方法。
背景技术
由于集成电路的发明，半导体工业由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进而经历了持续快速发展。在大多数情况下，这种集成密度的改进源自最小特征尺寸的反复减小，从而允许更多部件集成在给定芯片面积内。实际上，这些集成改进基本是二维(2D)的，其中，集成部件所占用的体积基本位于半导体晶圆的表面上。尽管在光刻的显著改进已经导致2D集成电路形成期间的大幅改进，但是存在对可以以二维实现的密度的物理限制。这些限制中一种限制是制造这些元件所需要的最小尺寸。此外，当将更多器件置于一个芯片中时，需要更复杂的设计。
一种已经开发的封装技术是封装件叠层(PoP)。如其名称所暗示，PoP是涉及在另一个封装件的顶部堆叠一个封装件的半导体封装创新。例如，PoP器件可以垂直组合离散存储器和逻辑球栅阵列(BGA)封装件。在PoP封装件设计中，顶部封装件可以通过外围焊球、引线接合等互连至底部封装件。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：管芯，具有电接触件；第一材料；以及第二材料，介于所述管芯和所述第一材料之间，所述第二材料和所述第一材料沿着所述管芯的长轴定位，所述第一材料包括延伸穿过所述第一材料的一个或多个导电部件。
在该半导体器件中，所述第一材料是硅。
在该半导体器件中，所述第一材料是二氧化硅。
在该半导体器件中，所述一个或多个导电部件包括至少一个通孔。
在该半导体器件中，所述一个或多个导电部件包括至少一个集成无源器件。
该半导体器件进一步包括在所述管芯和所述第一材料的第一面上方延伸的第一互连层。
该半导体器件进一步包括在所述管芯和所述第一材料的第二面上方延伸的第二互连层。
该半导体器件进一步包括位于所述管芯上方的封装管芯，所述封装管芯与延伸穿过所述第一材料的一个或多个导电部件电耦合。
在该半导体器件中，所述一个或多个导电部件包括电连接在一起的多个集成无源器件。
根据本发明的另一方面，提供了一种半导体器件，包括：顶部封装件；以及底部封装件，可操作地耦合至所述顶部封装件，所述底部封装件包括管芯和通过模塑料与所述管芯间隔开的连接块。
在该半导体器件中，所述连接块包括硅。
在该半导体器件中，所述连接块包括二氧化硅。
在该半导体器件中，所述连接块包括多个通孔。
在该半导体器件中，所述连接块包括多个集成无源器件。
根据本发明的又一方面，提供了一种形成半导体器件的方法，所述方法包括：提供管芯；提供具有一个或多个导电元件的连接块；以及形成包括通过材料层间隔开的所述管芯和所述连接块的层，所述连接块的材料不同于所述材料层的材料。
在该方法中，所述一个或多个导电元件包括一个或多个通孔。
在该方法中，所述一个或多个导电元件包括一个或多个集成无源器件。
在该方法中，所述层包括模塑料。
该方法进一步包括在所述管芯和所述连接块的第一面上方形成第一互连层。
该方法进一步包括在所述管芯和所述连接块的第二面上方形成第二互连层。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1a至图1c示出了实施例的截面图和平面图；
图2a至图2c示出了根据实施例的块的放大的截面图；
图3示出了涉及PoP器件的实施例的截面图；以及
图4a-4j示出了实施例的构造的工艺流程图。
具体实施方式
下面详细讨论实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅为示出制造和使用所公开的主题的具体方式，而不用于限制不同实施例的范围。
将结合具体环境(即，具有集成无源器件(IPD)的封装件叠层(PoP)结构)描述实施例。具体实施例将突出封装在模塑料中的离散块(诸如离散硅或SiO2块)的使用。离散块可以用于形成IPD、通过通孔(TV)(例如，硅通孔(TSV))和/或类似结构，以提供PoP应用中的电连接件。其他实施例可以用于其他应用(诸如中介层、封装衬底等)。
图1a示出了根据实施例的第一封装件10的截面图。第一封装件10包括具有耦合至其的一个或多个管芯(示出了一个管芯12)的第一互连层11。第一互连层11可以包括具有形成在其中的导电部件(示出为导电部件15)的一个或多个介电材料16层。在实施例中，介电材料16层由感光材料形成，诸如，聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等，可以使用类似于光刻胶的光刻掩模很容易地图案化这些感光材料。在可选实施例中，介电材料16层可以由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)等形成。在可选实施例中，第一互连层11可以包括中介层或封装衬底，诸如，硅中介层、有机衬底、层压衬底(例如，1-2-1层压衬底)等。如图1a所示，第一互连层11提供相对面之间的电连接件并可以用作再分布层(RDL)。例如，第一组外部接触焊盘17提供使用焊球19的外部电连接件。
管芯12横向封装在诸如模塑料14的介电材料中，该介电材料可以具有一个或多个定位于其中的连接块20。如图1a所示，连接块20沿着管芯12的长轴(major axis)对齐，并且模塑料14介于管芯12和连接块20之间。例如，连接块20可以包括通孔(TV)和/或集成无源器件(IPD)。通常，如下文中更详细地描述的，连接块20提供具有形成在其中的更高密度的诸如TV和/或IPD的结构的结构材料。在实施例中，连接块20包括硅、二氧化硅、玻璃和/或类似材料。
第二互连层13可以位于管芯12、模塑料14以及连接块20上方。第二互连层13可以包括具有形成在其中的导电部件(示出为导电部件9)的一个或多个介电材料18层。在实施例中，介电材料18层由感光材料形成，诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等，可以使用类似于光刻胶的光刻掩模很容易地图案化该感光材料。在可选实施例中，介电材料18层可以由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)等形成。在可选实施例中，第二互连层13可以包括中介层或封装衬底，诸如硅中介层、有机衬底、层压衬底(例如，1-2-1层压衬底)等。另外地，第二互连层13可以包括一组第二外部接触件7(通过导电部件9提供)，以连接至另一个器件，诸如管芯、管芯叠层、封装件、中介层和/或类似器件。另一个器件可以经由焊料凸块/焊球、引线接合等连接至第二外部接触件7。
如图1a所示以及下文中更详细的描述，电部件可以电耦合至第二互连层13的上表面。可以用作RDL的第二互连层13(经由导电部件9)提供那些电部件和位于连接块20中的TV/IPD之间的电连接件。第一互连层11反过来提供连接块20和管芯12和/或第一组外部接触焊盘17之间的电连接件，以及提供管芯12和第一组外部接触焊盘17之间的电连接件。可以是例如球栅阵列(BGA)的部分的焊球19可以附接至另一个衬底，诸如晶圆、封装衬底、PCB、管芯等。
诸如在图1a中所示的实施例包括连接块20，该连接块可以允许诸如通孔和IPD的结构形成在与模塑料14不同类型的材料中，从而提供不同的性能特征。连接块20可以包括将第二互连层13连接至第一互连层11的一个或多个TV，例如，硅通孔(TSV)。此外，连接块20可以包括一个或多个集成无源器件(IPD)，诸如集成电容器、集成电阻器等。在TV和IPD的情况下，硅块的使用允许更接近地设置通孔和器件。也就是说，TV和IPD的间距细度(fineness)增加，以允许通孔和无源器件集成的更大密度。在另一个实施例中，块20可以包括提供与硅相似的改进的二氧化硅(SiO2)。例如，通过使用硅或氧化硅，TV的间距可以将穿过模塑料的间距从大于100μm的减小至约60μm。
图1b示出了图1a所示的实施例的平面图。如图所示，单个管芯12位于两个连接块20之间。此外，模塑料14环绕单个管芯12和两个连接块20，从而将管芯12与两个连接块20间隔开。在这种布局中，两个连接块20为穿过模塑料14的管芯12提供额外的支撑和布线选项，从而允许更大灵活性。
图1c示出了另一个实施例的平面图，其中，利用单个管芯12以及单个连接块20。在该实施例中，管芯12和连接块20相互并排对齐，其中，连接块20沿着管芯12的单边对齐。此外，在其他实施例中，连接块20可以形成位于管芯12周围的环(或连续的或断开的)。可以可选地使用管芯12和一个或多个连接块20的任意合适的布置。
图2a描绘了连接块20的实施例。连接块20包括诸如硅、二氧化硅(SiO2)等的结构材料21。位于结构材料21中的孔形成一个或多个TV24和一个或多个集成的无源器件(IPD)22(诸如图2所示的沟槽电容器)。TV24填充有诸如金属的导电材料25，以提供从块20的第一面至块20的第二面的接触件。在IPD22包括电容器或电阻器的实施例中，IPD22可以分别地内衬导电材料25并填充有填充材料23。填充材料23包括形成集成电容器的电介质或者形成集成电阻器的电阻性材料。TV24和IPD22可以包括诸如粘附层、阻挡层等的其他部件，并且可以包括多层。
图2b至图2c示出了在另一个实施例中IPD22包括电感器29。图2b示出了在连接块20的单面上的金属化层27中形成电感器29的一个实施例。金属化层27可以形成在面对第一互连层11或者背离第一互连层11的连接块20上。可以使用合适的光刻、沉积以及诸如镶嵌工艺的抛光工艺在第一金属化层27中形成电感器29。
图2c示出了可选实施例，其中，不是在连接块20的一面上的单个金属化层27中形成电感器29，而是可以形成穿过连接块20的电感器29。例如，TV可以形成在连接块20中以提供电感器29的垂直部分，同时可以通过在位于连接块20的两面上的金属化层27中形成连接件来相互连接电感器29的垂直部分。
在连接块20由硅形成的实施例中，任意合适的半导体处理技术都可以用于形成连接块20。例如，光刻技术可以用于形成并图案化掩模以根据期望图案在硅中蚀刻通孔和沟槽。可以使用包括化学汽相沉积、原子层沉积、电镀等的合适技术用合适的导电材料、介电材料和/或电阻性材料填充沟槽。可以利用减薄技术实施晶圆减薄以沿着背面暴露TV。此后，可以实施切割工艺以形成如图2所示的连接块20。连接块20可以是诸如正方形、矩形等的任何形状。此外，可以使用一个或多个连接块20。例如，在实施例中，利用单个连接块20，而在其他实施例中，可以利用多个连接块20。连接块20可以沿着管芯12的一面或多面延伸，以及可以形成位于管芯12周围的环(或连续的或断开的)。
图3示出了封装件叠层(PoP)器件30的实施例。如下文中更详细的说明的，PoP器件30提供具有包含在连接块20中的集成或内嵌无源器件的创新的封装件叠层结构。同样地，该PoP器件30相对于标准的PoP器件提供了改进的电性能和更高的操作频率。此外，块20中TV和IPD的减小间距允许增加集成密度。如图3所示，PoP器件30通常包括通过连接至例如BGA布置中的焊球焊盘37的焊球36耦合至第一封装件10的第二封装件32。然而，可以通过诸如经由焊料凸块、引线接合等的其他方式连接第一封装件和第二封装件。
在实施例中，第二封装件32包括数个堆叠的存储芯片31。通过在图3中由参考数字35表示的例如通孔、引线接合等的可以相互电耦合存储芯片31。虽然图3示出了数个存储芯片31，但是在实施例中，第二封装件32可以包括单个存储芯片31。第二封装件32也可以根据PoP器件30的使用意向或性能需求结合其他芯片、管芯、封装件或电路。
如上所述，在图1a和图3所示的实施例中，第一互连层11包括至少一个介电材料16层。在可选实施例中，可以通过诸如硅的合适的半导体材料替换第一互连层11。如果使用硅替换介电材料16作为衬底，则钝化层和模制层可以包括在硅和BGA的焊球19之间。例如当互连层由介电材料16形成时，可以省略这些额外层。
第一封装件10也包括封装管芯12和连接块20的模塑料14。模塑料14可以由各种合适的模塑料形成。如图2所示，连接块20提供IPD和用于第一封装件10和第二封装件32之间的互连件的TV。如上所述，焊料凸块焊盘37用于安装第二封装件32并且该焊料凸块焊盘37通过内嵌在第二互连层13中或由第二互连层13支撑的导电部件9提供与连接块20中的TV或IPD的电连接件，其中，连接块20封装在模塑料14中。
图4a至图4j示出了用于形成实施例的方法的各种中间阶段。首先参考图4a，示出了具有形成在其上的剥离膜涂层46的第一载具41，例如，玻璃载具。在图4b中，连接块20和管芯12通过剥离膜涂层46附接至第一载具41的表面上。剥离膜涂层46可以包括紫外(UV)胶粘附膜，或可以由其他公知的粘附材料形成。在实施例中，剥离膜涂层46以液态形成散布到第一载具41上。在可选实施例中，剥离膜涂层46预先附接至管芯12和连接块20的背面上，然后，附接至第一载具41。
如图4b所示，连接块20可以被分别地形成并置于第一载具41上。在这个实施例中，使用诸如光刻、沉积、蚀刻、研磨、抛光等的合适的半导体处理技术，连接块20可以由诸如硅晶圆的晶圆形成，以形成用于特定应用的通孔、IPD等。连接块可以与晶圆分离并且例如如图4b所示设置连接块。
图4c示出了封装管芯12和连接块20设置的模塑料14。在实施例中，例如，模塑料14包括通过压模法形成在所示的结构上的模塑料。在另一个实施例中，可以使用含聚合物的材料，诸如PBO、聚酰亚胺、BCB等的感光材料。可以以液态形式应用模塑料14，散布该模塑料，然后进行固化。模塑料14的顶面高于管芯12和连接块20的顶面。
如图4d所示，实施包括研磨和/或抛光的晶圆减薄工艺以平坦化顶面。减薄工艺降低了并可以基本消除顶面的不均匀性。通过减薄去除包括覆盖管芯12和连接块20顶面的部分的模塑料14，从而暴露形成在连接块20中的TV和/或IPD。
在图4e中，第一互连层11形成在模塑料14、连接块20和管芯12上方。在实施例中，第一互连层11包括介电材料16和导电部件15(包括RDL)的交替层。第一互连层11的底面可以与管芯12、连接块20以及模塑料14的顶面接触。介电材料16可以包括如之前结合图1a描述的很多不同类型的材料。包括RDL的导电部件15可以包括其底部电耦合至如图2所示的连接块20中的通孔24和IPD22的下部。RDL和导电部件15也可以包括具有外部接触焊盘17的顶部区域。
根据一些实施例，第一互连层11的形成可能包括形成介电材料，蚀刻并去除介电材料的多部分，在介电材料上方形成凸块底部金属(UBM，未示出)，形成并图案化光刻胶(未示出)以覆盖UBM的多部分，以及电镀金属材料以形成第一组外部接触焊盘17。然后，去除UBM的暴露部分。第一组外部接触焊盘17可以由铜、铝、钨等形成。
图4f示出了第二载具42通过剥离膜涂层46附接至第一互连层11的正面。第二载具42的剥离膜涂层46可以类似于第一载具41的剥离膜涂层46。然后，翻转晶圆。
在图4g中，例如，通过将剥离膜涂层46暴露至UV光，导致该剥离膜涂层失去粘性来去除载具41。也去除剥离膜涂层46。可以实施任选的背面减薄工艺以减薄并且平坦化晶圆的表面，可能暴露形成在管芯12中的通孔。
图4h示出了形成在管芯12和连接块20上方的第二互连层13。第二互连层13可以由与参考图1a描述的介电材料16相似的介电材料18构建。可以以类似于第一互连层的方式形成第二互连层13。第二互连层13(在实施例中，RDL)提供连接块20中的TV和外部接触件7之间的互连件。
图4i示出了附接至晶圆背面的第三载具43。用类似于第一载具41的方式去除第二载具42。可以沿着晶圆的顶面放置焊球19，以形成与如图1a所示的第一组外部接触焊盘17接触的BGA。
最后，图4j示出了以类似于第一载具41和第二载具42的方式去除第三载具43。任选地，然后，将切割带44粘附至第二互连层13的表面。在一些实施例中，可以同时形成多个PoP。在这些实施例中，可以应用切割带并且沿线45实施切割工艺以将结构分离成如图1a所示的多个封装件。在实施例中，每个生成的结构都包括横向封装在模塑料14中的管芯12和连接块20。然后，如图3所示，生成的封装件可以通过焊球19或通过用第二组外部接触件7附接至管芯相对面的额外的焊球/凸块接合至其他封装部件(诸如封装衬底或PCB)。
在实施例中，提供具有管芯、第一材料以及第二材料的半导体器件。沿着管芯的长轴定位第二材料和第一材料。第一材料包括延伸穿过第一材料的一个或多个导电部件。
在另一个实施例中，提供包括顶部封装件和底部封装件的半导体器件。底部封装件包括管芯和通过模塑料与管芯间隔开的连接块。
在又一个实施例中，提供形成半导体器件的方法。方法包括提供管芯和具有一个或多个导电元件的连接块。形成包括通过材料层分离开的管芯和连接块的层，其中，连接块的材料不同于材料层的材料。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的主旨和范围的情况下，做各种不同的改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体器件，包括：
管芯，具有电接触件；
第一材料；以及
第二材料，介于所述管芯和所述第一材料之间，所述第二材料和所述第一材料沿着所述管芯的长轴定位，所述第一材料包括延伸穿过所述第一材料的一个或多个导电部件。
2.根据权利要求1所述的半导体器件，其中，所述第一材料是硅。
3.根据权利要求1所述的半导体器件，其中，所述第一材料是二氧化硅。
4.根据权利要求1所述的半导体器件，其中，所述一个或多个导电部件包括至少一个通孔。
5.根据权利要求1所述的半导体器件，其中，所述一个或多个导电部件包括至少一个集成无源器件。
6.根据权利要求1所述的半导体器件，进一步包括在所述管芯和所述第一材料的第一面上方延伸的第一互连层。
7.根据权利要求6所述的半导体器件，进一步包括在所述管芯和所述第一材料的第二面上方延伸的第二互连层。
8.根据权利要求1所述的半导体器件，进一步包括位于所述管芯上方的封装管芯，所述封装管芯与延伸穿过所述第一材料的一个或多个导电部件电耦合。
9.一种半导体器件，包括：
顶部封装件；以及
底部封装件，可操作地耦合至所述顶部封装件，所述底部封装件包括管芯和通过模塑料与所述管芯间隔开的连接块。
10.一种形成半导体器件的方法，所述方法包括：
提供管芯；
提供具有一个或多个导电元件的连接块；以及
形成包括通过材料层间隔开的所述管芯和所述连接块的层，所述连接块的材料不同于所述材料层的材料。
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